diff --git a/packages/devel/binutils-arm-none-eabi/package.mk b/packages/devel/binutils-arm-none-eabi/package.mk index 245647fae..8392f49bc 100644 --- a/packages/devel/binutils-arm-none-eabi/package.mk +++ b/packages/devel/binutils-arm-none-eabi/package.mk @@ -4,7 +4,7 @@ # Copyright (C) 2023 JELOS (https://github.com/JustEnoughLinuxOS) PKG_NAME="binutils-arm-none-eabi" -PKG_VERSION="" +PKG_VERSION="$(get_pkg_version binutils)" PKG_LICENSE="GPL" PKG_URL="" PKG_DEPENDS_HOST="toolchain:host" @@ -31,7 +31,7 @@ PKG_CONFIGURE_OPTS_HOST="--target=arm-none-eabi \ unpack() { mkdir -p ${PKG_BUILD} - tar --strip-components=1 -xf ${SOURCES}/binutils/binutils-${PKG_VERSION}.tar.xz -C ${PKG_BUILD} + tar --strip-components=1 -xf sources/binutils/binutils-${PKG_VERSION}.tar.xz -C ${PKG_BUILD} } pre_configure_host() { diff --git a/packages/emulators/libretro/beetle-supafaust-lr/config/Supafaust.opt b/packages/emulators/libretro/beetle-supafaust-lr/config/Supafaust.opt new file mode 100644 index 000000000..5c73e159c --- /dev/null +++ b/packages/emulators/libretro/beetle-supafaust-lr/config/Supafaust.opt @@ -0,0 +1,19 @@ +supafaust_audio_rate = "disabled" +supafaust_correct_aspect = "enabled" +supafaust_cx4_clock_rate = "100" +supafaust_deinterlacer = "bob_offset" +supafaust_frame_begin_vblank = "enabled" +supafaust_h_filter = "phr256blend_auto512" +supafaust_multitap = "disabled" +supafaust_pixel_format = "rgb565" +supafaust_region = "auto" +supafaust_renderer = "mt" +supafaust_run_ahead = "disabled" +supafaust_slend = "223" +supafaust_slendp = "238" +supafaust_slstart = "0" +supafaust_slstartp = "0" +supafaust_superfx_clock_rate = "100" +supafaust_superfx_icache = "disabled" +supafaust_thread_affinity_emu = "0x3" +supafaust_thread_affinity_ppu = "0xc" diff --git a/packages/emulators/libretro/beetle-supafaust-lr/package.mk b/packages/emulators/libretro/beetle-supafaust-lr/package.mk index a0acab616..d1753e8c3 100644 --- a/packages/emulators/libretro/beetle-supafaust-lr/package.mk +++ b/packages/emulators/libretro/beetle-supafaust-lr/package.mk @@ -38,4 +38,7 @@ PKG_AUTORECONF="no" makeinstall_target() { mkdir -p ${INSTALL}/usr/lib/libretro cp ${PKG_BUILD}/mednafen_supafaust_libretro.so ${INSTALL}/usr/lib/libretro/beetle_supafaust_libretro.so + + mkdir -p ${INSTALL}/usr/config/retroarch + cp -rf ${PKG_DIR}/config/* ${INSTALL}/usr/config/retroarch/ } diff --git a/packages/emulators/standalone/ppsspp-sa/package.mk b/packages/emulators/standalone/ppsspp-sa/package.mk index 204cf967b..fb0cca5b5 100644 --- a/packages/emulators/standalone/ppsspp-sa/package.mk +++ b/packages/emulators/standalone/ppsspp-sa/package.mk @@ -7,7 +7,7 @@ PKG_REV="1" PKG_ARCH="any" PKG_SITE="https://github.com/hrydgard/ppsspp" PKG_URL="${PKG_SITE}.git" -PKG_VERSION="53cfe5285d6b7c8959dd65bb72e6a6adf7248c74" +PKG_VERSION="58e12acee4d7829ee675ce95f3d377c3aaa3ecc5" PKG_LICENSE="GPLv2" PKG_DEPENDS_TARGET="toolchain ffmpeg libzip SDL2 zlib zip" PKG_SHORTDESC="PPSSPPDL" diff --git a/packages/jelos/sources/scripts/setsettings.sh b/packages/jelos/sources/scripts/setsettings.sh index e5b3501df..8f662f3b2 100755 --- a/packages/jelos/sources/scripts/setsettings.sh +++ b/packages/jelos/sources/scripts/setsettings.sh @@ -914,6 +914,23 @@ function set_saturnopts() { fi } +function set_snesopts() { + log "Set up SNES..." + if [ "${CORE}" = "beetle_supafaust" ] + then + log "Set up beetle_supafaust" + local FAUSTDIR="${RETROARCH_PATH}/config/Supafaust" + if [ ! -d "${FAUSTDIR}" ] + then + mkdir -p "${FAUSTDIR}" + fi + if [ ! -f "${FAUSTDIR}/Supafaust.opt" ] + then + cp "/usr/config/retroarch/Supafaust.opt" "${FAUSTDIR}/Supafaust.opt" + fi + fi +} + function set_dreamcastopts() { log "Set up Dreamcast..." if [ "${CORE}" = "flycast" ] @@ -1076,6 +1093,7 @@ set_analogsupport & set_tatemode & set_n64opts & set_saturnopts & +set_snesopts & set_dreamcastopts & ### Sed operations are expensive, so they are staged and executed as diff --git a/packages/tools/atf/package.mk b/packages/tools/atf/package.mk new file mode 100644 index 000000000..16bf0e2b2 --- /dev/null +++ b/packages/tools/atf/package.mk @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright (C) 2018-present Team LibreELEC +# Copyright (C) 2023 JELOS (https://github.com/JustEnoughLinuxOS) + +PKG_NAME="atf" +PKG_VERSION="2.10.0" +PKG_SHA256="696b8e53923aac4474532da7dd681f0bd044b329732facd65aeabea3e61adca9" +PKG_ARCH="arm aarch64" +PKG_LICENSE="BSD-3c" +PKG_SITE="https://github.com/ARM-software/arm-trusted-firmware" +PKG_URL="https://github.com/ARM-software/arm-trusted-firmware/archive/v${PKG_VERSION}.tar.gz" +PKG_DEPENDS_TARGET="toolchain" +PKG_LONGDESC="ARM Trusted Firmware is a reference implementation of secure world software, including a Secure Monitor executing at Exception Level 3 and various Arm interface standards." +PKG_TOOLCHAIN="manual" +PKG_PATCH_DIRS+="${DEVICE}" + +[ -n "${KERNEL_TOOLCHAIN}" ] && PKG_DEPENDS_TARGET+=" gcc-${KERNEL_TOOLCHAIN}:host" + +if [ "${ATF_PLATFORM}" = "rk3399" ]; then + PKG_DEPENDS_TARGET+=" gcc-arm-none-eabi:host" + export M0_CROSS_COMPILE="${TOOLCHAIN}/bin/arm-none-eabi-" +fi + +make_target() { + CROSS_COMPILE="${TARGET_KERNEL_PREFIX}" LDFLAGS="" CFLAGS="" make PLAT=${ATF_PLATFORM} bl31 +} + +makeinstall_target() { + mkdir -p ${INSTALL}/usr/share/bootloader + cp -a build/${ATF_PLATFORM}/release/${ATF_BL31_BINARY} ${INSTALL}/usr/share/bootloader +} diff --git a/packages/tools/atf/patches/RK3399/000-atf-fix-baud.patch b/packages/tools/atf/patches/RK3399/000-atf-fix-baud.patch new file mode 100644 index 000000000..06fbc195a --- /dev/null +++ b/packages/tools/atf/patches/RK3399/000-atf-fix-baud.patch @@ -0,0 +1,13 @@ +diff --git a/plat/rockchip/rk3399/rk3399_def.h b/plat/rockchip/rk3399/rk3399_def.h +index ba83242ebe..8d6ecfbe66 100644 +--- a/plat/rockchip/rk3399/rk3399_def.h ++++ b/plat/rockchip/rk3399/rk3399_def.h +@@ -17,7 +17,7 @@ + /************************************************************************** + * UART related constants + **************************************************************************/ +-#define RK3399_BAUDRATE 115200 ++#define RK3399_BAUDRATE 1500000 + #define RK3399_UART_CLOCK 24000000 + + /****************************************************************************** diff --git a/projects/Rockchip/bootloader/install b/projects/Rockchip/bootloader/install index 281e61a90..998d6bbf7 100755 --- a/projects/Rockchip/bootloader/install +++ b/projects/Rockchip/bootloader/install @@ -27,12 +27,17 @@ generate_rkspi_loader() { dd if=${PKG_BUILD}/u-boot.itb of=$RKSPI_LOADER seek=16384 conv=notrunc } + + if [ -n "${PKG_DATAFILE}" -a -n "${PKG_LOADER}" ]; then echo "loader: Make idbloader.img from ${PKG_DATAFILE}:${PKG_LOADER}..." case "${PKG_SOC}" in - rk35*|rk3399) + rk35*) tools/mkimage -n ${PKG_SOC} -T rksd -d ${PKG_DATAFILE}:${PKG_LOADER} -C bzip2 idbloader.img ;; + rk3399) + ${PKG_RKBIN}/tools/mkimage -n "${PKG_SOC}" -T rksd -d ${PKG_DATAFILE}:${PKG_LOADER} idbloader.img.rk || exit 1 + ;; *) tools/mkimage -n ${PKG_SOC} -T rksd -d "${PKG_DATAFILE}" -C bzip2 idbloader.img cat "${PKG_LOADER}" >> idbloader.img @@ -40,8 +45,12 @@ if [ -n "${PKG_DATAFILE}" -a -n "${PKG_LOADER}" ]; then esac fi -echo "uboot: copy idbloader.img image to ${INSTALL}/usr/share/bootloader..." -cp -av idbloader.img ${INSTALL}/usr/share/bootloader +case "${PKG_SOC}" in + rk35*|px30) + echo "uboot: copy idbloader.img image to ${INSTALL}/usr/share/bootloader..." + cp -av idbloader.img ${INSTALL}/usr/share/bootloader + ;; +esac if [ ! -n "${PKG_LOAD_ADDR}" ]; then PKG_LOAD_ADDR="0x00200000" @@ -53,6 +62,18 @@ case "${PKG_SOC}" in cp -av u-boot.itb ${INSTALL}/usr/share/bootloader/u-boot.itb generate_rkspi_loader ;; + rk3399) + PKG_ATF_INI="${PKG_RKBIN}"/RKTRUST/"${DEVICE}"TRUST.ini + echo "uboot: building ${UBOOT_FIT_IMAGE}..." + ${PKG_RKBIN}/tools/loaderimage --pack --uboot u-boot-dtb.bin uboot.img.rk "${PKG_LOAD_ADDR}" || exit 1 + dd if=idbloader.img.rk of="${UBOOT_FIT_IMAGE}" seek=0 conv=fsync,notrunc > /dev/null 2>&1 || exit 1 + dd if=uboot.img.rk of="${UBOOT_FIT_IMAGE}" seek=16320 conv=fsync,notrunc > /dev/null 2>&1 || exit 1 + "${PKG_RKBIN}"/tools/trust_merger --ignore-bl32 --prepath "${PKG_RKBIN}"/ "${PKG_ATF_INI}" || exit 1 + dd if=trust.img of="${UBOOT_FIT_IMAGE}" seek=24512 conv=fsync,notrunc > /dev/null 2>&1 || exit 1 + + echo "uboot: copy ${UBOOT_FIT_IMAGE} to ${INSTALL}/usr/share/bootloader..." + cp -av ${UBOOT_FIT_IMAGE} ${INSTALL}/usr/share/bootloader + ;; *) echo "uboot: build loader image uboot.img at ${PKG_LOAD_ADDR}..." ${PKG_UBOOT}/tools/loaderimage --pack --uboot u-boot-dtb.bin uboot.img ${PKG_LOAD_ADDR} ||: @@ -61,7 +82,7 @@ case "${PKG_SOC}" in esac case "${DEVICE}" in - RK33*) + RK3326) if [ -n "${PKG_BL31}" ]; then echo "trust: create trust.ini..." cat >trust.ini <"${SAVE_ERROR}" 2>&1 || show_error - fi - if [ -f "${RELEASE_DIR}/3rdparty/bootloader/trust.img" ]; then - echo "image: burn trust.img to image..." - dd if="${RELEASE_DIR}/3rdparty/bootloader/trust.img" of="${DISK}" bs=512 seek=24576 conv=sync,noerror,notrunc >"${SAVE_ERROR}" 2>&1 || show_error - elif [ -f "${RELEASE_DIR}/3rdparty/bootloader/resource.img" ]; then - echo "image: burn resource.img to image..." - dd if="${RELEASE_DIR}/3rdparty/bootloader/resource.img" of="${DISK}" bs=512 seek=24576 conv=sync,noerror,notrunc >"${SAVE_ERROR}" 2>&1 || show_error - fi + if [ -f "${RELEASE_DIR}/3rdparty/bootloader/u-boot.itb" ]; then + echo "image: burn uboot.itb to image... (${PKG_SOC})" + dd if="${RELEASE_DIR}/3rdparty/bootloader/u-boot.itb" of="${DISK}" bs=512 seek=16384 conv=sync,noerror,notrunc >"${SAVE_ERROR}" 2>&1 || show_error + fi + if [ -f "${RELEASE_DIR}/3rdparty/bootloader/trust.img" ]; then + echo "image: burn trust.img to image..." + dd if="${RELEASE_DIR}/3rdparty/bootloader/trust.img" of="${DISK}" bs=512 seek=24576 conv=sync,noerror,notrunc >"${SAVE_ERROR}" 2>&1 || show_error + elif [ -f "${RELEASE_DIR}/3rdparty/bootloader/resource.img" ]; then + echo "image: burn resource.img to image..." + dd if="${RELEASE_DIR}/3rdparty/bootloader/resource.img" of="${DISK}" bs=512 seek=24576 conv=sync,noerror,notrunc >"${SAVE_ERROR}" 2>&1 || show_error + fi + ;; + rk3399) + if [ -f "${RELEASE_DIR}/3rdparty/bootloader/rk3399-uboot.bin" ]; then + echo "image: burn u-boot.bin to image..." + dd if="${RELEASE_DIR}/3rdparty/bootloader/rk3399-uboot.bin" of="${DISK}" bs=512 seek=64 conv=sync,noerror,notrunc >"${SAVE_ERROR}" 2>&1 || show_error + fi ;; *) if [ -f "${RELEASE_DIR}/3rdparty/bootloader/uboot.img" ]; then diff --git a/projects/Rockchip/bootloader/release b/projects/Rockchip/bootloader/release index 4e42f9f31..2b98b8197 100755 --- a/projects/Rockchip/bootloader/release +++ b/projects/Rockchip/bootloader/release @@ -18,6 +18,11 @@ if [ -n "${UBOOT_CONFIG}" ]; then cp -a ${KERNEL_DIR}/resource.img ${RELEASE_DIR}/3rdparty/bootloader fi ;; + rk3399) + if [ -f ${BOOTLOADER_DIR}/rk3399-uboot.bin ]; then + cp -a ${BOOTLOADER_DIR}/rk3399-uboot.bin ${RELEASE_DIR}/3rdparty/bootloader + fi + ;; *) if [ -f ${BOOTLOADER_DIR}/uboot.img ]; then cp -a ${BOOTLOADER_DIR}/uboot.img ${RELEASE_DIR}/3rdparty/bootloader diff --git a/projects/Rockchip/bootloader/update.sh b/projects/Rockchip/bootloader/update.sh index 97a37ea67..19963273a 100755 --- a/projects/Rockchip/bootloader/update.sh +++ b/projects/Rockchip/bootloader/update.sh @@ -105,6 +105,11 @@ if [ -f $SYSTEM_ROOT/usr/share/bootloader/uboot.img ]; then dd if=$SYSTEM_ROOT/usr/share/bootloader/uboot.img of=$BOOT_DISK bs=512 seek=16384 conv=fsync &>/dev/null echo "done" fi +if [ -f $SYSTEM_ROOT/usr/share/bootloader/rk3399-uboot.bin ]; then + echo -n "Updating uboot.bin... " + dd if=$SYSTEM_ROOT/usr/share/bootloader/rk3399-uboot.bin of=$BOOT_DISK bs=512 seek=64 conv=fsync &>/dev/null + echo "done" +fi if [ -f $SYSTEM_ROOT/usr/share/bootloader/u-boot.itb ]; then echo -n "Updating uboot.itb... " dd if=$SYSTEM_ROOT/usr/share/bootloader/u-boot.itb of=$BOOT_DISK bs=512 seek=16384 conv=fsync &>/dev/null diff --git a/projects/Rockchip/devices/RK3399/linux/linux.aarch64.conf b/projects/Rockchip/devices/RK3399/linux/linux.aarch64.conf index f48cfb679..71ab7b73a 100644 --- a/projects/Rockchip/devices/RK3399/linux/linux.aarch64.conf +++ b/projects/Rockchip/devices/RK3399/linux/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 6.1.68 Kernel Configuration +# Linux/arm64 6.7.0 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-libreelec-linux-gnueabi-gcc-12.3.0 (GCC) 12.3.0" CONFIG_CC_IS_GCC=y @@ -58,7 +58,6 @@ CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_GENERIC_IRQ_IPI=y CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y CONFIG_IRQ_MSI_IOMMU=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_SPARSE_IRQ=y @@ -125,7 +124,6 @@ CONFIG_CPU_ISOLATION=y # CONFIG_TREE_RCU=y # CONFIG_RCU_EXPERT is not set -CONFIG_SRCU=y CONFIG_TREE_SRCU=y CONFIG_TASKS_RCU_GENERIC=y CONFIG_TASKS_TRACE_RCU=y @@ -138,7 +136,6 @@ CONFIG_IKCONFIG_PROC=y # CONFIG_IKHEADERS is not set CONFIG_LOG_BUF_SHIFT=18 CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 -CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 # CONFIG_PRINTK_INDEX is not set CONFIG_GENERIC_SCHED_CLOCK=y @@ -149,6 +146,7 @@ CONFIG_GENERIC_SCHED_CLOCK=y # end of Scheduler features CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y CONFIG_CC_HAS_INT128=y CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" CONFIG_GCC11_NO_ARRAY_BOUNDS=y @@ -165,6 +163,7 @@ CONFIG_CGROUP_SCHED=y CONFIG_FAIR_GROUP_SCHED=y # CONFIG_CFS_BANDWIDTH is not set # CONFIG_RT_GROUP_SCHED is not set +CONFIG_SCHED_MM_CID=y CONFIG_CGROUP_PIDS=y # CONFIG_CGROUP_RDMA is not set # CONFIG_CGROUP_FREEZER is not set @@ -186,7 +185,6 @@ CONFIG_PID_NS=y CONFIG_NET_NS=y # CONFIG_CHECKPOINT_RESTORE is not set CONFIG_SCHED_AUTOGROUP=y -# CONFIG_SYSFS_DEPRECATED is not set CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="@INITRAMFS_SOURCE@" @@ -212,6 +210,7 @@ CONFIG_INITRAMFS_PRESERVE_MTIME=y CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_LD_ORPHAN_WARN=y +CONFIG_LD_ORPHAN_WARN_LEVEL="warn" CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y CONFIG_SYSCTL_EXCEPTION_TRACE=y @@ -238,13 +237,14 @@ CONFIG_IO_URING=y CONFIG_ADVISE_SYSCALLS=y CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_SELFTEST is not set # CONFIG_KALLSYMS_ALL is not set CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_KCMP=y CONFIG_RSEQ=y +CONFIG_CACHESTAT_SYSCALL=y # CONFIG_DEBUG_RSEQ is not set -CONFIG_EMBEDDED=y CONFIG_HAVE_PERF_EVENTS=y # CONFIG_PC104 is not set @@ -257,10 +257,18 @@ CONFIG_PERF_EVENTS=y CONFIG_SYSTEM_DATA_VERIFICATION=y CONFIG_PROFILING=y + +# +# Kexec and crash features +# +# CONFIG_KEXEC is not set +# CONFIG_KEXEC_FILE is not set +# CONFIG_CRASH_DUMP is not set +# end of Kexec and crash features # end of General setup CONFIG_ARM64=y -CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y CONFIG_64BIT=y CONFIG_MMU=y CONFIG_ARM64_PAGE_SHIFT=12 @@ -279,13 +287,13 @@ CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CSUM=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y CONFIG_SMP=y CONFIG_KERNEL_MODE_NEON=y CONFIG_FIX_EARLYCON_MEM=y CONFIG_PGTABLE_LEVELS=4 CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y # # Platform selection @@ -307,13 +315,16 @@ CONFIG_ARCH_PROC_KCORE_TEXT=y # CONFIG_ARCH_MESON is not set # CONFIG_ARCH_MVEBU is not set # CONFIG_ARCH_NXP is not set +# CONFIG_ARCH_MA35 is not set # CONFIG_ARCH_NPCM is not set +# CONFIG_ARCH_PENSANDO is not set # CONFIG_ARCH_QCOM is not set # CONFIG_ARCH_REALTEK is not set # CONFIG_ARCH_RENESAS is not set CONFIG_ARCH_ROCKCHIP=y # CONFIG_ARCH_SEATTLE is not set # CONFIG_ARCH_INTEL_SOCFPGA is not set +# CONFIG_ARCH_STM32 is not set # CONFIG_ARCH_SYNQUACER is not set # CONFIG_ARCH_TEGRA is not set # CONFIG_ARCH_SPRD is not set @@ -361,7 +372,8 @@ CONFIG_ARM64_ERRATUM_1319367=y # CONFIG_ARM64_ERRATUM_2054223 is not set # CONFIG_ARM64_ERRATUM_2067961 is not set # CONFIG_ARM64_ERRATUM_2441009 is not set -CONFIG_ARM64_ERRATUM_2966298=y +# CONFIG_ARM64_ERRATUM_2645198 is not set +# CONFIG_ARM64_ERRATUM_2966298 is not set # CONFIG_CAVIUM_ERRATUM_22375 is not set # CONFIG_CAVIUM_ERRATUM_23154 is not set # CONFIG_CAVIUM_ERRATUM_27456 is not set @@ -374,6 +386,7 @@ CONFIG_ARM64_ERRATUM_2966298=y # CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set # CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set # CONFIG_NVIDIA_CARMEL_CNP_ERRATUM is not set +# CONFIG_ROCKCHIP_ERRATUM_3588001 is not set # CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set # end of ARM errata workarounds via the alternatives framework @@ -404,12 +417,15 @@ CONFIG_HW_PERF_EVENTS=y CONFIG_CC_HAVE_SHADOW_CALL_STACK=y # CONFIG_PARAVIRT is not set # CONFIG_PARAVIRT_TIME_ACCOUNTING is not set -# CONFIG_KEXEC is not set -# CONFIG_KEXEC_FILE is not set -# CONFIG_CRASH_DUMP is not set +CONFIG_ARCH_SUPPORTS_KEXEC=y +CONFIG_ARCH_SUPPORTS_KEXEC_FILE=y +CONFIG_ARCH_SUPPORTS_KEXEC_SIG=y +CONFIG_ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG=y +CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y +CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y CONFIG_TRANS_TABLE=y # CONFIG_XEN is not set -CONFIG_ARCH_FORCE_MAX_ORDER=11 +CONFIG_ARCH_FORCE_MAX_ORDER=10 CONFIG_UNMAP_KERNEL_AT_EL0=y CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y CONFIG_RODATA_FULL_DEFAULT_ENABLED=y @@ -425,8 +441,9 @@ CONFIG_KUSER_HELPERS=y # # CONFIG_ARM64_HW_AFDBM is not set # CONFIG_ARM64_PAN is not set -CONFIG_AS_HAS_LDAPR=y CONFIG_AS_HAS_LSE_ATOMICS=y +CONFIG_ARM64_LSE_ATOMICS=y +CONFIG_ARM64_USE_LSE_ATOMICS=y # end of ARMv8.1 architectural features # @@ -445,8 +462,9 @@ CONFIG_AS_HAS_SHA3=y # CONFIG_ARM64_PTR_AUTH is not set CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y -CONFIG_AS_HAS_PAC=y +CONFIG_AS_HAS_ARMV8_3=y CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y +CONFIG_AS_HAS_LDAPR=y # end of ARMv8.3 architectural features # @@ -474,13 +492,11 @@ CONFIG_ARM64_AS_HAS_MTE=y CONFIG_ARM64_SVE=y CONFIG_ARM64_SME=y -CONFIG_ARM64_MODULE_PLTS=y # CONFIG_ARM64_PSEUDO_NMI is not set CONFIG_RELOCATABLE=y # CONFIG_RANDOMIZE_BASE is not set CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y CONFIG_STACKPROTECTOR_PER_TASK=y -CONFIG_ARCH_NR_GPIO=0 # end of Kernel Features # @@ -577,6 +593,8 @@ CONFIG_HAVE_KVM=y # # General architecture-dependent options # +CONFIG_HOTPLUG_CORE_SYNC=y +CONFIG_HOTPLUG_CORE_SYNC_DEAD=y # CONFIG_KPROBES is not set # CONFIG_JUMP_LABEL is not set CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y @@ -609,7 +627,9 @@ CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y CONFIG_MMU_GATHER_TABLE_FREE=y CONFIG_MMU_GATHER_RCU_TABLE_FREE=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y +CONFIG_ARCH_HAS_NMI_SAFE_THIS_CPU_OPS=y CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y CONFIG_HAVE_CMPXCHG_LOCAL=y CONFIG_HAVE_CMPXCHG_DOUBLE=y @@ -684,11 +704,14 @@ CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y CONFIG_HAVE_GCC_PLUGINS=y CONFIG_GCC_PLUGINS=y # CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set +CONFIG_FUNCTION_ALIGNMENT_4B=y +CONFIG_FUNCTION_ALIGNMENT=4 # end of General architecture-dependent options CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 CONFIG_MODULES=y +# CONFIG_MODULE_DEBUG is not set # CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set @@ -744,7 +767,6 @@ CONFIG_EFI_PARTITION=y # CONFIG_CMDLINE_PARTITION is not set # end of Partition Types -CONFIG_BLOCK_COMPAT=y CONFIG_BLK_PM=y # @@ -842,18 +864,20 @@ CONFIG_SWAP=y # CONFIG_ZSWAP is not set CONFIG_ZSMALLOC=y # CONFIG_ZSMALLOC_STAT is not set +CONFIG_ZSMALLOC_CHAIN_SIZE=8 # # SLAB allocator options # -# CONFIG_SLAB is not set +# CONFIG_SLAB_DEPRECATED is not set CONFIG_SLUB=y -# CONFIG_SLOB is not set +# CONFIG_SLUB_TINY is not set # CONFIG_SLAB_MERGE_DEFAULT is not set # CONFIG_SLAB_FREELIST_RANDOM is not set # CONFIG_SLAB_FREELIST_HARDENED is not set # CONFIG_SLUB_STATS is not set # CONFIG_SLUB_CPU_PARTIAL is not set +# CONFIG_RANDOM_KMALLOC_CACHES is not set # end of SLAB allocator options # CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set @@ -868,11 +892,13 @@ CONFIG_EXCLUSIVE_SYSTEM_RAM=y CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y # CONFIG_MEMORY_HOTPLUG is not set +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y # CONFIG_COMPACTION is not set # CONFIG_PAGE_REPORTING is not set CONFIG_MIGRATION=y +CONFIG_PCP_BATCH_SCALE_MAX=5 CONFIG_PHYS_ADDR_T_64BIT=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 @@ -893,10 +919,15 @@ CONFIG_ZONE_DMA32=y # CONFIG_VM_EVENT_COUNTERS is not set # CONFIG_PERCPU_STATS is not set # CONFIG_GUP_TEST is not set +# CONFIG_DMAPOOL_TEST is not set CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_MEMFD_CREATE=y +CONFIG_SECRETMEM=y # CONFIG_ANON_VMA_NAME is not set # CONFIG_USERFAULTFD is not set # CONFIG_LRU_GEN is not set +CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK=y +CONFIG_PER_VMA_LOCK=y CONFIG_LOCK_MM_AND_FIND_VMA=y # @@ -910,6 +941,7 @@ CONFIG_NET=y CONFIG_COMPAT_NETLINK_MESSAGES=y CONFIG_NET_INGRESS=y CONFIG_NET_EGRESS=y +CONFIG_NET_XGRESS=y CONFIG_SKB_EXTENSIONS=y # @@ -949,6 +981,7 @@ CONFIG_INET_TUNNEL=m # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_TCP_SIGPOOL=y CONFIG_TCP_MD5SIG=y CONFIG_IPV6=m # CONFIG_IPV6_ROUTER_PREF is not set @@ -984,6 +1017,7 @@ CONFIG_BRIDGE_NETFILTER=m CONFIG_NETFILTER_INGRESS=y CONFIG_NETFILTER_EGRESS=y CONFIG_NETFILTER_FAMILY_BRIDGE=y +CONFIG_NETFILTER_BPF_LINK=y # CONFIG_NETFILTER_NETLINK_ACCT is not set # CONFIG_NETFILTER_NETLINK_QUEUE is not set # CONFIG_NETFILTER_NETLINK_LOG is not set @@ -1123,7 +1157,6 @@ CONFIG_IP_NF_TARGET_MASQUERADE=m # CONFIG_IP_NF_TARGET_NETMAP is not set # CONFIG_IP_NF_TARGET_REDIRECT is not set CONFIG_IP_NF_MANGLE=m -# CONFIG_IP_NF_TARGET_CLUSTERIP is not set # CONFIG_IP_NF_TARGET_ECN is not set # CONFIG_IP_NF_TARGET_TTL is not set # CONFIG_IP_NF_RAW is not set @@ -1181,6 +1214,7 @@ CONFIG_DNS_RESOLVER=y # CONFIG_QRTR is not set # CONFIG_NET_NCSI is not set CONFIG_PCPU_DEV_REFCNT=y +CONFIG_MAX_SKB_FRAGS=17 CONFIG_RPS=y CONFIG_RFS_ACCEL=y CONFIG_SOCK_RX_QUEUE_MAPPING=y @@ -1209,6 +1243,7 @@ CONFIG_BT_RFCOMM=y CONFIG_BT_HIDP=y CONFIG_BT_HS=y CONFIG_BT_LE=y +CONFIG_BT_LE_L2CAP_ECRED=y # CONFIG_BT_LEDS is not set # CONFIG_BT_MSFTEXT is not set # CONFIG_BT_AOSPEXT is not set @@ -1224,6 +1259,7 @@ CONFIG_BT_RTL=m CONFIG_BT_MTK=m CONFIG_BT_HCIBTUSB=m CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y +CONFIG_BT_HCIBTUSB_POLL_SYNC=y CONFIG_BT_HCIBTUSB_BCM=y CONFIG_BT_HCIBTUSB_MTK=y CONFIG_BT_HCIBTUSB_RTL=y @@ -1235,7 +1271,7 @@ CONFIG_BT_HCIUART_H4=y # CONFIG_BT_HCIUART_BCSP is not set # CONFIG_BT_HCIUART_ATH3K is not set # CONFIG_BT_HCIUART_LL is not set -# CONFIG_BT_HCIUART_3WIRE is not set +CONFIG_BT_HCIUART_3WIRE=y # CONFIG_BT_HCIUART_INTEL is not set # CONFIG_BT_HCIUART_BCM is not set CONFIG_BT_HCIUART_RTL=y @@ -1250,6 +1286,7 @@ CONFIG_BT_HCIBFUSB=m # CONFIG_BT_ATH3K is not set # CONFIG_BT_MTKSDIO is not set # CONFIG_BT_MTKUART is not set +# CONFIG_BT_NXPUART is not set # end of Bluetooth device drivers # CONFIG_AF_RXRPC is not set @@ -1270,10 +1307,6 @@ CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y # CONFIG_CFG80211_DEBUGFS is not set # CONFIG_CFG80211_CRDA_SUPPORT is not set CONFIG_CFG80211_WEXT=y -CONFIG_LIB80211=m -CONFIG_LIB80211_CRYPT_WEP=m -CONFIG_LIB80211_CRYPT_CCMP=m -# CONFIG_LIB80211_DEBUG is not set CONFIG_MAC80211=m CONFIG_MAC80211_HAS_RC=y CONFIG_MAC80211_RC_MINSTREL=y @@ -1281,7 +1314,6 @@ CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" # CONFIG_MAC80211_MESH is not set CONFIG_MAC80211_LEDS=y -# CONFIG_MAC80211_DEBUGFS is not set # CONFIG_MAC80211_MESSAGE_TRACING is not set # CONFIG_MAC80211_DEBUG_MENU is not set CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 @@ -1327,6 +1359,7 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # Firmware loader # CONFIG_FW_LOADER=y +CONFIG_FW_LOADER_DEBUG=y CONFIG_EXTRA_FIRMWARE="" # CONFIG_FW_LOADER_USER_HELPER is not set # CONFIG_FW_LOADER_COMPRESS is not set @@ -1351,18 +1384,23 @@ CONFIG_REGMAP_IRQ=y CONFIG_DMA_SHARED_BUFFER=y # CONFIG_DMA_FENCE_TRACE is not set CONFIG_GENERIC_ARCH_TOPOLOGY=y +# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set # end of Generic Driver Options # # Bus devices # -# CONFIG_BRCMSTB_GISB_ARB is not set # CONFIG_MOXTET is not set # CONFIG_VEXPRESS_CONFIG is not set # CONFIG_MHI_BUS is not set # CONFIG_MHI_BUS_EP is not set # end of Bus devices +# +# Cache Drivers +# +# end of Cache Drivers + # CONFIG_CONNECTOR is not set # @@ -1373,12 +1411,14 @@ CONFIG_GENERIC_ARCH_TOPOLOGY=y # ARM System Control and Management Interface Protocol # CONFIG_ARM_SCMI_PROTOCOL=y +# CONFIG_ARM_SCMI_RAW_MODE_SUPPORT is not set CONFIG_ARM_SCMI_HAVE_TRANSPORT=y CONFIG_ARM_SCMI_HAVE_SHMEM=y CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y CONFIG_ARM_SCMI_TRANSPORT_SMC=y # CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set CONFIG_ARM_SCMI_POWER_DOMAIN=y +CONFIG_ARM_SCMI_PERF_DOMAIN=y # CONFIG_ARM_SCMI_POWER_CONTROL is not set # end of ARM System Control and Management Interface Protocol @@ -1389,6 +1429,12 @@ CONFIG_ARM_SCPI_POWER_DOMAIN=y # CONFIG_GOOGLE_FIRMWARE is not set CONFIG_ARM_PSCI_FW=y # CONFIG_ARM_PSCI_CHECKER is not set + +# +# Qualcomm firmware drivers +# +# end of Qualcomm firmware drivers + CONFIG_HAVE_ARM_SMCCC=y CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y # CONFIG_ARM_SMCCC_SOC_ID is not set @@ -1423,6 +1469,7 @@ CONFIG_ZRAM_DEF_COMP_LZORLE=y CONFIG_ZRAM_DEF_COMP="lzo-rle" # CONFIG_ZRAM_WRITEBACK is not set # CONFIG_ZRAM_MEMORY_TRACKING is not set +# CONFIG_ZRAM_MULTI_COMP is not set CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 # CONFIG_BLK_DEV_DRBD is not set @@ -1469,7 +1516,6 @@ CONFIG_BLK_DEV_NBD=m # # CONFIG_EEPROM_AT24 is not set # CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_LEGACY is not set # CONFIG_EEPROM_MAX6875 is not set CONFIG_EEPROM_93CX6=m # CONFIG_EEPROM_93XX46 is not set @@ -1558,11 +1604,13 @@ CONFIG_TUN=m CONFIG_TUN_VNET_CROSS_LE=y CONFIG_VETH=m CONFIG_NLMON=m +# CONFIG_NETKIT is not set # CONFIG_ETHERNET is not set CONFIG_PHYLINK=y CONFIG_PHYLIB=y CONFIG_SWPHY=y # CONFIG_LED_TRIGGER_PHY is not set +CONFIG_PHYLIB_LEDS=y CONFIG_FIXED_PHY=y # CONFIG_SFP is not set @@ -1588,17 +1636,21 @@ CONFIG_AX88796B_PHY=y # CONFIG_LSI_ET1011C_PHY is not set # CONFIG_MARVELL_PHY is not set # CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MARVELL_88Q2XXX_PHY is not set # CONFIG_MARVELL_88X2222_PHY is not set # CONFIG_MAXLINEAR_GPHY is not set # CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MICREL_PHY is not set +# CONFIG_MICROCHIP_T1S_PHY is not set # CONFIG_MICROCHIP_PHY is not set # CONFIG_MICROCHIP_T1_PHY is not set # CONFIG_MICROSEMI_PHY is not set # CONFIG_MOTORCOMM_PHY is not set # CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_CBTX_PHY is not set # CONFIG_NXP_C45_TJA11XX_PHY is not set # CONFIG_NXP_TJA11XX_PHY is not set +# CONFIG_NCN26000_PHY is not set # CONFIG_AT803X_PHY is not set # CONFIG_QSEMI_PHY is not set # CONFIG_REALTEK_PHY is not set @@ -1708,6 +1760,14 @@ CONFIG_RTL8192C_COMMON=m CONFIG_RTL8XXXU=m CONFIG_RTL8XXXU_UNTESTED=y CONFIG_RTW88=m +# CONFIG_RTW88_8822BS is not set +# CONFIG_RTW88_8822BU is not set +# CONFIG_RTW88_8822CS is not set +# CONFIG_RTW88_8822CU is not set +# CONFIG_RTW88_8723DS is not set +# CONFIG_RTW88_8723DU is not set +# CONFIG_RTW88_8821CS is not set +# CONFIG_RTW88_8821CU is not set CONFIG_RTW89=m # CONFIG_WLAN_VENDOR_RSI is not set # CONFIG_WLAN_VENDOR_SILABS is not set @@ -1715,8 +1775,8 @@ CONFIG_RTW89=m # CONFIG_WLAN_VENDOR_TI is not set # CONFIG_WLAN_VENDOR_ZYDAS is not set # CONFIG_WLAN_VENDOR_QUANTENNA is not set -# CONFIG_MAC80211_HWSIM is not set # CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_MAC80211_HWSIM is not set # CONFIG_VIRT_WIFI is not set # CONFIG_WAN is not set @@ -1842,6 +1902,7 @@ CONFIG_INPUT_TOUCHSCREEN=y # CONFIG_TOUCHSCREEN_CY8CTMG110 is not set # CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set # CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set +# CONFIG_TOUCHSCREEN_CYTTSP5 is not set # CONFIG_TOUCHSCREEN_DYNAPRO is not set # CONFIG_TOUCHSCREEN_HAMPSHIRE is not set # CONFIG_TOUCHSCREEN_EETI is not set @@ -1852,6 +1913,7 @@ CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_GOODIX=y # CONFIG_TOUCHSCREEN_HIDEEP is not set # CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set +# CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX is not set # CONFIG_TOUCHSCREEN_ILI210X is not set # CONFIG_TOUCHSCREEN_ILITEK is not set # CONFIG_TOUCHSCREEN_S6SY761 is not set @@ -1867,10 +1929,10 @@ CONFIG_TOUCHSCREEN_GOODIX=y # CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set # CONFIG_TOUCHSCREEN_MSG2638 is not set # CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_NOVATEK_NVT_TS is not set # CONFIG_TOUCHSCREEN_IMAGIS is not set # CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set # CONFIG_TOUCHSCREEN_INEXIO is not set -# CONFIG_TOUCHSCREEN_MK712 is not set # CONFIG_TOUCHSCREEN_PENMOUNT is not set # CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set @@ -1896,7 +1958,9 @@ CONFIG_TOUCHSCREEN_GOODIX=y # CONFIG_TOUCHSCREEN_COLIBRI_VF50 is not set # CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set # CONFIG_TOUCHSCREEN_IQS5XX is not set +# CONFIG_TOUCHSCREEN_IQS7211 is not set # CONFIG_TOUCHSCREEN_ZINITIX is not set +# CONFIG_TOUCHSCREEN_HIMAX_HX83112B is not set CONFIG_INPUT_MISC=y # CONFIG_INPUT_AD714X is not set # CONFIG_INPUT_ATMEL_CAPTOUCH is not set @@ -1951,6 +2015,7 @@ CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set +CONFIG_LEGACY_TIOCSTI=y CONFIG_LDISC_AUTOLOAD=y # @@ -1981,7 +2046,7 @@ CONFIG_SERIAL_OF_PLATFORM=y # # CONFIG_SERIAL_AMBA_PL010 is not set # CONFIG_SERIAL_AMBA_PL011 is not set -# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_EARLYCON_SEMIHOST is not set # CONFIG_SERIAL_MAX3100 is not set # CONFIG_SERIAL_MAX310X is not set # CONFIG_SERIAL_UARTLITE is not set @@ -2017,11 +2082,10 @@ CONFIG_HW_RANDOM=y # CONFIG_HW_RANDOM_XIPHERA is not set CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=y CONFIG_DEVMEM=y +CONFIG_DEVPORT=y # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set # CONFIG_XILLYUSB is not set -CONFIG_RANDOM_TRUST_CPU=y -# CONFIG_RANDOM_TRUST_BOOTLOADER is not set # end of Character devices # @@ -2049,7 +2113,6 @@ CONFIG_I2C_MUX=y # end of Multiplexer I2C Chip support CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_ALGOBIT=y # # I2C Hardware Bus support @@ -2060,9 +2123,13 @@ CONFIG_I2C_ALGOBIT=y # # CONFIG_I2C_CADENCE is not set # CONFIG_I2C_CBUS_GPIO is not set -# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +CONFIG_I2C_DESIGNWARE_CORE=y +# CONFIG_I2C_DESIGNWARE_SLAVE is not set +CONFIG_I2C_DESIGNWARE_PLATFORM=y +# CONFIG_I2C_DESIGNWARE_PCI is not set # CONFIG_I2C_EMEV2 is not set # CONFIG_I2C_GPIO is not set +# CONFIG_I2C_HISI is not set # CONFIG_I2C_NOMADIK is not set # CONFIG_I2C_OCORES is not set # CONFIG_I2C_PCA_PLATFORM is not set @@ -2096,7 +2163,7 @@ CONFIG_I2C_RK3X=y CONFIG_SPI=y # CONFIG_SPI_DEBUG is not set CONFIG_SPI_MASTER=y -# CONFIG_SPI_MEM is not set +CONFIG_SPI_MEM=y # # SPI Master Controller Drivers @@ -2107,15 +2174,14 @@ CONFIG_SPI_BITBANG=y # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set # CONFIG_SPI_DESIGNWARE is not set -# CONFIG_SPI_NXP_FLEXSPI is not set -# CONFIG_SPI_GPIO is not set +CONFIG_SPI_GPIO=y # CONFIG_SPI_FSL_SPI is not set # CONFIG_SPI_MICROCHIP_CORE is not set # CONFIG_SPI_MICROCHIP_CORE_QSPI is not set # CONFIG_SPI_OC_TINY is not set # CONFIG_SPI_PL022 is not set CONFIG_SPI_ROCKCHIP=y -# CONFIG_SPI_ROCKCHIP_SFC is not set +CONFIG_SPI_ROCKCHIP_SFC=y # CONFIG_SPI_SC18IS602 is not set # CONFIG_SPI_SIFIVE is not set # CONFIG_SPI_MXIC is not set @@ -2127,7 +2193,7 @@ CONFIG_SPI_ROCKCHIP=y # # SPI Multiplexer support # -# CONFIG_SPI_MUX is not set +CONFIG_SPI_MUX=y # # SPI Protocol Masters @@ -2165,6 +2231,7 @@ CONFIG_PTP_1588_CLOCK_OPTIONAL=y # CONFIG_PTP_1588_CLOCK_KVM is not set # CONFIG_PTP_1588_CLOCK_IDT82P33 is not set # CONFIG_PTP_1588_CLOCK_IDTCM is not set +# CONFIG_PTP_1588_CLOCK_MOCK is not set # end of PTP clock support CONFIG_PINCTRL=y @@ -2193,7 +2260,7 @@ CONFIG_GPIOLIB=y CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_OF_GPIO=y CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_DEBUG_GPIO=y +# CONFIG_DEBUG_GPIO is not set CONFIG_GPIO_SYSFS=y CONFIG_GPIO_CDEV=y CONFIG_GPIO_CDEV_V1=y @@ -2209,6 +2276,7 @@ CONFIG_GPIO_DWAPB=y # CONFIG_GPIO_FTGPIO010 is not set CONFIG_GPIO_GENERIC_PLATFORM=y # CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_HISI is not set # CONFIG_GPIO_HLWD is not set # CONFIG_GPIO_LOGICVC is not set # CONFIG_GPIO_MB86S7X is not set @@ -2225,6 +2293,8 @@ CONFIG_GPIO_ROCKCHIP=y # I2C GPIO expanders # # CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_FXL6408 is not set +# CONFIG_GPIO_DS4520 is not set # CONFIG_GPIO_GW_PLD is not set # CONFIG_GPIO_MAX7300 is not set # CONFIG_GPIO_MAX732X is not set @@ -2259,13 +2329,13 @@ CONFIG_GPIO_ROCKCHIP=y # Virtual GPIO drivers # # CONFIG_GPIO_AGGREGATOR is not set +# CONFIG_GPIO_LATCH is not set # CONFIG_GPIO_MOCKUP is not set # CONFIG_GPIO_SIM is not set # end of Virtual GPIO drivers # CONFIG_W1 is not set CONFIG_POWER_RESET=y -# CONFIG_POWER_RESET_BRCMSTB is not set CONFIG_POWER_RESET_GPIO=y CONFIG_POWER_RESET_GPIO_RESTART=y # CONFIG_POWER_RESET_LTC2952 is not set @@ -2280,7 +2350,6 @@ CONFIG_SYSCON_REBOOT_MODE=y CONFIG_POWER_SUPPLY=y # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y -# CONFIG_PDA_POWER is not set # CONFIG_GENERIC_ADC_BATTERY is not set # CONFIG_IP5XXX_POWER is not set # CONFIG_TEST_POWER is not set @@ -2319,9 +2388,12 @@ CONFIG_CHARGER_GPIO=y # CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_RT5033 is not set # CONFIG_CHARGER_RT9455 is not set +# CONFIG_CHARGER_RT9467 is not set +# CONFIG_CHARGER_RT9471 is not set # CONFIG_CHARGER_UCS1002 is not set # CONFIG_CHARGER_BD99954 is not set # CONFIG_BATTERY_UG3105 is not set +# CONFIG_FUEL_GAUGE_MM8013 is not set CONFIG_HWMON=y # CONFIG_HWMON_DEBUG_CHIP is not set @@ -2365,15 +2437,18 @@ CONFIG_HWMON=y # CONFIG_SENSORS_G762 is not set # CONFIG_SENSORS_GPIO_FAN is not set # CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_HS3001 is not set # CONFIG_SENSORS_IIO_HWMON is not set # CONFIG_SENSORS_IT87 is not set # CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_POWERZ is not set # CONFIG_SENSORS_POWR1220 is not set # CONFIG_SENSORS_LINEAGE is not set # CONFIG_SENSORS_LTC2945 is not set # CONFIG_SENSORS_LTC2947_I2C is not set # CONFIG_SENSORS_LTC2947_SPI is not set # CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC2991 is not set # CONFIG_SENSORS_LTC2992 is not set # CONFIG_SENSORS_LTC4151 is not set # CONFIG_SENSORS_LTC4215 is not set @@ -2390,6 +2465,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_MAX31722 is not set # CONFIG_SENSORS_MAX31730 is not set # CONFIG_SENSORS_MAX31760 is not set +# CONFIG_MAX31827 is not set # CONFIG_SENSORS_MAX6620 is not set # CONFIG_SENSORS_MAX6621 is not set # CONFIG_SENSORS_MAX6639 is not set @@ -2397,6 +2473,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_MAX6697 is not set # CONFIG_SENSORS_MAX31790 is not set +# CONFIG_SENSORS_MC34VR500 is not set # CONFIG_SENSORS_MCP3021 is not set # CONFIG_SENSORS_TC654 is not set # CONFIG_SENSORS_TPS23861 is not set @@ -2449,7 +2526,6 @@ CONFIG_SENSORS_PWM_FAN=y # CONFIG_SENSORS_SCH5627 is not set # CONFIG_SENSORS_SCH5636 is not set # CONFIG_SENSORS_STTS751 is not set -# CONFIG_SENSORS_SMM665 is not set # CONFIG_SENSORS_ADC128D818 is not set # CONFIG_SENSORS_ADS7828 is not set # CONFIG_SENSORS_ADS7871 is not set @@ -2520,6 +2596,7 @@ CONFIG_WATCHDOG_OPEN_TIMEOUT=0 # CONFIG_SOFT_WATCHDOG is not set # CONFIG_GPIO_WATCHDOG is not set # CONFIG_XILINX_WATCHDOG is not set +# CONFIG_XILINX_WINDOW_WATCHDOG is not set # CONFIG_ZIIRAVE_WATCHDOG is not set # CONFIG_ARM_SP805_WATCHDOG is not set # CONFIG_ARM_SBSA_WATCHDOG is not set @@ -2551,6 +2628,7 @@ CONFIG_BCMA=y CONFIG_MFD_CORE=y # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_SMPRO is not set # CONFIG_MFD_AS3722 is not set # CONFIG_PMIC_ADP5520 is not set # CONFIG_MFD_AAT2870_CORE is not set @@ -2559,7 +2637,9 @@ CONFIG_MFD_CORE=y # CONFIG_MFD_BCM590XX is not set # CONFIG_MFD_BD9571MWV is not set # CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_CS42L43_I2C is not set # CONFIG_MFD_MADERA is not set +# CONFIG_MFD_MAX5970 is not set # CONFIG_PMIC_DA903X is not set # CONFIG_MFD_DA9052_SPI is not set # CONFIG_MFD_DA9052_I2C is not set @@ -2573,14 +2653,13 @@ CONFIG_MFD_CORE=y # CONFIG_MFD_MC13XXX_I2C is not set # CONFIG_MFD_MP2629 is not set # CONFIG_MFD_HI6421_PMIC is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_HTC_I2CPLD is not set # CONFIG_MFD_IQS62X is not set # CONFIG_MFD_KEMPLD is not set # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set # CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77541 is not set # CONFIG_MFD_MAX77620 is not set # CONFIG_MFD_MAX77650 is not set # CONFIG_MFD_MAX77686 is not set @@ -2607,7 +2686,9 @@ CONFIG_MFD_CORE=y # CONFIG_MFD_RT5033 is not set # CONFIG_MFD_RT5120 is not set # CONFIG_MFD_RC5T583 is not set -CONFIG_MFD_RK808=y +CONFIG_MFD_RK8XX=y +CONFIG_MFD_RK8XX_I2C=y +# CONFIG_MFD_RK8XX_SPI is not set # CONFIG_MFD_RN5T618 is not set # CONFIG_MFD_SEC_CORE is not set # CONFIG_MFD_SI476X_CORE is not set @@ -2629,10 +2710,13 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_TI_LP873X is not set # CONFIG_MFD_TI_LP87565 is not set # CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS65219 is not set # CONFIG_MFD_TPS6586X is not set # CONFIG_MFD_TPS65910 is not set # CONFIG_MFD_TPS65912_I2C is not set # CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS6594_I2C is not set +# CONFIG_MFD_TPS6594_SPI is not set # CONFIG_TWL4030_CORE is not set # CONFIG_TWL6040_CORE is not set # CONFIG_MFD_WL1273_CORE is not set @@ -2656,7 +2740,7 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_KHADAS_MCU is not set # CONFIG_MFD_QCOM_PM8008 is not set # CONFIG_RAVE_SP_CORE is not set -# CONFIG_MFD_INTEL_M10_BMC is not set +# CONFIG_MFD_INTEL_M10_BMC_SPI is not set # CONFIG_MFD_RSMU_I2C is not set # CONFIG_MFD_RSMU_SPI is not set # end of Multifunction device drivers @@ -2664,12 +2748,13 @@ CONFIG_MFD_SYSCON=y CONFIG_REGULATOR=y CONFIG_REGULATOR_DEBUG=y CONFIG_REGULATOR_FIXED_VOLTAGE=y -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +CONFIG_REGULATOR_VIRTUAL_CONSUMER=y +CONFIG_REGULATOR_USERSPACE_CONSUMER=y # CONFIG_REGULATOR_88PG86X is not set # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set # CONFIG_REGULATOR_ARM_SCMI is not set +# CONFIG_REGULATOR_AW37503 is not set # CONFIG_REGULATOR_DA9121 is not set # CONFIG_REGULATOR_DA9210 is not set # CONFIG_REGULATOR_DA9211 is not set @@ -2685,12 +2770,15 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_LTC3589 is not set # CONFIG_REGULATOR_LTC3676 is not set # CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX77503 is not set +# CONFIG_REGULATOR_MAX77857 is not set # CONFIG_REGULATOR_MAX8649 is not set # CONFIG_REGULATOR_MAX8660 is not set # CONFIG_REGULATOR_MAX8893 is not set # CONFIG_REGULATOR_MAX8952 is not set # CONFIG_REGULATOR_MAX8973 is not set # CONFIG_REGULATOR_MAX20086 is not set +# CONFIG_REGULATOR_MAX20411 is not set # CONFIG_REGULATOR_MAX77826 is not set # CONFIG_REGULATOR_MCP16502 is not set # CONFIG_REGULATOR_MP5416 is not set @@ -2705,16 +2793,21 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_PV88080 is not set # CONFIG_REGULATOR_PV88090 is not set CONFIG_REGULATOR_PWM=y +# CONFIG_REGULATOR_RAA215300 is not set # CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set CONFIG_REGULATOR_RK808=y # CONFIG_REGULATOR_RT4801 is not set +# CONFIG_REGULATOR_RT4803 is not set # CONFIG_REGULATOR_RT5190A is not set +# CONFIG_REGULATOR_RT5739 is not set # CONFIG_REGULATOR_RT5759 is not set # CONFIG_REGULATOR_RT6160 is not set +# CONFIG_REGULATOR_RT6190 is not set # CONFIG_REGULATOR_RT6245 is not set # CONFIG_REGULATOR_RTQ2134 is not set # CONFIG_REGULATOR_RTMV20 is not set # CONFIG_REGULATOR_RTQ6752 is not set +# CONFIG_REGULATOR_RTQ2208 is not set # CONFIG_REGULATOR_SLG51000 is not set # CONFIG_REGULATOR_SY8106A is not set # CONFIG_REGULATOR_SY8824X is not set @@ -2722,11 +2815,12 @@ CONFIG_REGULATOR_RK808=y # CONFIG_REGULATOR_TPS51632 is not set # CONFIG_REGULATOR_TPS62360 is not set # CONFIG_REGULATOR_TPS6286X is not set +# CONFIG_REGULATOR_TPS6287X is not set # CONFIG_REGULATOR_TPS65023 is not set # CONFIG_REGULATOR_TPS6507X is not set # CONFIG_REGULATOR_TPS65132 is not set # CONFIG_REGULATOR_TPS6524X is not set -# CONFIG_REGULATOR_VCTRL is not set +CONFIG_REGULATOR_VCTRL=y # CONFIG_RC_CORE is not set CONFIG_CEC_CORE=y CONFIG_CEC_NOTIFIER=y @@ -2809,7 +2903,6 @@ CONFIG_V4L_MEM2MEM_DRIVERS=y # # Aspeed media platform drivers # -# CONFIG_VIDEO_ASPEED is not set # # Atmel media platform drivers @@ -2837,6 +2930,14 @@ CONFIG_V4L_MEM2MEM_DRIVERS=y # Mediatek media platform drivers # +# +# Microchip Technology, Inc. media platform drivers +# + +# +# Nuvoton media platform drivers +# + # # NVidia media platform drivers # @@ -2856,7 +2957,6 @@ CONFIG_V4L_MEM2MEM_DRIVERS=y # # Rockchip media platform drivers # -CONFIG_VIDEO_ROCKCHIP_IEP=y CONFIG_VIDEO_ROCKCHIP_RGA=y CONFIG_VIDEO_ROCKCHIP_ISP1=y @@ -2947,6 +3047,7 @@ CONFIG_VIDEO_MSP3400=m # CONFIG_VIDEO_SAA7110 is not set # CONFIG_VIDEO_SAA711X is not set # CONFIG_VIDEO_TC358743 is not set +# CONFIG_VIDEO_TC358746 is not set # CONFIG_VIDEO_TVP514X is not set # CONFIG_VIDEO_TVP5150 is not set # CONFIG_VIDEO_TVP7002 is not set @@ -2966,7 +3067,6 @@ CONFIG_VIDEO_MSP3400=m # # Video encoders # -# CONFIG_VIDEO_AD9389B is not set # CONFIG_VIDEO_ADV7170 is not set # CONFIG_VIDEO_ADV7175 is not set # CONFIG_VIDEO_ADV7343 is not set @@ -3005,6 +3105,14 @@ CONFIG_VIDEO_MSP3400=m # CONFIG_VIDEO_THS7303 is not set # end of Miscellaneous helper chips +# +# Video serializers and deserializers +# +# CONFIG_VIDEO_DS90UB913 is not set +# CONFIG_VIDEO_DS90UB953 is not set +# CONFIG_VIDEO_DS90UB960 is not set +# end of Video serializers and deserializers + # # Media SPI Adapters # @@ -3015,6 +3123,9 @@ CONFIG_VIDEO_MSP3400=m # # Graphics support # +CONFIG_VIDEO_CMDLINE=y +CONFIG_VIDEO_NOMODESET=y +# CONFIG_AUXDISPLAY is not set CONFIG_DRM=y CONFIG_DRM_MIPI_DSI=y # CONFIG_DRM_DEBUG_MM is not set @@ -3064,9 +3175,6 @@ CONFIG_ROCKCHIP_DW_MIPI_DSI=y # CONFIG_ROCKCHIP_RGB is not set # CONFIG_ROCKCHIP_RK3066_HDMI is not set # CONFIG_DRM_UDL is not set -# CONFIG_DRM_RCAR_DW_HDMI is not set -# CONFIG_DRM_RCAR_USE_LVDS is not set -# CONFIG_DRM_RCAR_USE_MIPI_DSI is not set CONFIG_DRM_PANEL=y # @@ -3075,6 +3183,7 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_ABT_Y030XX067A is not set # CONFIG_DRM_PANEL_ARM_VERSATILE is not set # CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set +# CONFIG_DRM_PANEL_AUO_A030JTN01 is not set # CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set # CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set # CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set @@ -3086,12 +3195,16 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set # CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set # CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set +# CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set # CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set +# CONFIG_DRM_PANEL_JDI_LPM102A188A is not set # CONFIG_DRM_PANEL_JDI_R63452 is not set # CONFIG_DRM_PANEL_KHADAS_TS050 is not set # CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set @@ -3100,26 +3213,32 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set +# CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set # CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set # CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set # CONFIG_DRM_PANEL_NOVATEK_NT35560 is not set # CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set # CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set # CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set # CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set # CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set +# CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set # CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set # CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set # CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set # CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set # CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set # CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM692E5 is not set # CONFIG_DRM_PANEL_RONBO_RB070D30 is not set # CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set # CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set @@ -3136,13 +3255,17 @@ CONFIG_DRM_PANEL_SHARP_LS054B3SX01=y # CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set # CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set # CONFIG_DRM_PANEL_SONY_ACX565AKM is not set +# CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set # CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set +# CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set # CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set # CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set # CONFIG_DRM_PANEL_TPO_TPG110 is not set # CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set # CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set +# CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set +# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set # CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set # CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set # end of Display Panels @@ -3153,7 +3276,6 @@ CONFIG_DRM_PANEL_BRIDGE=y # # Display Interface Bridges # -# CONFIG_DRM_CDNS_DSI is not set # CONFIG_DRM_CHIPONE_ICN6211 is not set # CONFIG_DRM_CHRONTEL_CH7033 is not set CONFIG_DRM_DISPLAY_CONNECTOR=m @@ -3169,6 +3291,7 @@ CONFIG_DRM_DISPLAY_CONNECTOR=m # CONFIG_DRM_NXP_PTN3460 is not set # CONFIG_DRM_PARADE_PS8622 is not set # CONFIG_DRM_PARADE_PS8640 is not set +# CONFIG_DRM_SAMSUNG_DSIM is not set # CONFIG_DRM_SIL_SII8620 is not set # CONFIG_DRM_SII902X is not set # CONFIG_DRM_SII9234 is not set @@ -3188,6 +3311,7 @@ CONFIG_DRM_DISPLAY_CONNECTOR=m # CONFIG_DRM_ANALOGIX_ANX78XX is not set # CONFIG_DRM_ANALOGIX_ANX7625 is not set # CONFIG_DRM_I2C_ADV7511 is not set +# CONFIG_DRM_CDNS_DSI is not set # CONFIG_DRM_CDNS_MHDP8546 is not set CONFIG_DRM_DW_HDMI=y # CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set @@ -3221,30 +3345,11 @@ CONFIG_DRM_PANFROST=y # CONFIG_DRM_SSD130X is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y -CONFIG_DRM_NOMODESET=y # # Frame buffer Devices # -CONFIG_FB_CMDLINE=y -CONFIG_FB_NOTIFY=y CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_IMAGEBLIT=y -# CONFIG_FB_FOREIGN_ENDIAN is not set -CONFIG_FB_SYS_FOPS=y -CONFIG_FB_DEFERRED_IO=y -CONFIG_FB_MODE_HELPERS=y -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# # CONFIG_FB_ARMCLCD is not set # CONFIG_FB_OPENCORES is not set # CONFIG_FB_S1D13XXX is not set @@ -3255,6 +3360,22 @@ CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_METRONOME is not set # CONFIG_FB_SIMPLE is not set # CONFIG_FB_SSD1307 is not set +CONFIG_FB_CORE=y +CONFIG_FB_NOTIFY=y +# CONFIG_FIRMWARE_EDID is not set +CONFIG_FB_DEVICE=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_IMAGEBLIT=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_DMAMEM_HELPERS=y +CONFIG_FB_IOMEM_FOPS=y +CONFIG_FB_SYSMEM_HELPERS=y +CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set # end of Frame buffer Devices # @@ -3263,6 +3384,7 @@ CONFIG_FB_MODE_HELPERS=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_KTD253 is not set +# CONFIG_BACKLIGHT_KTZ8866 is not set CONFIG_BACKLIGHT_PWM=y # CONFIG_BACKLIGHT_QCOM_WLED is not set # CONFIG_BACKLIGHT_ADP8860 is not set @@ -3296,6 +3418,7 @@ CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y # CONFIG_LOGO is not set # end of Graphics support +# CONFIG_DRM_ACCEL is not set CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_TIMER=y @@ -3319,6 +3442,7 @@ CONFIG_SND_CTL_FAST_LOOKUP=y # CONFIG_SND_CTL_INPUT_VALIDATION is not set CONFIG_SND_SEQUENCER=y # CONFIG_SND_SEQ_DUMMY is not set +# CONFIG_SND_SEQ_UMP is not set # CONFIG_SND_DRIVERS is not set # @@ -3356,6 +3480,7 @@ CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y # CONFIG_SND_SOC_IMX_AUDMUX is not set # end of SoC Audio for Freescale CPUs +# CONFIG_SND_SOC_CHV3_I2S is not set # CONFIG_SND_I2S_HI6210_I2S is not set # CONFIG_SND_SOC_IMG is not set # CONFIG_SND_SOC_MTK_BTCVSD is not set @@ -3403,9 +3528,15 @@ CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_AK5386 is not set # CONFIG_SND_SOC_AK5558 is not set # CONFIG_SND_SOC_ALC5623 is not set +# CONFIG_SND_SOC_AUDIO_IIO_AUX is not set # CONFIG_SND_SOC_AW8738 is not set +# CONFIG_SND_SOC_AW88395 is not set +# CONFIG_SND_SOC_AW88261 is not set +# CONFIG_SND_SOC_AW87390 is not set +# CONFIG_SND_SOC_AW88399 is not set # CONFIG_SND_SOC_BD28623 is not set # CONFIG_SND_SOC_BT_SCO is not set +# CONFIG_SND_SOC_CHV3_CODEC is not set # CONFIG_SND_SOC_CS35L32 is not set # CONFIG_SND_SOC_CS35L33 is not set # CONFIG_SND_SOC_CS35L34 is not set @@ -3415,6 +3546,8 @@ CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_CS35L41_I2C is not set # CONFIG_SND_SOC_CS35L45_SPI is not set # CONFIG_SND_SOC_CS35L45_I2C is not set +# CONFIG_SND_SOC_CS35L56_I2C is not set +# CONFIG_SND_SOC_CS35L56_SPI is not set # CONFIG_SND_SOC_CS42L42 is not set # CONFIG_SND_SOC_CS42L51_I2C is not set # CONFIG_SND_SOC_CS42L52 is not set @@ -3444,14 +3577,17 @@ CONFIG_SND_SOC_ES8316=y # CONFIG_SND_SOC_GTM601 is not set # CONFIG_SND_SOC_HDA is not set # CONFIG_SND_SOC_ICS43432 is not set +# CONFIG_SND_SOC_IDT821034 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set +# CONFIG_SND_SOC_MAX98090 is not set # CONFIG_SND_SOC_MAX98357A is not set # CONFIG_SND_SOC_MAX98504 is not set # CONFIG_SND_SOC_MAX9867 is not set # CONFIG_SND_SOC_MAX98927 is not set # CONFIG_SND_SOC_MAX98520 is not set # CONFIG_SND_SOC_MAX98373_I2C is not set +# CONFIG_SND_SOC_MAX98388 is not set # CONFIG_SND_SOC_MAX98390 is not set # CONFIG_SND_SOC_MAX98396 is not set # CONFIG_SND_SOC_MAX9860 is not set @@ -3469,6 +3605,7 @@ CONFIG_SND_SOC_ES8316=y # CONFIG_SND_SOC_PCM5102A is not set # CONFIG_SND_SOC_PCM512x_I2C is not set # CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_PEB2466 is not set # CONFIG_SND_SOC_RK3328 is not set # CONFIG_SND_SOC_RK817 is not set # CONFIG_SND_SOC_RT5616 is not set @@ -3476,15 +3613,18 @@ CONFIG_SND_SOC_ES8316=y # CONFIG_SND_SOC_RT5640 is not set # CONFIG_SND_SOC_RT5659 is not set # CONFIG_SND_SOC_RT9120 is not set +# CONFIG_SND_SOC_RTQ9128 is not set # CONFIG_SND_SOC_SGTL5000 is not set CONFIG_SND_SOC_SIMPLE_AMPLIFIER=y # CONFIG_SND_SOC_SIMPLE_MUX is not set +# CONFIG_SND_SOC_SMA1303 is not set CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_SRC4XXX_I2C is not set # CONFIG_SND_SOC_SSM2305 is not set # CONFIG_SND_SOC_SSM2518 is not set # CONFIG_SND_SOC_SSM2602_SPI is not set # CONFIG_SND_SOC_SSM2602_I2C is not set +# CONFIG_SND_SOC_SSM3515 is not set # CONFIG_SND_SOC_SSM4567 is not set # CONFIG_SND_SOC_STA32X is not set # CONFIG_SND_SOC_STA350 is not set @@ -3494,6 +3634,7 @@ CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_TAS2764 is not set # CONFIG_SND_SOC_TAS2770 is not set # CONFIG_SND_SOC_TAS2780 is not set +# CONFIG_SND_SOC_TAS2781_I2C is not set # CONFIG_SND_SOC_TAS5086 is not set # CONFIG_SND_SOC_TAS571X is not set # CONFIG_SND_SOC_TAS5720 is not set @@ -3536,6 +3677,7 @@ CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_WM8904 is not set # CONFIG_SND_SOC_WM8940 is not set # CONFIG_SND_SOC_WM8960 is not set +# CONFIG_SND_SOC_WM8961 is not set # CONFIG_SND_SOC_WM8962 is not set # CONFIG_SND_SOC_WM8974 is not set # CONFIG_SND_SOC_WM8978 is not set @@ -3563,10 +3705,7 @@ CONFIG_SND_SIMPLE_CARD=y CONFIG_SND_AUDIO_GRAPH_CARD=y # CONFIG_SND_AUDIO_GRAPH_CARD2 is not set # CONFIG_SND_TEST_COMPONENT is not set - -# -# HID support -# +CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_BATTERY_STRENGTH is not set CONFIG_HIDRAW=y @@ -3589,10 +3728,12 @@ CONFIG_HID_GENERIC=y # CONFIG_HID_DRAGONRISE is not set # CONFIG_HID_EMS_FF is not set # CONFIG_HID_ELECOM is not set +# CONFIG_HID_EVISION is not set # CONFIG_HID_EZKEY is not set # CONFIG_HID_GEMBIRD is not set # CONFIG_HID_GFRM is not set # CONFIG_HID_GLORIOUS is not set +# CONFIG_HID_GOOGLE_STADIA_FF is not set # CONFIG_HID_VIVALDI is not set # CONFIG_HID_KEYTOUCH is not set # CONFIG_HID_KYE is not set @@ -3630,7 +3771,6 @@ CONFIG_HID_GENERIC=y # CONFIG_HID_SEMITEK is not set # CONFIG_HID_SPEEDLINK is not set # CONFIG_HID_STEAM is not set -# CONFIG_HID_STEELSERIES is not set # CONFIG_HID_SUNPLUS is not set # CONFIG_HID_RMI is not set # CONFIG_HID_GREENASIA is not set @@ -3648,6 +3788,11 @@ CONFIG_HID_GENERIC=y # CONFIG_HID_ALPS is not set # end of Special HID drivers +# +# HID-BPF support +# +# end of HID-BPF support + # # USB HID support # @@ -3662,17 +3807,11 @@ CONFIG_HID_GENERIC=y # end of USB HID Boot Protocol drivers # end of USB HID support -# -# I2C HID support -# +CONFIG_I2C_HID=y # CONFIG_I2C_HID_OF is not set # CONFIG_I2C_HID_OF_ELAN is not set CONFIG_I2C_HID_OF_GOODIX=y -# end of I2C HID support - CONFIG_I2C_HID_CORE=y -# end of HID support - CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_SUPPORT=y CONFIG_USB_COMMON=y @@ -3712,7 +3851,6 @@ CONFIG_USB_EHCI_TT_NEWSCHED=y CONFIG_USB_EHCI_HCD_PLATFORM=y # CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_FOTG210_HCD is not set # CONFIG_USB_MAX3421_HCD is not set CONFIG_USB_OHCI_HCD=y # CONFIG_USB_OHCI_HCD_SSB is not set @@ -3761,6 +3899,10 @@ CONFIG_USB_UAS=y # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # CONFIG_USBIP_CORE is not set + +# +# USB dual-mode controller drivers +# # CONFIG_USB_CDNS_SUPPORT is not set # CONFIG_USB_MUSB_HDRC is not set CONFIG_USB_DWC3=y @@ -3802,7 +3944,6 @@ CONFIG_USB_DWC2_DUAL_ROLE=y # CONFIG_USB_CYPRESS_CY7C63 is not set # CONFIG_USB_CYTHERM is not set # CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set # CONFIG_USB_APPLEDISPLAY is not set # CONFIG_APPLE_MFI_FASTCHARGE is not set # CONFIG_USB_SISUSBVGA is not set @@ -3841,7 +3982,6 @@ CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 # # USB Peripheral Controller # -# CONFIG_USB_FOTG210_UDC is not set # CONFIG_USB_GR_UDC is not set # CONFIG_USB_R8A66597 is not set # CONFIG_USB_PXA27X is not set @@ -3896,7 +4036,10 @@ CONFIG_TYPEC_FUSB302=y # USB Type-C Multiplexer/DeMultiplexer Switch support # # CONFIG_TYPEC_MUX_FSA4480 is not set +# CONFIG_TYPEC_MUX_GPIO_SBU is not set # CONFIG_TYPEC_MUX_PI3USB30532 is not set +# CONFIG_TYPEC_MUX_NB7VPQ904M is not set +# CONFIG_TYPEC_MUX_PTN36502 is not set # end of USB Type-C Multiplexer/DeMultiplexer Switch support # @@ -3957,6 +4100,7 @@ CONFIG_LEDS_CLASS=y # LED drivers # # CONFIG_LEDS_AN30259A is not set +# CONFIG_LEDS_AW200XX is not set # CONFIG_LEDS_AW2013 is not set # CONFIG_LEDS_BCM6328 is not set # CONFIG_LEDS_BCM6358 is not set @@ -3975,9 +4119,11 @@ CONFIG_LEDS_GPIO=y # CONFIG_LEDS_LP8860 is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_PCA963X is not set +# CONFIG_LEDS_PCA995X is not set # CONFIG_LEDS_DAC124S085 is not set CONFIG_LEDS_PWM=y # CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_BD2606MVV is not set # CONFIG_LEDS_BD2802 is not set # CONFIG_LEDS_LT3593 is not set # CONFIG_LEDS_TCA6507 is not set @@ -3994,7 +4140,7 @@ CONFIG_LEDS_SYSCON=y # CONFIG_LEDS_MLXREG is not set # CONFIG_LEDS_USER is not set # CONFIG_LEDS_SPI_BYTE is not set -# CONFIG_LEDS_TI_LMU_COMMON is not set +# CONFIG_LEDS_LM3697 is not set # # Flash and Torch LED drivers @@ -4014,7 +4160,7 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_BACKLIGHT=y CONFIG_LEDS_TRIGGER_CPU=y # CONFIG_LEDS_TRIGGER_ACTIVITY is not set -CONFIG_LEDS_TRIGGER_GPIO=y +# CONFIG_LEDS_TRIGGER_GPIO is not set CONFIG_LEDS_TRIGGER_DEFAULT_ON=y # @@ -4128,9 +4274,7 @@ CONFIG_RTC_I2C_AND_SPI=y # CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set # CONFIG_RTC_DRV_MSM6242 is not set -# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_RP5C01 is not set -# CONFIG_RTC_DRV_V3020 is not set # CONFIG_RTC_DRV_ZYNQMP is not set # @@ -4163,6 +4307,7 @@ CONFIG_DMA_OF=y # CONFIG_MV_XOR_V2 is not set CONFIG_PL330_DMA=y # CONFIG_XILINX_DMA is not set +# CONFIG_XILINX_XDMA is not set # CONFIG_XILINX_ZYNQMP_DMA is not set # CONFIG_XILINX_ZYNQMP_DPDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set @@ -4189,7 +4334,6 @@ CONFIG_SYNC_FILE=y # CONFIG_DMABUF_SYSFS_STATS is not set # end of DMABUF options -# CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set # CONFIG_VFIO is not set # CONFIG_VIRT_DRIVERS is not set @@ -4209,7 +4353,6 @@ CONFIG_STAGING=y # CONFIG_RTLLIB is not set CONFIG_RTL8723BS=m CONFIG_R8712U=m -CONFIG_R8188EU=m # CONFIG_VT6656 is not set # @@ -4247,24 +4390,16 @@ CONFIG_R8188EU=m # # CONFIG_AD5933 is not set # end of Network Analyzer, Impedance Converters - -# -# Active energy metering IC -# -# CONFIG_ADE7854 is not set -# end of Active energy metering IC - -# -# Resolver to digital converters -# -# CONFIG_AD2S1210 is not set -# end of Resolver to digital converters # end of IIO staging drivers CONFIG_STAGING_MEDIA=y # CONFIG_VIDEO_MAX96712 is not set CONFIG_VIDEO_ROCKCHIP_VDEC=m -# CONFIG_STAGING_MEDIA_DEPRECATED is not set +CONFIG_STAGING_MEDIA_DEPRECATED=y + +# +# Atmel media platform drivers +# # CONFIG_STAGING_BOARD is not set # CONFIG_LTE_GDM724X is not set # CONFIG_FB_TFT is not set @@ -4290,8 +4425,8 @@ CONFIG_COMMON_CLK=y # CONFIG_LMK04832 is not set # CONFIG_COMMON_CLK_MAX9485 is not set CONFIG_COMMON_CLK_RK808=y -# CONFIG_COMMON_CLK_SCMI is not set -# CONFIG_COMMON_CLK_SCPI is not set +CONFIG_COMMON_CLK_SCMI=y +CONFIG_COMMON_CLK_SCPI=y # CONFIG_COMMON_CLK_SI5341 is not set # CONFIG_COMMON_CLK_SI5351 is not set # CONFIG_COMMON_CLK_SI514 is not set @@ -4302,11 +4437,13 @@ CONFIG_COMMON_CLK_RK808=y # CONFIG_COMMON_CLK_CS2000_CP is not set # CONFIG_COMMON_CLK_AXI_CLKGEN is not set # CONFIG_COMMON_CLK_XGENE is not set -# CONFIG_COMMON_CLK_PWM is not set +CONFIG_COMMON_CLK_PWM=y # CONFIG_COMMON_CLK_RS9_PCIE is not set +# CONFIG_COMMON_CLK_SI521XX is not set +# CONFIG_COMMON_CLK_VC3 is not set # CONFIG_COMMON_CLK_VC5 is not set # CONFIG_COMMON_CLK_VC7 is not set -# CONFIG_COMMON_CLK_FIXED_MMIO is not set +CONFIG_COMMON_CLK_FIXED_MMIO=y CONFIG_COMMON_CLK_ROCKCHIP=y # CONFIG_CLK_PX30 is not set # CONFIG_CLK_RK3308 is not set @@ -4314,6 +4451,7 @@ CONFIG_COMMON_CLK_ROCKCHIP=y # CONFIG_CLK_RK3368 is not set CONFIG_CLK_RK3399=y # CONFIG_CLK_RK3568 is not set +# CONFIG_CLK_RK3588 is not set # CONFIG_XILINX_VCU is not set # CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set # CONFIG_HWSPINLOCK is not set @@ -4330,7 +4468,6 @@ CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y # CONFIG_FSL_ERRATUM_A008585 is not set # CONFIG_HISILICON_ERRATUM_161010101 is not set # CONFIG_ARM64_ERRATUM_858921 is not set -# CONFIG_MICROCHIP_PIT64B is not set # end of Clock Source drivers CONFIG_MAILBOX=y @@ -4361,6 +4498,7 @@ CONFIG_IOMMU_DEFAULT_DMA_STRICT=y # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set CONFIG_OF_IOMMU=y CONFIG_IOMMU_DMA=y +# CONFIG_IOMMUFD is not set CONFIG_ROCKCHIP_IOMMU=y CONFIG_ARM_SMMU=y # CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set @@ -4395,7 +4533,6 @@ CONFIG_ARM_SMMU_V3=y # # Broadcom SoC drivers # -# CONFIG_SOC_BRCMSTB is not set # end of Broadcom SoC drivers # @@ -4421,6 +4558,8 @@ CONFIG_ARM_SMMU_V3=y # CONFIG_LITEX_SOC_CONTROLLER is not set # end of Enable LiteX SoC Builder specific drivers +# CONFIG_WPCM450_SOC is not set + # # Qualcomm SoC drivers # @@ -4428,7 +4567,6 @@ CONFIG_ARM_SMMU_V3=y CONFIG_ROCKCHIP_GRF=y CONFIG_ROCKCHIP_IODOMAIN=y -CONFIG_ROCKCHIP_PM_DOMAINS=y # CONFIG_SOC_TI is not set # @@ -4437,6 +4575,33 @@ CONFIG_ROCKCHIP_PM_DOMAINS=y # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers +# +# PM Domains +# + +# +# Amlogic PM Domains +# +# end of Amlogic PM Domains + +# +# Broadcom PM Domains +# +# end of Broadcom PM Domains + +# +# i.MX PM Domains +# +# end of i.MX PM Domains + +# +# Qualcomm PM Domains +# +# end of Qualcomm PM Domains + +CONFIG_ROCKCHIP_PM_DOMAINS=y +# end of PM Domains + CONFIG_PM_DEVFREQ=y # @@ -4468,21 +4633,22 @@ CONFIG_EXTCON=y # CONFIG_EXTCON_SM5502 is not set # CONFIG_EXTCON_USB_GPIO is not set # CONFIG_EXTCON_USBC_TUSB320 is not set -# CONFIG_MEMORY is not set +CONFIG_MEMORY=y +# CONFIG_ARM_PL172_MPMC is not set CONFIG_IIO=y CONFIG_IIO_BUFFER=y CONFIG_IIO_BUFFER_CB=y # CONFIG_IIO_BUFFER_DMA is not set # CONFIG_IIO_BUFFER_DMAENGINE is not set -# CONFIG_IIO_BUFFER_HW_CONSUMER is not set +CONFIG_IIO_BUFFER_HW_CONSUMER=y CONFIG_IIO_KFIFO_BUF=y CONFIG_IIO_TRIGGERED_BUFFER=y -# CONFIG_IIO_CONFIGFS is not set +CONFIG_IIO_CONFIGFS=y CONFIG_IIO_TRIGGER=y CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 -# CONFIG_IIO_SW_DEVICE is not set -# CONFIG_IIO_SW_TRIGGER is not set -# CONFIG_IIO_TRIGGERED_EVENT is not set +CONFIG_IIO_SW_DEVICE=y +CONFIG_IIO_SW_TRIGGER=y +CONFIG_IIO_TRIGGERED_EVENT=y # # Accelerometers @@ -4512,6 +4678,8 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_FXLS8962AF_I2C is not set # CONFIG_FXLS8962AF_SPI is not set # CONFIG_IIO_ST_ACCEL_3AXIS is not set +# CONFIG_IIO_KX022A_SPI is not set +# CONFIG_IIO_KX022A_I2C is not set # CONFIG_KXSD9 is not set # CONFIG_KXCJK1013 is not set # CONFIG_MC3230 is not set @@ -4533,6 +4701,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # # Analog to digital converters # +# CONFIG_AD4130 is not set # CONFIG_AD7091R5 is not set # CONFIG_AD7124 is not set # CONFIG_AD7192 is not set @@ -4559,6 +4728,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_HI8435 is not set # CONFIG_HX711 is not set # CONFIG_INA2XX_ADC is not set +# CONFIG_LTC2309 is not set # CONFIG_LTC2471 is not set # CONFIG_LTC2485 is not set # CONFIG_LTC2496 is not set @@ -4567,11 +4737,13 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_MAX11100 is not set # CONFIG_MAX1118 is not set # CONFIG_MAX11205 is not set +# CONFIG_MAX11410 is not set # CONFIG_MAX1241 is not set # CONFIG_MAX1363 is not set # CONFIG_MAX9611 is not set # CONFIG_MCP320X is not set # CONFIG_MCP3422 is not set +# CONFIG_MCP3564 is not set # CONFIG_MCP3911 is not set # CONFIG_NAU7802 is not set CONFIG_ROCKCHIP_SARADC=y @@ -4585,11 +4757,14 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_TI_ADC128S052 is not set # CONFIG_TI_ADC161S626 is not set # CONFIG_TI_ADS1015 is not set +# CONFIG_TI_ADS7924 is not set +# CONFIG_TI_ADS1100 is not set # CONFIG_TI_ADS7950 is not set # CONFIG_TI_ADS8344 is not set # CONFIG_TI_ADS8688 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS131E08 is not set +# CONFIG_TI_LMP92064 is not set # CONFIG_TI_TLC4541 is not set # CONFIG_TI_TSC2046 is not set # CONFIG_VF610_ADC is not set @@ -4599,6 +4774,7 @@ CONFIG_ROCKCHIP_SARADC=y # # Analog to digital and digital to analog converters # +# CONFIG_AD74115 is not set # CONFIG_AD74413R is not set # end of Analog to digital and digital to analog converters @@ -4692,8 +4868,10 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_LTC2632 is not set # CONFIG_M62332 is not set # CONFIG_MAX517 is not set +# CONFIG_MAX5522 is not set # CONFIG_MAX5821 is not set # CONFIG_MCP4725 is not set +# CONFIG_MCP4728 is not set # CONFIG_MCP4922 is not set # CONFIG_TI_DAC082S085 is not set # CONFIG_TI_DAC5571 is not set @@ -4705,6 +4883,7 @@ CONFIG_ROCKCHIP_SARADC=y # # IIO dummy driver # +# CONFIG_IIO_SIMPLE_DUMMY is not set # end of IIO dummy driver # @@ -4728,6 +4907,7 @@ CONFIG_ROCKCHIP_SARADC=y # # CONFIG_ADF4350 is not set # CONFIG_ADF4371 is not set +# CONFIG_ADF4377 is not set # CONFIG_ADMV1013 is not set # CONFIG_ADMV1014 is not set # CONFIG_ADMV4420 is not set @@ -4823,6 +5003,8 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_SENSORS_ISL29028 is not set # CONFIG_ISL29125 is not set # CONFIG_JSA1212 is not set +# CONFIG_ROHM_BU27008 is not set +# CONFIG_ROHM_BU27034 is not set # CONFIG_RPR0521 is not set # CONFIG_LTR501 is not set # CONFIG_LTRF216A is not set @@ -4831,6 +5013,7 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_MAX44009 is not set # CONFIG_NOA1305 is not set # CONFIG_OPT3001 is not set +# CONFIG_OPT4001 is not set # CONFIG_PA12203001 is not set # CONFIG_SI1133 is not set # CONFIG_SI1145 is not set @@ -4867,13 +5050,14 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_SENSORS_HMC5843_SPI is not set # CONFIG_SENSORS_RM3100_I2C is not set # CONFIG_SENSORS_RM3100_SPI is not set +# CONFIG_TI_TMAG5273 is not set # CONFIG_YAMAHA_YAS530 is not set # end of Magnetometer sensors # # Multiplexers # -# CONFIG_IIO_MUX is not set +CONFIG_IIO_MUX=y # end of Multiplexers # @@ -4884,8 +5068,10 @@ CONFIG_ROCKCHIP_SARADC=y # # Triggers - standalone # +CONFIG_IIO_HRTIMER_TRIGGER=y # CONFIG_IIO_INTERRUPT_TRIGGER is not set -# CONFIG_IIO_SYSFS_TRIGGER is not set +# CONFIG_IIO_TIGHTLOOP_TRIGGER is not set +CONFIG_IIO_SYSFS_TRIGGER=y # end of Triggers - standalone # @@ -4907,6 +5093,7 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_MCP4531 is not set # CONFIG_MCP41010 is not set # CONFIG_TPL0102 is not set +# CONFIG_X9250 is not set # end of Digital potentiometers # @@ -4919,6 +5106,7 @@ CONFIG_ROCKCHIP_SARADC=y # Pressure sensors # # CONFIG_ABP060MG is not set +# CONFIG_ROHM_BM1390 is not set # CONFIG_BMP280 is not set # CONFIG_DLHL60D is not set # CONFIG_DPS310 is not set @@ -4927,6 +5115,7 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_MPL115_I2C is not set # CONFIG_MPL115_SPI is not set # CONFIG_MPL3115 is not set +# CONFIG_MPRLS0025PA is not set # CONFIG_MS5611 is not set # CONFIG_MS5637 is not set # CONFIG_IIO_ST_PRESS is not set @@ -4944,6 +5133,7 @@ CONFIG_ROCKCHIP_SARADC=y # # Proximity and distance sensors # +# CONFIG_IRSD200 is not set # CONFIG_ISL29501 is not set # CONFIG_LIDAR_LITE_V2 is not set # CONFIG_MB1232 is not set @@ -4964,6 +5154,7 @@ CONFIG_ROCKCHIP_SARADC=y # # CONFIG_AD2S90 is not set # CONFIG_AD2S1200 is not set +# CONFIG_AD2S1210 is not set # end of Resolver to digital converters # @@ -4978,6 +5169,7 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_TMP117 is not set # CONFIG_TSYS01 is not set # CONFIG_TSYS02D is not set +# CONFIG_MAX30208 is not set # CONFIG_MAX31856 is not set # CONFIG_MAX31865 is not set # end of Temperature sensors @@ -5018,7 +5210,6 @@ CONFIG_RESET_SCMI=y # CONFIG_GENERIC_PHY=y CONFIG_GENERIC_PHY_MIPI_DPHY=y -# CONFIG_PHY_XGENE is not set # CONFIG_PHY_CAN_TRANSCEIVER is not set # @@ -5039,7 +5230,7 @@ CONFIG_GENERIC_PHY_MIPI_DPHY=y # CONFIG_PHY_MAPPHONE_MDM6600 is not set # CONFIG_PHY_OCELOT_SERDES is not set CONFIG_PHY_ROCKCHIP_DP=y -# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set +CONFIG_PHY_ROCKCHIP_DPHY_RX0=y CONFIG_PHY_ROCKCHIP_EMMC=y # CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set CONFIG_PHY_ROCKCHIP_INNO_USB2=y @@ -5063,8 +5254,11 @@ CONFIG_PHY_ROCKCHIP_USB=y # CONFIG_ARM_CCN is not set # CONFIG_ARM_CMN is not set CONFIG_ARM_PMU=y +# CONFIG_ARM_SMMU_V3_PMU is not set +CONFIG_ARM_PMUV3=y # CONFIG_ARM_DSU_PMU is not set # CONFIG_ARM_SPE_PMU is not set +# CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU is not set # end of Performance monitor support CONFIG_RAS=y @@ -5079,6 +5273,14 @@ CONFIG_RAS=y # CONFIG_DAX is not set CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y + +# +# Layout Types +# +# CONFIG_NVMEM_LAYOUT_SL28_VPD is not set +# CONFIG_NVMEM_LAYOUT_ONIE_TLV is not set +# end of Layout Types + CONFIG_NVMEM_RMEM=m CONFIG_NVMEM_ROCKCHIP_EFUSE=y CONFIG_NVMEM_ROCKCHIP_OTP=m @@ -5093,6 +5295,17 @@ CONFIG_NVMEM_ROCKCHIP_OTP=m # CONFIG_FPGA is not set # CONFIG_FSI is not set # CONFIG_TEE is not set +CONFIG_MULTIPLEXER=y + +# +# Multiplexer drivers +# +# CONFIG_MUX_ADG792A is not set +# CONFIG_MUX_ADGS1408 is not set +CONFIG_MUX_GPIO=y +CONFIG_MUX_MMIO=y +# end of Multiplexer drivers + CONFIG_PM_OPP=y # CONFIG_SIOX is not set # CONFIG_SLIMBUS is not set @@ -5101,6 +5314,7 @@ CONFIG_PM_OPP=y # CONFIG_MOST is not set # CONFIG_PECI is not set # CONFIG_HTE is not set +# CONFIG_CDX_BUS is not set # end of Device Drivers # @@ -5109,6 +5323,8 @@ CONFIG_PM_OPP=y CONFIG_DCACHE_WORD_ACCESS=y # CONFIG_VALIDATE_FS_PARSER is not set CONFIG_FS_IOMAP=y +CONFIG_BUFFER_HEAD=y +CONFIG_LEGACY_DIRECT_IO=y # CONFIG_EXT2_FS is not set # CONFIG_EXT3_FS is not set CONFIG_EXT4_FS=y @@ -5123,6 +5339,7 @@ CONFIG_FS_MBCACHE=y # CONFIG_JFS_FS is not set CONFIG_XFS_FS=y CONFIG_XFS_SUPPORT_V4=y +CONFIG_XFS_SUPPORT_ASCII_CI=y # CONFIG_XFS_QUOTA is not set # CONFIG_XFS_POSIX_ACL is not set # CONFIG_XFS_RT is not set @@ -5134,6 +5351,7 @@ CONFIG_XFS_SUPPORT_V4=y # CONFIG_BTRFS_FS is not set # CONFIG_NILFS2_FS is not set # CONFIG_F2FS_FS is not set +# CONFIG_BCACHEFS_FS is not set CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y # CONFIG_EXPORTFS_BLOCK_OPS is not set @@ -5145,7 +5363,6 @@ CONFIG_FSNOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_FANOTIFY is not set # CONFIG_QUOTA is not set -# CONFIG_AUTOFS4_FS is not set # CONFIG_AUTOFS_FS is not set CONFIG_FUSE_FS=y # CONFIG_CUSE is not set @@ -5156,6 +5373,7 @@ CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y # CONFIG_OVERLAY_FS_INDEX is not set # CONFIG_OVERLAY_FS_XINO_AUTO is not set # CONFIG_OVERLAY_FS_METACOPY is not set +# CONFIG_OVERLAY_FS_DEBUG is not set # # Caches @@ -5181,7 +5399,7 @@ CONFIG_ZISOFS=y # DOS/FAT/EXFAT/NT Filesystems # CONFIG_FAT_FS=y -# CONFIG_MSDOS_FS is not set +CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_FAT_DEFAULT_CODEPAGE=437 CONFIG_FAT_DEFAULT_IOCHARSET="ascii" @@ -5206,9 +5424,9 @@ CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_TMPFS_XATTR=y # CONFIG_TMPFS_INODE64 is not set +# CONFIG_TMPFS_QUOTA is not set CONFIG_ARCH_SUPPORTS_HUGETLBFS=y # CONFIG_HUGETLBFS is not set -CONFIG_MEMFD_CREATE=y CONFIG_ARCH_HAS_GIGANTIC_PAGE=y CONFIG_CONFIGFS_FS=y # end of Pseudo filesystems @@ -5227,9 +5445,11 @@ CONFIG_MISC_FILESYSTEMS=y CONFIG_SQUASHFS=y CONFIG_SQUASHFS_FILE_CACHE=y # CONFIG_SQUASHFS_FILE_DIRECT is not set -# CONFIG_SQUASHFS_DECOMP_SINGLE is not set -# CONFIG_SQUASHFS_DECOMP_MULTI is not set -CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +CONFIG_SQUASHFS_DECOMP_SINGLE=y +# CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set +CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y +# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set +# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set # CONFIG_SQUASHFS_XATTR is not set CONFIG_SQUASHFS_ZLIB=y CONFIG_SQUASHFS_LZ4=y @@ -5248,15 +5468,7 @@ CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 # CONFIG_ROMFS_FS is not set CONFIG_PSTORE=y CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 -CONFIG_PSTORE_DEFLATE_COMPRESS=y -# CONFIG_PSTORE_LZO_COMPRESS is not set -# CONFIG_PSTORE_LZ4_COMPRESS is not set -# CONFIG_PSTORE_LZ4HC_COMPRESS is not set -# CONFIG_PSTORE_842_COMPRESS is not set -# CONFIG_PSTORE_ZSTD_COMPRESS is not set CONFIG_PSTORE_COMPRESS=y -CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y -CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" # CONFIG_PSTORE_CONSOLE is not set # CONFIG_PSTORE_PMSG is not set # CONFIG_PSTORE_RAM is not set @@ -5342,7 +5554,6 @@ CONFIG_ENCRYPTED_KEYS=y # CONFIG_SECURITY_DMESG_RESTRICT is not set # CONFIG_SECURITY is not set CONFIG_SECURITYFS=y -CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y # CONFIG_HARDENED_USERCOPY is not set # CONFIG_FORTIFY_SOURCE is not set # CONFIG_STATIC_USERMODEHELPER is not set @@ -5363,12 +5574,19 @@ CONFIG_INIT_STACK_NONE=y # CONFIG_INIT_STACK_ALL_PATTERN is not set # CONFIG_INIT_STACK_ALL_ZERO is not set # CONFIG_GCC_PLUGIN_STACKLEAK is not set -# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set -# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y +CONFIG_INIT_ON_FREE_DEFAULT_ON=y CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y # CONFIG_ZERO_CALL_USED_REGS is not set # end of Memory initialization +# +# Hardening of kernel data structures +# +# CONFIG_LIST_HARDENED is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# end of Hardening of kernel data structures + CONFIG_RANDSTRUCT_NONE=y # CONFIG_RANDSTRUCT_FULL is not set # CONFIG_RANDSTRUCT_PERFORMANCE is not set @@ -5384,6 +5602,7 @@ CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_SIG2=y CONFIG_CRYPTO_SKCIPHER=y CONFIG_CRYPTO_SKCIPHER2=y CONFIG_CRYPTO_HASH=y @@ -5401,13 +5620,13 @@ CONFIG_CRYPTO_MANAGER2=y # CONFIG_CRYPTO_USER is not set # CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set # CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set -CONFIG_CRYPTO_GF128MUL=y CONFIG_CRYPTO_NULL=y CONFIG_CRYPTO_NULL2=y # CONFIG_CRYPTO_PCRYPT is not set CONFIG_CRYPTO_CRYPTD=y CONFIG_CRYPTO_AUTHENC=y # CONFIG_CRYPTO_TEST is not set +CONFIG_CRYPTO_ENGINE=m # end of Crypto core or helper # @@ -5471,6 +5690,7 @@ CONFIG_CRYPTO_ECB=y # CONFIG_CRYPTO_CHACHA20POLY1305 is not set CONFIG_CRYPTO_CCM=y CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_GENIV=y CONFIG_CRYPTO_SEQIV=y CONFIG_CRYPTO_ECHAINIV=y CONFIG_CRYPTO_ESSIV=m @@ -5491,7 +5711,7 @@ CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y -# CONFIG_CRYPTO_SHA3 is not set +CONFIG_CRYPTO_SHA3=y # CONFIG_CRYPTO_SM3_GENERIC is not set # CONFIG_CRYPTO_STREEBOG is not set # CONFIG_CRYPTO_VMAC is not set @@ -5530,6 +5750,9 @@ CONFIG_CRYPTO_DRBG_HMAC=y # CONFIG_CRYPTO_DRBG_CTR is not set CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64 +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32 +CONFIG_CRYPTO_JITTERENTROPY_OSR=1 # end of Random number generation # @@ -5570,10 +5793,21 @@ CONFIG_CRYPTO_POLY1305_NEON=y # CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set # CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set # CONFIG_CRYPTO_AES_ARM64_CE_CCM is not set +# CONFIG_CRYPTO_SM4_ARM64_CE_CCM is not set +# CONFIG_CRYPTO_SM4_ARM64_CE_GCM is not set # CONFIG_CRYPTO_CRCT10DIF_ARM64_CE is not set # end of Accelerated Cryptographic Algorithms for CPU (arm64) -# CONFIG_CRYPTO_HW is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set +# CONFIG_CRYPTO_DEV_CCP is not set +CONFIG_CRYPTO_DEV_ROCKCHIP=m +CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG=y +# CONFIG_CRYPTO_DEV_SAFEXCEL is not set +# CONFIG_CRYPTO_DEV_CCREE is not set +# CONFIG_CRYPTO_DEV_HISI_SEC is not set +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set CONFIG_ASYMMETRIC_KEY_TYPE=y CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y CONFIG_X509_CERTIFICATE_PARSER=y @@ -5620,6 +5854,7 @@ CONFIG_ARCH_USE_SYM_ANNOTATIONS=y CONFIG_CRYPTO_LIB_UTILS=y CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_LIB_ARC4=y +CONFIG_CRYPTO_LIB_GF128MUL=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y @@ -5665,7 +5900,6 @@ CONFIG_ZSTD_DECOMPRESS=y CONFIG_XZ_DEC=y # CONFIG_XZ_DEC_X86 is not set # CONFIG_XZ_DEC_POWERPC is not set -# CONFIG_XZ_DEC_IA64 is not set CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_ARMTHUMB=y # CONFIG_XZ_DEC_SPARC is not set @@ -5683,8 +5917,10 @@ CONFIG_GENERIC_ALLOCATOR=y CONFIG_XARRAY_MULTI=y CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y CONFIG_DMA_OPS=y +CONFIG_NEED_SG_DMA_FLAGS=y CONFIG_NEED_SG_DMA_LENGTH=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y @@ -5695,6 +5931,8 @@ CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y CONFIG_SWIOTLB=y +# CONFIG_SWIOTLB_DYNAMIC is not set +CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y # CONFIG_DMA_RESTRICTED_POOL is not set CONFIG_DMA_NONCOHERENT_MMAP=y CONFIG_DMA_COHERENT_POOL=y @@ -5721,6 +5959,7 @@ CONFIG_FONT_8x16=y CONFIG_SG_POOL=y CONFIG_ARCH_STACKWALK=y CONFIG_SBITMAP=y +# CONFIG_LWQ_TEST is not set # end of Library routines CONFIG_GENERIC_IOREMAP=y @@ -5812,10 +6051,11 @@ CONFIG_ARCH_HAS_DEBUG_WX=y # CONFIG_DEBUG_WX is not set CONFIG_GENERIC_PTDUMP=y # CONFIG_PTDUMP_DEBUGFS is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_SHRINKER_DEBUG is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_PER_VMA_LOCK_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SHRINKER_DEBUG is not set # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_SCHED_STACK_END_CHECK is not set CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y @@ -5845,8 +6085,13 @@ CONFIG_HAVE_ARCH_KFENCE=y CONFIG_PANIC_ON_OOPS_VALUE=0 CONFIG_PANIC_TIMEOUT=1 # CONFIG_SOFTLOCKUP_DETECTOR is not set -# CONFIG_DETECT_HUNG_TASK is not set +CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY=y +# CONFIG_HARDLOCKUP_DETECTOR is not set +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y # CONFIG_WQ_WATCHDOG is not set +# CONFIG_WQ_CPU_INTENSIVE_REPORT is not set # CONFIG_TEST_LOCKUP is not set # end of Debug Oops, Lockups and Hangs @@ -5854,7 +6099,8 @@ CONFIG_PANIC_TIMEOUT=1 # Scheduler Debugging # # CONFIG_SCHED_DEBUG is not set -# CONFIG_SCHEDSTATS is not set +CONFIG_SCHED_INFO=y +CONFIG_SCHEDSTATS=y # end of Scheduler Debugging # CONFIG_DEBUG_TIMEKEEPING is not set @@ -5866,7 +6112,7 @@ CONFIG_LOCK_DEBUGGING_SUPPORT=y # CONFIG_PROVE_LOCKING is not set # CONFIG_LOCK_STAT is not set # CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_DEBUG_SPINLOCK is not set +CONFIG_DEBUG_SPINLOCK=y # CONFIG_DEBUG_MUTEXES is not set # CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set # CONFIG_DEBUG_RWSEMS is not set @@ -5891,12 +6137,9 @@ CONFIG_STACKTRACE=y # CONFIG_DEBUG_PLIST is not set # CONFIG_DEBUG_SG is not set # CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_BUG_ON_DATA_CORRUPTION is not set # CONFIG_DEBUG_MAPLE_TREE is not set # end of Debug kernel data structures -# CONFIG_DEBUG_CREDENTIALS is not set - # # RCU Debugging # @@ -5905,6 +6148,7 @@ CONFIG_STACKTRACE=y # CONFIG_RCU_REF_SCALE_TEST is not set CONFIG_RCU_CPU_STALL_TIMEOUT=60 CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=20 +# CONFIG_RCU_CPU_STALL_CPUTIME is not set # CONFIG_RCU_TRACE is not set # CONFIG_RCU_EQS_DEBUG is not set # end of RCU Debugging @@ -5914,16 +6158,18 @@ CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=20 # CONFIG_LATENCYTOP is not set CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_RETVAL=y CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set # CONFIG_SAMPLES is not set -CONFIG_STRICT_DEVMEM=y -CONFIG_IO_STRICT_DEVMEM=y +CONFIG_HAVE_SAMPLE_FTRACE_DIRECT=y +CONFIG_HAVE_SAMPLE_FTRACE_DIRECT_MULTI=y +# CONFIG_STRICT_DEVMEM is not set # # arm64 Debugging diff --git a/projects/Rockchip/devices/RK3399/options b/projects/Rockchip/devices/RK3399/options index 417bb4253..07c923687 100644 --- a/projects/Rockchip/devices/RK3399/options +++ b/projects/Rockchip/devices/RK3399/options @@ -32,11 +32,13 @@ PARTITION_TABLE="msdos" DEVICE_DTB=("rk3399-anbernic-rg552") UBOOT_DTB="${DEVICE_DTB[0]}" + UBOOT_FIT_IMAGE="rk3399-uboot.bin" UBOOT_CONFIG="evb-rk3399_defconfig" PKG_SOC="rk3399" + ATF_PLATFORM="${PKG_SOC}" PKG_DATAFILE="$PKG_RKBIN/bin/rk33/rk3399_ddr_933MHz_v1.30.bin" PKG_LOADER="$PKG_RKBIN/bin/rk33/rk3399_miniloader_v1.26.bin" - PKG_BL31="$PKG_RKBIN/bin/rk33/rk3399_bl31_v1.36.elf" + ATF_BL31_BINARY="bl31/bl31.elf" BOOT_INI=false EXT_LINUX_CONF=true diff --git a/projects/Rockchip/packages/linux/package.mk b/projects/Rockchip/packages/linux/package.mk index ee12a17f9..336e82319 100644 --- a/projects/Rockchip/packages/linux/package.mk +++ b/projects/Rockchip/packages/linux/package.mk @@ -24,10 +24,14 @@ case ${DEVICE} in PKG_GIT_CLONE_BRANCH="main" ;; RK356*) - PKG_VERSION="6.7-rc8" - PKG_URL="https://git.kernel.org/torvalds/t/${PKG_NAME}-${PKG_VERSION}.tar.gz" + PKG_VERSION="6.7" + PKG_URL="https://www.kernel.org/pub/linux/kernel/v6.x/${PKG_NAME}-${PKG_VERSION}.tar.xz" ;; - RK33*) + RK3399) + PKG_VERSION="6.7" + PKG_URL="https://www.kernel.org/pub/linux/kernel/v6.x/${PKG_NAME}-${PKG_VERSION}.tar.xz" + ;; + RK3326) PKG_VERSION="6.1.70" PKG_URL="https://www.kernel.org/pub/linux/kernel/v6.x/${PKG_NAME}-${PKG_VERSION}.tar.xz" ;; @@ -174,6 +178,7 @@ make_target() { NO_GTK2=1 \ NO_LIBNUMA=1 \ NO_LIBAUDIT=1 \ + NO_LIBTRACEEVENT=1 \ NO_LZMA=1 \ NO_SDT=1 \ NO_LIBTRACEEVENT=1 \ diff --git a/projects/Rockchip/packages/linux/patches/RK3399/000-rk3399-dts.patch b/projects/Rockchip/packages/linux/patches/RK3399/000-rk3399-dts.patch index f589e1fc6..5c4014b2a 100644 --- a/projects/Rockchip/packages/linux/patches/RK3399/000-rk3399-dts.patch +++ b/projects/Rockchip/packages/linux/patches/RK3399/000-rk3399-dts.patch @@ -1,7 +1,7 @@ diff -rupN linux.orig/arch/arm64/boot/dts/rockchip/Makefile linux/arch/arm64/boot/dts/rockchip/Makefile ---- linux.orig/arch/arm64/boot/dts/rockchip/Makefile 2024-01-02 16:20:12.766155041 +0000 -+++ linux/arch/arm64/boot/dts/rockchip/Makefile 2024-01-02 21:22:52.154473211 +0000 -@@ -21,6 +21,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-li +--- linux.orig/arch/arm64/boot/dts/rockchip/Makefile 2024-01-09 14:07:11.858381650 +0000 ++++ linux/arch/arm64/boot/dts/rockchip/Makefile 2024-01-09 18:09:58.589953944 +0000 +@@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-li dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb @@ -11,8 +11,8 @@ diff -rupN linux.orig/arch/arm64/boot/dts/rockchip/Makefile linux/arch/arm64/boo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb diff -rupN linux.orig/arch/arm64/boot/dts/rockchip/rk3399-anbernic-rg552.dts linux/arch/arm64/boot/dts/rockchip/rk3399-anbernic-rg552.dts --- linux.orig/arch/arm64/boot/dts/rockchip/rk3399-anbernic-rg552.dts 1970-01-01 00:00:00.000000000 +0000 -+++ linux/arch/arm64/boot/dts/rockchip/rk3399-anbernic-rg552.dts 2024-01-02 22:48:46.115043990 +0000 -@@ -0,0 +1,1329 @@ ++++ linux/arch/arm64/boot/dts/rockchip/rk3399-anbernic-rg552.dts 2024-01-09 18:09:58.589953944 +0000 +@@ -0,0 +1,1336 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. @@ -265,7 +265,7 @@ diff -rupN linux.orig/arch/arm64/boot/dts/rockchip/rk3399-anbernic-rg552.dts lin + }; + + }; -+ ++ + es8316-sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; @@ -310,7 +310,7 @@ diff -rupN linux.orig/arch/arm64/boot/dts/rockchip/rk3399-anbernic-rg552.dts lin + hdmi-sound { + status = "okay"; + }; -+ ++ + fan: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm1 0 10000 1>; @@ -408,6 +408,17 @@ diff -rupN linux.orig/arch/arm64/boot/dts/rockchip/rk3399-anbernic-rg552.dts lin + vin-supply = <&vcc12v_dcin>; + }; + ++ /* switched by pmic_sleep */ ++ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc1v8_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc_1v8>; ++ }; ++ + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; @@ -617,10 +628,6 @@ diff -rupN linux.orig/arch/arm64/boot/dts/rockchip/rk3399-anbernic-rg552.dts lin + cpu-supply = <&vdd_cpu_b>; +}; + -+&saradc { -+ status = "okay"; -+}; -+ +&sdio0 { + clock-frequency = <150000000>; + clock-freq-min-max = <100000 150000000>; @@ -684,7 +691,7 @@ diff -rupN linux.orig/arch/arm64/boot/dts/rockchip/rk3399-anbernic-rg552.dts lin +}; + +&saradc { -+ vref-supply = <&vcc_1v8>; ++ vref-supply = <&vcca1v8_s3>; + status = "okay"; +}; + @@ -1196,7 +1203,7 @@ diff -rupN linux.orig/arch/arm64/boot/dts/rockchip/rk3399-anbernic-rg552.dts lin + + btns { + btn_pins: btn-pins { -+ rockchip,pins = ++ rockchip,pins = + <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, diff --git a/projects/Rockchip/packages/linux/patches/RK3399/003-singleadc-joypad.patch b/projects/Rockchip/packages/linux/patches/RK3399/003-singleadc-joypad.patch index 13864bf91..3500bd714 100644 --- a/projects/Rockchip/packages/linux/patches/RK3399/003-singleadc-joypad.patch +++ b/projects/Rockchip/packages/linux/patches/RK3399/003-singleadc-joypad.patch @@ -1,6 +1,52 @@ +diff -rupN linux.orig/drivers/gpio/gpiolib-of.c linux/drivers/gpio/gpiolib-of.c +--- linux.orig/drivers/gpio/gpiolib-of.c 2024-01-08 18:42:48.903867377 +0000 ++++ linux/drivers/gpio/gpiolib-of.c 2024-01-08 18:46:49.713063075 +0000 +@@ -25,21 +25,6 @@ + #include "gpiolib.h" + #include "gpiolib-of.h" + +-/* +- * This is Linux-specific flags. By default controllers' and Linux' mapping +- * match, but GPIO controllers are free to translate their own flags to +- * Linux-specific in their .xlate callback. Though, 1:1 mapping is recommended. +- */ +-enum of_gpio_flags { +- OF_GPIO_ACTIVE_LOW = 0x1, +- OF_GPIO_SINGLE_ENDED = 0x2, +- OF_GPIO_OPEN_DRAIN = 0x4, +- OF_GPIO_TRANSITORY = 0x8, +- OF_GPIO_PULL_UP = 0x10, +- OF_GPIO_PULL_DOWN = 0x20, +- OF_GPIO_PULL_DISABLE = 0x40, +-}; +- + /** + * of_gpio_named_count() - Count GPIOs for a device + * @np: device node to count GPIOs for +@@ -398,6 +383,20 @@ out: + return desc; + } + ++int of_get_named_gpio_flags(const struct device_node *np, const char *list_name, ++ int index, enum of_gpio_flags *flags) ++{ ++ struct gpio_desc *desc; ++ ++ desc = of_get_named_gpiod_flags(np, list_name, index, flags); ++ ++ if (IS_ERR(desc)) ++ return PTR_ERR(desc); ++ else ++ return desc_to_gpio(desc); ++} ++EXPORT_SYMBOL_GPL(of_get_named_gpio_flags); ++ + /** + * of_get_named_gpio() - Get a GPIO number to use with GPIO API + * @np: device node to get GPIO from diff -rupN linux.orig/drivers/input/Kconfig linux/drivers/input/Kconfig ---- linux.orig/drivers/input/Kconfig 2023-12-15 19:18:57.320911751 +0000 -+++ linux/drivers/input/Kconfig 2023-12-15 19:20:05.987107578 +0000 +--- linux.orig/drivers/input/Kconfig 2024-01-08 18:42:49.679884040 +0000 ++++ linux/drivers/input/Kconfig 2024-01-08 18:43:42.593020626 +0000 @@ -51,6 +51,19 @@ config INPUT_FF_MEMLESS To compile this driver as a module, choose M here: the module will be called ff-memless. @@ -22,8 +68,8 @@ diff -rupN linux.orig/drivers/input/Kconfig linux/drivers/input/Kconfig tristate "Sparse keymap support library" help diff -rupN linux.orig/drivers/input/Makefile linux/drivers/input/Makefile ---- linux.orig/drivers/input/Makefile 2023-12-15 19:18:57.320911751 +0000 -+++ linux/drivers/input/Makefile 2023-12-15 19:20:05.987107578 +0000 +--- linux.orig/drivers/input/Makefile 2024-01-08 18:42:49.679884040 +0000 ++++ linux/drivers/input/Makefile 2024-01-08 18:43:42.593020626 +0000 @@ -10,6 +10,7 @@ input-core-y := input.o input-compat.o i input-core-y += touchscreen.o @@ -34,7 +80,7 @@ diff -rupN linux.orig/drivers/input/Makefile linux/drivers/input/Makefile obj-$(CONFIG_INPUT_VIVALDIFMAP) += vivaldi-fmap.o diff -rupN linux.orig/drivers/input/input-polldev.c linux/drivers/input/input-polldev.c --- linux.orig/drivers/input/input-polldev.c 1970-01-01 00:00:00.000000000 +0000 -+++ linux/drivers/input/input-polldev.c 2023-12-15 19:20:05.987107578 +0000 ++++ linux/drivers/input/input-polldev.c 2024-01-08 18:43:42.593020626 +0000 @@ -0,0 +1,362 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* @@ -399,8 +445,8 @@ diff -rupN linux.orig/drivers/input/input-polldev.c linux/drivers/input/input-po +} +EXPORT_SYMBOL(input_unregister_polled_device); diff -rupN linux.orig/drivers/input/joystick/Kconfig linux/drivers/input/joystick/Kconfig ---- linux.orig/drivers/input/joystick/Kconfig 2023-12-15 19:18:57.324911879 +0000 -+++ linux/drivers/input/joystick/Kconfig 2023-12-15 19:20:05.987107578 +0000 +--- linux.orig/drivers/input/joystick/Kconfig 2024-01-08 18:42:49.679884040 +0000 ++++ linux/drivers/input/joystick/Kconfig 2024-01-08 18:43:42.593020626 +0000 @@ -393,6 +393,12 @@ config JOYSTICK_FSIA6B To compile this driver as a module, choose M here: the module will be called fsia6b. @@ -415,8 +461,8 @@ diff -rupN linux.orig/drivers/input/joystick/Kconfig linux/drivers/input/joystic bool "N64 controller" depends on MACH_NINTENDO64 diff -rupN linux.orig/drivers/input/joystick/Makefile linux/drivers/input/joystick/Makefile ---- linux.orig/drivers/input/joystick/Makefile 2023-12-15 19:18:57.324911879 +0000 -+++ linux/drivers/input/joystick/Makefile 2023-12-15 19:20:05.987107578 +0000 +--- linux.orig/drivers/input/joystick/Makefile 2024-01-08 18:42:49.679884040 +0000 ++++ linux/drivers/input/joystick/Makefile 2024-01-08 18:43:42.593020626 +0000 @@ -30,6 +30,7 @@ obj-$(CONFIG_JOYSTICK_PXRC) += pxrc.o obj-$(CONFIG_JOYSTICK_QWIIC) += qwiic-joystick.o obj-$(CONFIG_JOYSTICK_SENSEHAT) += sensehat-joystick.o @@ -427,8 +473,8 @@ diff -rupN linux.orig/drivers/input/joystick/Makefile linux/drivers/input/joysti obj-$(CONFIG_JOYSTICK_STINGER) += stinger.o diff -rupN linux.orig/drivers/input/joystick/singleadcjoy.c linux/drivers/input/joystick/singleadcjoy.c --- linux.orig/drivers/input/joystick/singleadcjoy.c 1970-01-01 00:00:00.000000000 +0000 -+++ linux/drivers/input/joystick/singleadcjoy.c 2023-12-15 19:36:26.739762439 +0000 -@@ -0,0 +1,1416 @@ ++++ linux/drivers/input/joystick/singleadcjoy.c 2024-01-08 18:43:54.081267482 +0000 +@@ -0,0 +1,1448 @@ +/*----------------------------------------------------------------------------*/ + +/* @@ -1162,35 +1208,67 @@ diff -rupN linux.orig/drivers/input/joystick/singleadcjoy.c linux/drivers/input/ +{ + struct joypad *joypad = poll_dev->private; + int nbtn; ++ int mag; + -+ for (nbtn = 0; nbtn < joypad->amux_count; nbtn++) { -+ struct bt_adc *adc = &joypad->adcs[nbtn]; ++ /* Assumes an even number of axes and that joystick axis pairs are sequential */ ++ /* e.g. left stick Y immediately follows left stick X */ ++ for (nbtn = 0; nbtn < joypad->amux_count; nbtn+=2) { ++ struct bt_adc *adcx = &joypad->adcs[nbtn]; ++ struct bt_adc *adcy = &joypad->adcs[nbtn + 1]; + -+ adc->value = joypad_adc_read(joypad->amux, adc); -+ if (!adc->value) { ++ /* Read first joystick axis */ ++ adcx->value = joypad_adc_read(joypad->amux, adcx); ++ if (!adcx->value) { + //dev_err(joypad->dev, "%s : saradc channels[%d]! adc->value : %d\n",__func__, nbtn, adc->value); + continue; + } -+ adc->value = adc->value - adc->cal; ++ adcx->value = adcx->value - adcx->cal; ++ ++ /* Read second joystick axis */ ++ adcy->value = joypad_adc_read(joypad->amux, adcy); ++ if (!adcy->value) { ++ //dev_err(joypad->dev, "%s : saradc channels[%d]! adc->value : %d\n",__func__, nbtn, adc->value); ++ continue; ++ } ++ adcy->value = adcy->value - adcy->cal; + + /* Joystick Deadzone check */ ++ mag = int_sqrt((adcx->value * adcx->value) + (adcy->value * adcy->value)); + if (joypad->bt_adc_deadzone) { -+ if (abs(adc->value) < joypad->bt_adc_deadzone) -+ adc->value = 0; ++ if (mag <= joypad->bt_adc_deadzone) { ++ adcx->value = 0; ++ adcy->value = 0; ++ } ++ else { ++ /* Assumes adcx->max == -adcx->min == adcy->max == -adcy->min */ ++ /* Order of operations is critical to avoid integer overflow */ ++ adcx->value = (((adcx->max * adcx->value) / mag) * (mag - joypad->bt_adc_deadzone)) / (adcx->max - joypad->bt_adc_deadzone); ++ adcy->value = (((adcy->max * adcy->value) / mag) * (mag - joypad->bt_adc_deadzone)) / (adcy->max - joypad->bt_adc_deadzone); ++ } + } + + /* adc data tuning */ -+ if (adc->tuning_n && adc->value < 0) -+ adc->value = ADC_DATA_TUNING(adc->value, adc->tuning_n); -+ if (adc->tuning_p && adc->value > 0) -+ adc->value = ADC_DATA_TUNING(adc->value, adc->tuning_p); ++ if (adcx->tuning_n && adcx->value < 0) ++ adcx->value = ADC_DATA_TUNING(adcx->value, adcx->tuning_n); ++ if (adcx->tuning_p && adcx->value > 0) ++ adcx->value = ADC_DATA_TUNING(adcx->value, adcx->tuning_p); ++ if (adcy->tuning_n && adcy->value < 0) ++ adcy->value = ADC_DATA_TUNING(adcy->value, adcy->tuning_n); ++ if (adcy->tuning_p && adcy->value > 0) ++ adcy->value = ADC_DATA_TUNING(adcy->value, adcy->tuning_p); + -+ adc->value = adc->value > adc->max ? adc->max : adc->value; -+ adc->value = adc->value < adc->min ? adc->min : adc->value; ++ /* Clamp to [min, max] */ ++ adcx->value = adcx->value > adcx->max ? adcx->max : adcx->value; ++ adcx->value = adcx->value < adcx->min ? adcx->min : adcx->value; ++ adcy->value = adcy->value > adcy->max ? adcy->max : adcy->value; ++ adcy->value = adcy->value < adcy->min ? adcy->min : adcy->value; + + input_report_abs(poll_dev->input, -+ adc->report_type, -+ adc->invert ? adc->value * (-1) : adc->value); ++ adcx->report_type, ++ adcx->invert ? adcx->value * (-1) : adcx->value); ++ input_report_abs(poll_dev->input, ++ adcy->report_type, ++ adcy->invert ? adcy->value * (-1) : adcy->value); + } + input_sync(poll_dev->input); +} @@ -1847,7 +1925,7 @@ diff -rupN linux.orig/drivers/input/joystick/singleadcjoy.c linux/drivers/input/ +module_exit(joypad_exit); diff -rupN linux.orig/include/linux/input-polldev.h linux/include/linux/input-polldev.h --- linux.orig/include/linux/input-polldev.h 1970-01-01 00:00:00.000000000 +0000 -+++ linux/include/linux/input-polldev.h 2023-12-15 19:20:05.987107578 +0000 ++++ linux/include/linux/input-polldev.h 2024-01-08 18:43:42.593020626 +0000 @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _INPUT_POLLDEV_H @@ -1907,3 +1985,65 @@ diff -rupN linux.orig/include/linux/input-polldev.h linux/include/linux/input-po +void input_unregister_polled_device(struct input_polled_dev *dev); + +#endif +diff -rupN linux.orig/include/linux/of_gpio.h linux/include/linux/of_gpio.h +--- linux.orig/include/linux/of_gpio.h 2024-01-08 18:42:51.555924323 +0000 ++++ linux/include/linux/of_gpio.h 2024-01-08 19:08:52.942972824 +0000 +@@ -17,8 +17,26 @@ + + struct device_node; + ++/* ++ * This is Linux-specific flags. By default controllers' and Linux' mapping ++ * match, but GPIO controllers are free to translate their own flags to ++ * Linux-specific in their .xlate callback. Though, 1:1 mapping is recommended. ++ */ ++enum of_gpio_flags { ++ OF_GPIO_ACTIVE_LOW = 0x1, ++ OF_GPIO_SINGLE_ENDED = 0x2, ++ OF_GPIO_OPEN_DRAIN = 0x4, ++ OF_GPIO_TRANSITORY = 0x8, ++ OF_GPIO_PULL_UP = 0x10, ++ OF_GPIO_PULL_DOWN = 0x20, ++ OF_GPIO_PULL_DISABLE = 0x40, ++}; ++ + #ifdef CONFIG_OF_GPIO + ++extern int of_get_named_gpio_flags(const struct device_node *np, ++ const char *list_name, int index, enum of_gpio_flags *flags); ++ + extern int of_get_named_gpio(const struct device_node *np, + const char *list_name, int index); + +@@ -26,13 +44,30 @@ extern int of_get_named_gpio(const struc + + #include + +-/* Drivers may not strictly depend on the GPIO support, so let them link. */ + static inline int of_get_named_gpio(const struct device_node *np, + const char *propname, int index) + { ++ return -ENOSYS; ++} ++ ++/* Drivers may not strictly depend on the GPIO support, so let them link. */ ++static inline int of_get_named_gpio_flags(const struct device_node *np, ++ const char *list_name, int index, enum of_gpio_flags *flags) ++{ ++ if (flags) ++ *flags = 0; ++ + return -ENOSYS; + } + + #endif /* CONFIG_OF_GPIO */ + ++static inline int of_get_gpio_flags(const struct device_node *np, int index, ++ enum of_gpio_flags *flags) ++{ ++ return of_get_named_gpio_flags(np, "gpios", index, flags); ++} ++ ++//#endif /* CONFIG_OF_GPIO */ ++ + #endif /* __LINUX_OF_GPIO_H */ diff --git a/projects/Rockchip/packages/linux/patches/RK3399/005-battery-name.patch b/projects/Rockchip/packages/linux/patches/RK3399/004-battery-name.patch similarity index 100% rename from projects/Rockchip/packages/linux/patches/RK3399/005-battery-name.patch rename to projects/Rockchip/packages/linux/patches/RK3399/004-battery-name.patch diff --git a/projects/Rockchip/packages/linux/patches/RK3399/004-singleadc-deadzone.patch b/projects/Rockchip/packages/linux/patches/RK3399/004-singleadc-deadzone.patch deleted file mode 100644 index 6a8c85b4c..000000000 --- a/projects/Rockchip/packages/linux/patches/RK3399/004-singleadc-deadzone.patch +++ /dev/null @@ -1,100 +0,0 @@ -From c731e0b23383c8b451932331f22122afe04348bd Mon Sep 17 00:00:00 2001 -From: Johnny on Flame -Date: Fri, 3 Nov 2023 04:53:33 +0000 -Subject: [PATCH] Port radial thresholding from @littleguy77. - ---- - drivers/input/joystick/singleadcjoy.c | 64 ++++++++++++++++++++------- - 1 file changed, 48 insertions(+), 16 deletions(-) - -diff --git a/drivers/input/joystick/singleadcjoy.c b/drivers/input/joystick/singleadcjoy.c -index f0a24a24a..455e11121 100644 ---- a/drivers/input/joystick/singleadcjoy.c -+++ b/drivers/input/joystick/singleadcjoy.c -@@ -580,35 +580,67 @@ static void joypad_adc_check(struct input_polled_dev *poll_dev) - { - struct joypad *joypad = poll_dev->private; - int nbtn; -+ int mag; - -- for (nbtn = 0; nbtn < joypad->amux_count; nbtn++) { -- struct bt_adc *adc = &joypad->adcs[nbtn]; -+ /* Assumes an even number of axes and that joystick axis pairs are sequential */ -+ /* e.g. left stick Y immediately follows left stick X */ -+ for (nbtn = 0; nbtn < joypad->amux_count; nbtn+=2) { -+ struct bt_adc *adcx = &joypad->adcs[nbtn]; -+ struct bt_adc *adcy = &joypad->adcs[nbtn + 1]; - -- adc->value = joypad_adc_read(joypad->amux, adc); -- if (!adc->value) { -+ /* Read first joystick axis */ -+ adcx->value = joypad_adc_read(joypad->amux, adcx); -+ if (!adcx->value) { -+ //dev_err(joypad->dev, "%s : saradc channels[%d]! adc->value : %d\n",__func__, nbtn, adc->value); -+ continue; -+ } -+ adcx->value = adcx->value - adcx->cal; -+ -+ /* Read second joystick axis */ -+ adcy->value = joypad_adc_read(joypad->amux, adcy); -+ if (!adcy->value) { - //dev_err(joypad->dev, "%s : saradc channels[%d]! adc->value : %d\n",__func__, nbtn, adc->value); - continue; - } -- adc->value = adc->value - adc->cal; -+ adcy->value = adcy->value - adcy->cal; - - /* Joystick Deadzone check */ -+ mag = int_sqrt((adcx->value * adcx->value) + (adcy->value * adcy->value)); - if (joypad->bt_adc_deadzone) { -- if (abs(adc->value) < joypad->bt_adc_deadzone) -- adc->value = 0; -+ if (mag <= joypad->bt_adc_deadzone) { -+ adcx->value = 0; -+ adcy->value = 0; -+ } -+ else { -+ /* Assumes adcx->max == -adcx->min == adcy->max == -adcy->min */ -+ /* Order of operations is critical to avoid integer overflow */ -+ adcx->value = (((adcx->max * adcx->value) / mag) * (mag - joypad->bt_adc_deadzone)) / (adcx->max - joypad->bt_adc_deadzone); -+ adcy->value = (((adcy->max * adcy->value) / mag) * (mag - joypad->bt_adc_deadzone)) / (adcy->max - joypad->bt_adc_deadzone); -+ } - } - - /* adc data tuning */ -- if (adc->tuning_n && adc->value < 0) -- adc->value = ADC_DATA_TUNING(adc->value, adc->tuning_n); -- if (adc->tuning_p && adc->value > 0) -- adc->value = ADC_DATA_TUNING(adc->value, adc->tuning_p); -- -- adc->value = adc->value > adc->max ? adc->max : adc->value; -- adc->value = adc->value < adc->min ? adc->min : adc->value; -+ if (adcx->tuning_n && adcx->value < 0) -+ adcx->value = ADC_DATA_TUNING(adcx->value, adcx->tuning_n); -+ if (adcx->tuning_p && adcx->value > 0) -+ adcx->value = ADC_DATA_TUNING(adcx->value, adcx->tuning_p); -+ if (adcy->tuning_n && adcy->value < 0) -+ adcy->value = ADC_DATA_TUNING(adcy->value, adcy->tuning_n); -+ if (adcy->tuning_p && adcy->value > 0) -+ adcy->value = ADC_DATA_TUNING(adcy->value, adcy->tuning_p); -+ -+ /* Clamp to [min, max] */ -+ adcx->value = adcx->value > adcx->max ? adcx->max : adcx->value; -+ adcx->value = adcx->value < adcx->min ? adcx->min : adcx->value; -+ adcy->value = adcy->value > adcy->max ? adcy->max : adcy->value; -+ adcy->value = adcy->value < adcy->min ? adcy->min : adcy->value; - - input_report_abs(poll_dev->input, -- adc->report_type, -- adc->invert ? adc->value * (-1) : adc->value); -+ adcx->report_type, -+ adcx->invert ? adcx->value * (-1) : adcx->value); -+ input_report_abs(poll_dev->input, -+ adcy->report_type, -+ adcy->invert ? adcy->value * (-1) : adcy->value); - } - input_sync(poll_dev->input); - } --- -2.34.1 - diff --git a/projects/Rockchip/packages/linux/patches/RK3399/005-adc-revert.patch b/projects/Rockchip/packages/linux/patches/RK3399/005-adc-revert.patch new file mode 100644 index 000000000..3e9e69490 --- /dev/null +++ b/projects/Rockchip/packages/linux/patches/RK3399/005-adc-revert.patch @@ -0,0 +1,403 @@ +diff -rupN linux.orig/drivers/iio/adc/rockchip_saradc.c linux/drivers/iio/adc/rockchip_saradc.c +--- linux.orig/drivers/iio/adc/rockchip_saradc.c 2024-01-09 14:07:12.430393829 +0000 ++++ linux/drivers/iio/adc/rockchip_saradc.c 2024-01-09 16:30:43.561613614 +0000 +@@ -4,13 +4,13 @@ + * Copyright (C) 2014 ROCKCHIP, Inc. + */ + +-#include + #include + #include + #include + #include + #include + #include ++#include + #include + #include + #include +@@ -38,31 +38,10 @@ + #define SARADC_TIMEOUT msecs_to_jiffies(100) + #define SARADC_MAX_CHANNELS 8 + +-/* v2 registers */ +-#define SARADC2_CONV_CON 0x000 +-#define SARADC_T_PD_SOC 0x004 +-#define SARADC_T_DAS_SOC 0x00c +-#define SARADC2_END_INT_EN 0x104 +-#define SARADC2_ST_CON 0x108 +-#define SARADC2_STATUS 0x10c +-#define SARADC2_END_INT_ST 0x110 +-#define SARADC2_DATA_BASE 0x120 +- +-#define SARADC2_EN_END_INT BIT(0) +-#define SARADC2_START BIT(4) +-#define SARADC2_SINGLE_MODE BIT(5) +- +-#define SARADC2_CONV_CHANNELS GENMASK(15, 0) +- +-struct rockchip_saradc; +- + struct rockchip_saradc_data { + const struct iio_chan_spec *channels; + int num_channels; + unsigned long clk_rate; +- void (*start)(struct rockchip_saradc *info, int chn); +- int (*read)(struct rockchip_saradc *info); +- void (*power_down)(struct rockchip_saradc *info); + }; + + struct rockchip_saradc { +@@ -81,81 +60,27 @@ struct rockchip_saradc { + struct notifier_block nb; + }; + +-static void rockchip_saradc_reset_controller(struct reset_control *reset); +- +-static void rockchip_saradc_start_v1(struct rockchip_saradc *info, int chn) +-{ +- /* 8 clock periods as delay between power up and start cmd */ +- writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC); +- /* Select the channel to be used and trigger conversion */ +- writel(SARADC_CTRL_POWER_CTRL | (chn & SARADC_CTRL_CHN_MASK) | +- SARADC_CTRL_IRQ_ENABLE, info->regs + SARADC_CTRL); +-} +- +-static void rockchip_saradc_start_v2(struct rockchip_saradc *info, int chn) +-{ +- int val; +- +- if (info->reset) +- rockchip_saradc_reset_controller(info->reset); +- +- writel_relaxed(0xc, info->regs + SARADC_T_DAS_SOC); +- writel_relaxed(0x20, info->regs + SARADC_T_PD_SOC); +- val = FIELD_PREP(SARADC2_EN_END_INT, 1); +- val |= val << 16; +- writel_relaxed(val, info->regs + SARADC2_END_INT_EN); +- val = FIELD_PREP(SARADC2_START, 1) | +- FIELD_PREP(SARADC2_SINGLE_MODE, 1) | +- FIELD_PREP(SARADC2_CONV_CHANNELS, chn); +- val |= val << 16; +- writel(val, info->regs + SARADC2_CONV_CON); +-} +- +-static void rockchip_saradc_start(struct rockchip_saradc *info, int chn) +-{ +- info->data->start(info, chn); +-} +- +-static int rockchip_saradc_read_v1(struct rockchip_saradc *info) +-{ +- return readl_relaxed(info->regs + SARADC_DATA); +-} +- +-static int rockchip_saradc_read_v2(struct rockchip_saradc *info) +-{ +- int offset; +- +- /* Clear irq */ +- writel_relaxed(0x1, info->regs + SARADC2_END_INT_ST); +- +- offset = SARADC2_DATA_BASE + info->last_chan->channel * 0x4; +- +- return readl_relaxed(info->regs + offset); +-} +- +-static int rockchip_saradc_read(struct rockchip_saradc *info) +-{ +- return info->data->read(info); +-} +- +-static void rockchip_saradc_power_down_v1(struct rockchip_saradc *info) +-{ +- writel_relaxed(0, info->regs + SARADC_CTRL); +-} +- + static void rockchip_saradc_power_down(struct rockchip_saradc *info) + { +- if (info->data->power_down) +- info->data->power_down(info); ++ /* Clear irq & power down adc */ ++ writel_relaxed(0, info->regs + SARADC_CTRL); + } + + static int rockchip_saradc_conversion(struct rockchip_saradc *info, +- struct iio_chan_spec const *chan) ++ struct iio_chan_spec const *chan) + { + reinit_completion(&info->completion); + ++ /* 8 clock periods as delay between power up and start cmd */ ++ writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC); ++ + info->last_chan = chan; +- rockchip_saradc_start(info, chan->channel); ++ ++ /* Select the channel to be used and trigger conversion */ ++ writel(SARADC_CTRL_POWER_CTRL ++ | (chan->channel & SARADC_CTRL_CHN_MASK) ++ | SARADC_CTRL_IRQ_ENABLE, ++ info->regs + SARADC_CTRL); + + if (!wait_for_completion_timeout(&info->completion, SARADC_TIMEOUT)) + return -ETIMEDOUT; +@@ -198,7 +123,7 @@ static irqreturn_t rockchip_saradc_isr(i + struct rockchip_saradc *info = dev_id; + + /* Read value */ +- info->last_val = rockchip_saradc_read(info); ++ info->last_val = readl_relaxed(info->regs + SARADC_DATA); + info->last_val &= GENMASK(info->last_chan->scan_type.realbits - 1, 0); + + rockchip_saradc_power_down(info); +@@ -238,9 +163,6 @@ static const struct rockchip_saradc_data + .channels = rockchip_saradc_iio_channels, + .num_channels = ARRAY_SIZE(rockchip_saradc_iio_channels), + .clk_rate = 1000000, +- .start = rockchip_saradc_start_v1, +- .read = rockchip_saradc_read_v1, +- .power_down = rockchip_saradc_power_down_v1, + }; + + static const struct iio_chan_spec rockchip_rk3066_tsadc_iio_channels[] = { +@@ -252,9 +174,6 @@ static const struct rockchip_saradc_data + .channels = rockchip_rk3066_tsadc_iio_channels, + .num_channels = ARRAY_SIZE(rockchip_rk3066_tsadc_iio_channels), + .clk_rate = 50000, +- .start = rockchip_saradc_start_v1, +- .read = rockchip_saradc_read_v1, +- .power_down = rockchip_saradc_power_down_v1, + }; + + static const struct iio_chan_spec rockchip_rk3399_saradc_iio_channels[] = { +@@ -270,9 +189,6 @@ static const struct rockchip_saradc_data + .channels = rockchip_rk3399_saradc_iio_channels, + .num_channels = ARRAY_SIZE(rockchip_rk3399_saradc_iio_channels), + .clk_rate = 1000000, +- .start = rockchip_saradc_start_v1, +- .read = rockchip_saradc_read_v1, +- .power_down = rockchip_saradc_power_down_v1, + }; + + static const struct iio_chan_spec rockchip_rk3568_saradc_iio_channels[] = { +@@ -290,28 +206,6 @@ static const struct rockchip_saradc_data + .channels = rockchip_rk3568_saradc_iio_channels, + .num_channels = ARRAY_SIZE(rockchip_rk3568_saradc_iio_channels), + .clk_rate = 1000000, +- .start = rockchip_saradc_start_v1, +- .read = rockchip_saradc_read_v1, +- .power_down = rockchip_saradc_power_down_v1, +-}; +- +-static const struct iio_chan_spec rockchip_rk3588_saradc_iio_channels[] = { +- SARADC_CHANNEL(0, "adc0", 12), +- SARADC_CHANNEL(1, "adc1", 12), +- SARADC_CHANNEL(2, "adc2", 12), +- SARADC_CHANNEL(3, "adc3", 12), +- SARADC_CHANNEL(4, "adc4", 12), +- SARADC_CHANNEL(5, "adc5", 12), +- SARADC_CHANNEL(6, "adc6", 12), +- SARADC_CHANNEL(7, "adc7", 12), +-}; +- +-static const struct rockchip_saradc_data rk3588_saradc_data = { +- .channels = rockchip_rk3588_saradc_iio_channels, +- .num_channels = ARRAY_SIZE(rockchip_rk3588_saradc_iio_channels), +- .clk_rate = 1000000, +- .start = rockchip_saradc_start_v2, +- .read = rockchip_saradc_read_v2, + }; + + static const struct of_device_id rockchip_saradc_match[] = { +@@ -327,9 +221,6 @@ static const struct of_device_id rockchi + }, { + .compatible = "rockchip,rk3568-saradc", + .data = &rk3568_saradc_data, +- }, { +- .compatible = "rockchip,rk3588-saradc", +- .data = &rk3588_saradc_data, + }, + {}, + }; +@@ -345,6 +236,20 @@ static void rockchip_saradc_reset_contro + reset_control_deassert(reset); + } + ++static void rockchip_saradc_clk_disable(void *data) ++{ ++ struct rockchip_saradc *info = data; ++ ++ clk_disable_unprepare(info->clk); ++} ++ ++static void rockchip_saradc_pclk_disable(void *data) ++{ ++ struct rockchip_saradc *info = data; ++ ++ clk_disable_unprepare(info->pclk); ++} ++ + static void rockchip_saradc_regulator_disable(void *data) + { + struct rockchip_saradc *info = data; +@@ -393,7 +298,8 @@ out: + } + + static int rockchip_saradc_volt_notify(struct notifier_block *nb, +- unsigned long event, void *data) ++ unsigned long event, ++ void *data) + { + struct rockchip_saradc *info = + container_of(nb, struct rockchip_saradc, nb); +@@ -413,10 +319,10 @@ static void rockchip_saradc_regulator_un + + static int rockchip_saradc_probe(struct platform_device *pdev) + { +- const struct rockchip_saradc_data *match_data; + struct rockchip_saradc *info = NULL; + struct device_node *np = pdev->dev.of_node; + struct iio_dev *indio_dev = NULL; ++ const struct of_device_id *match; + int ret; + int irq; + +@@ -424,23 +330,25 @@ static int rockchip_saradc_probe(struct + return -ENODEV; + + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info)); +- if (!indio_dev) +- return dev_err_probe(&pdev->dev, -ENOMEM, +- "failed allocating iio device\n"); +- ++ if (!indio_dev) { ++ dev_err(&pdev->dev, "failed allocating iio device\n"); ++ return -ENOMEM; ++ } + info = iio_priv(indio_dev); + +- match_data = of_device_get_match_data(&pdev->dev); +- if (!match_data) +- return dev_err_probe(&pdev->dev, -ENODEV, +- "failed to match device\n"); ++ match = of_match_device(rockchip_saradc_match, &pdev->dev); ++ if (!match) { ++ dev_err(&pdev->dev, "failed to match device\n"); ++ return -ENODEV; ++ } + +- info->data = match_data; ++ info->data = match->data; + + /* Sanity check for possible later IP variants with more channels */ +- if (info->data->num_channels > SARADC_MAX_CHANNELS) +- return dev_err_probe(&pdev->dev, -EINVAL, +- "max channels exceeded"); ++ if (info->data->num_channels > SARADC_MAX_CHANNELS) { ++ dev_err(&pdev->dev, "max channels exceeded"); ++ return -EINVAL; ++ } + + info->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(info->regs)) +@@ -466,7 +374,7 @@ static int rockchip_saradc_probe(struct + + irq = platform_get_irq(pdev, 0); + if (irq < 0) +- return irq; ++ return dev_err_probe(&pdev->dev, irq, "failed to get irq\n"); + + ret = devm_request_irq(&pdev->dev, irq, rockchip_saradc_isr, + 0, dev_name(&pdev->dev), info); +@@ -475,6 +383,16 @@ static int rockchip_saradc_probe(struct + return ret; + } + ++ info->pclk = devm_clk_get(&pdev->dev, "apb_pclk"); ++ if (IS_ERR(info->pclk)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(info->pclk), ++ "failed to get pclk\n"); ++ ++ info->clk = devm_clk_get(&pdev->dev, "saradc"); ++ if (IS_ERR(info->clk)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(info->clk), ++ "failed to get adc clock\n"); ++ + info->vref = devm_regulator_get(&pdev->dev, "vref"); + if (IS_ERR(info->vref)) + return dev_err_probe(&pdev->dev, PTR_ERR(info->vref), +@@ -488,20 +406,23 @@ static int rockchip_saradc_probe(struct + * This may become user-configurable in the future. + */ + ret = clk_set_rate(info->clk, info->data->clk_rate); +- if (ret < 0) +- return dev_err_probe(&pdev->dev, ret, +- "failed to set adc clk rate\n"); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "failed to set adc clk rate, %d\n", ret); ++ return ret; ++ } + + ret = regulator_enable(info->vref); +- if (ret < 0) +- return dev_err_probe(&pdev->dev, ret, +- "failed to enable vref regulator\n"); +- ++ if (ret < 0) { ++ dev_err(&pdev->dev, "failed to enable vref regulator\n"); ++ return ret; ++ } + ret = devm_add_action_or_reset(&pdev->dev, + rockchip_saradc_regulator_disable, info); +- if (ret) +- return dev_err_probe(&pdev->dev, ret, +- "failed to register devm action\n"); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to register devm action, %d\n", ++ ret); ++ return ret; ++ } + + ret = regulator_get_voltage(info->vref); + if (ret < 0) +@@ -509,15 +430,31 @@ static int rockchip_saradc_probe(struct + + info->uv_vref = ret; + +- info->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk"); +- if (IS_ERR(info->pclk)) +- return dev_err_probe(&pdev->dev, PTR_ERR(info->pclk), +- "failed to get pclk\n"); ++ ret = clk_prepare_enable(info->pclk); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "failed to enable pclk\n"); ++ return ret; ++ } ++ ret = devm_add_action_or_reset(&pdev->dev, ++ rockchip_saradc_pclk_disable, info); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to register devm action, %d\n", ++ ret); ++ return ret; ++ } + +- info->clk = devm_clk_get_enabled(&pdev->dev, "saradc"); +- if (IS_ERR(info->clk)) +- return dev_err_probe(&pdev->dev, PTR_ERR(info->clk), +- "failed to get adc clock\n"); ++ ret = clk_prepare_enable(info->clk); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "failed to enable converter clock\n"); ++ return ret; ++ } ++ ret = devm_add_action_or_reset(&pdev->dev, ++ rockchip_saradc_clk_disable, info); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to register devm action, %d\n", ++ ret); ++ return ret; ++ } + + platform_set_drvdata(pdev, indio_dev); + diff --git a/projects/Rockchip/packages/linux/patches/RK3399/006-rtl8188fu-wifi.patch b/projects/Rockchip/packages/linux/patches/RK3399/006-rtl8188fu-wifi.patch deleted file mode 100644 index 3e8131a0e..000000000 --- a/projects/Rockchip/packages/linux/patches/RK3399/006-rtl8188fu-wifi.patch +++ /dev/null @@ -1,2388 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# Copyright (C) 2022 Batocera (https://github.com/batocera-linux/batocera.linux) -(https://github.com/batocera-linux/batocera.linux/blob/989ccefd2c174e2f850991c1639f346ce003f504/board/batocera/rockchip/rk3399/linux_patches/linux-0003-drivers-support-chip-RTL8188FU.patch#L1032) - -From patchwork Wed Sep 28 21:16:46 2022 -Content-Type: text/plain; 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- Wed, 28 Sep 2022 14:16:48 -0700 (PDT) -Message-ID: -Date: Thu, 29 Sep 2022 00:16:46 +0300 -MIME-Version: 1.0 -User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 - Thunderbird/91.12.0 -Content-Language: en-US -To: linux-wireless@vger.kernel.org -Cc: Jes Sorensen -From: Bitterblue Smith -Subject: [PATCH v3] wifi: rtl8xxxu: Support new chip RTL8188FU -Precedence: bulk -List-ID: -X-Mailing-List: linux-wireless@vger.kernel.org - -This chip is found in the cheapest USB adapters, e.g. 1.17 USD with -VAT and shipping from China included. - -It's a gen 2 chip, similar to the RTL8723BU, but without Bluetooth. -Features: 2.4 GHz, b/g/n mode, 1T1R, 150 Mbps. - -The vendor driver rtl8188fu version 4.3.23.6_20964.20170110 [0] -was used as reference. The CD shipped with the device includes a -newer driver, version 5.11.5-1-g12f7cde4b.20201102, but that one -couldn't complete the WPA2 key exchange thing for whatever reason. - -[0] https://github.com/kelebek333/rtl8188fu - -Signed-off-by: Bitterblue Smith ---- -v3: -- Address comments from Kalle Valo: - - Use SPDX tags. - - Make the arrays in rtl8188f_spur_calibration static const. - - Make sure all comments have a space after /* and before */. - - Put an empty line before some comments. - - Avoid indenting a block in rtl8188fu_phy_iqcalibrate. - - Move two macros outside of rtl8188f_enable_rf. -- Remove an if whose condition was always true in - rtl8188fu_config_channel. -- Remove two unnecessary memcpy in rtl8188fu_parse_efuse. -- Fix small mistakes in rtl8188fu_config_channel, - rtl8188f_phy_lc_calibrate, and rtl8188fu_phy_iqcalibrate. - -v2: -- Make some functions static, remove an unused variable. -Reported-by: kernel test robot -- Remove "The speed is not great yet, but it's usable." from the - commit message. Other patches will improve the speed. ---- - .../net/wireless/realtek/rtl8xxxu/Makefile | 2 +- - .../net/wireless/realtek/rtl8xxxu/rtl8xxxu.h | 56 + - .../realtek/rtl8xxxu/rtl8xxxu_8188f.c | 1679 +++++++++++++++++ - .../realtek/rtl8xxxu/rtl8xxxu_8192c.c | 1 + - .../realtek/rtl8xxxu/rtl8xxxu_8192e.c | 1 + - .../realtek/rtl8xxxu/rtl8xxxu_8723a.c | 1 + - .../realtek/rtl8xxxu/rtl8xxxu_8723b.c | 3 +- - .../wireless/realtek/rtl8xxxu/rtl8xxxu_core.c | 137 +- - .../wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h | 19 + - 9 files changed, 1874 insertions(+), 25 deletions(-) - create mode 100644 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c - -diff --git a/drivers/net/wireless/realtek/rtl8xxxu/Makefile b/drivers/net/wireless/realtek/rtl8xxxu/Makefile -index b278f8697..c4ad5325f 100644 ---- a/drivers/net/wireless/realtek/rtl8xxxu/Makefile -+++ b/drivers/net/wireless/realtek/rtl8xxxu/Makefile -@@ -2,4 +2,4 @@ - obj-$(CONFIG_RTL8XXXU) += rtl8xxxu.o - - rtl8xxxu-y := rtl8xxxu_core.o rtl8xxxu_8192e.o rtl8xxxu_8723b.o \ -- rtl8xxxu_8723a.o rtl8xxxu_8192c.o -+ rtl8xxxu_8723a.o rtl8xxxu_8192c.o rtl8xxxu_8188f.o -diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h -index 1ba66b8f7..44f0d7944 100644 ---- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h -+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h -@@ -35,6 +35,7 @@ - #define REALTEK_USB_CMD_IDX 0x00 - - #define TX_TOTAL_PAGE_NUM 0xf8 -+#define TX_TOTAL_PAGE_NUM_8188F 0xf7 - #define TX_TOTAL_PAGE_NUM_8192E 0xf3 - #define TX_TOTAL_PAGE_NUM_8723B 0xf7 - /* (HPQ + LPQ + NPQ + PUBQ) = TX_TOTAL_PAGE_NUM */ -@@ -43,6 +44,11 @@ - #define TX_PAGE_NUM_LO_PQ 0x02 - #define TX_PAGE_NUM_NORM_PQ 0x02 - -+#define TX_PAGE_NUM_PUBQ_8188F 0xe5 -+#define TX_PAGE_NUM_HI_PQ_8188F 0x0c -+#define TX_PAGE_NUM_LO_PQ_8188F 0x02 -+#define TX_PAGE_NUM_NORM_PQ_8188F 0x02 -+ - #define TX_PAGE_NUM_PUBQ_8192E 0xe7 - #define TX_PAGE_NUM_HI_PQ_8192E 0x08 - #define TX_PAGE_NUM_LO_PQ_8192E 0x0c -@@ -859,6 +865,50 @@ struct rtl8192eu_efuse { - u8 res12[0xc3]; - }; - -+struct rtl8188fu_efuse_tx_power { -+ u8 cck_base[6]; -+ u8 ht40_base[5]; -+ /* a: ofdm; b: ht20 */ -+ struct rtl8723au_idx ht20_ofdm_1s_diff; -+}; -+ -+struct rtl8188fu_efuse { -+ __le16 rtl_id; -+ u8 res0[0x0e]; -+ struct rtl8188fu_efuse_tx_power tx_power_index_A; /* 0x10 */ -+ u8 res1[0x9c]; /* 0x1c */ -+ u8 channel_plan; /* 0xb8 */ -+ u8 xtal_k; -+ u8 thermal_meter; -+ u8 iqk_lck; -+ u8 res2[5]; -+ u8 rf_board_option; -+ u8 rf_feature_option; -+ u8 rf_bt_setting; -+ u8 eeprom_version; -+ u8 eeprom_customer_id; -+ u8 res3[2]; -+ u8 kfree_thermal_k_on; -+ u8 rf_antenna_option; /* 0xc9 */ -+ u8 rfe_option; -+ u8 country_code; -+ u8 res4[4]; -+ u8 vid; /* 0xd0 */ -+ u8 res5[1]; -+ u8 pid; /* 0xd2 */ -+ u8 res6[1]; -+ u8 usb_optional_function; -+ u8 res7[2]; -+ u8 mac_addr[ETH_ALEN]; /* 0xd7 */ -+ u8 res8[2]; -+ u8 vendor_name[7]; -+ u8 res9[2]; -+ u8 device_name[7]; /* 0xe8 */ -+ u8 res10[0x41]; -+ u8 unknown[0x0d]; /* 0x130 */ -+ u8 res11[0xc3]; -+}; -+ - struct rtl8xxxu_reg8val { - u16 reg; - u8 val; -@@ -1368,6 +1418,7 @@ struct rtl8xxxu_priv { - struct rtl8723bu_efuse efuse8723bu; - struct rtl8192cu_efuse efuse8192; - struct rtl8192eu_efuse efuse8192eu; -+ struct rtl8188fu_efuse efuse8188fu; - } efuse_wifi; - u32 adda_backup[RTL8XXXU_ADDA_REGS]; - u32 mac_backup[RTL8XXXU_MAC_REGS]; -@@ -1414,6 +1465,7 @@ struct rtl8xxxu_fileops { - void (*init_phy_bb) (struct rtl8xxxu_priv *priv); - int (*init_phy_rf) (struct rtl8xxxu_priv *priv); - void (*phy_init_antenna_selection) (struct rtl8xxxu_priv *priv); -+ void (*phy_lc_calibrate) (struct rtl8xxxu_priv *priv); - void (*phy_iq_calibrate) (struct rtl8xxxu_priv *priv); - void (*config_channel) (struct ieee80211_hw *hw); - int (*parse_rx_desc) (struct rtl8xxxu_priv *priv, struct sk_buff *skb); -@@ -1493,9 +1545,11 @@ int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv, - int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name); - void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv); - void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv); -+int rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data); - void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv); - int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv); - void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start); -+void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv); - int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv); - int rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, - struct h2c_cmd *h2c, int len); -@@ -1539,7 +1593,9 @@ void rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, - u32 rts_rate); - void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv, - u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5); -- -+void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv); -+ -+extern struct rtl8xxxu_fileops rtl8188fu_fops; - extern struct rtl8xxxu_fileops rtl8192cu_fops; - extern struct rtl8xxxu_fileops rtl8192eu_fops; - extern struct rtl8xxxu_fileops rtl8723au_fops; -diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c -index e69de29bb..4ede76610 100644 ---- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c -+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c -@@ -0,0 +1,1679 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * RTL8XXXU mac80211 USB driver - 8188f specific subdriver -+ * -+ * Copyright (c) 2022 Bitterblue Smith -+ * -+ * Portions copied from existing rtl8xxxu code: -+ * Copyright (c) 2014 - 2017 Jes Sorensen -+ * -+ * Portions, notably calibration code: -+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "rtl8xxxu.h" -+#include "rtl8xxxu_regs.h" -+ -+static struct rtl8xxxu_reg8val rtl8188f_mac_init_table[] = { -+ {0x024, 0xDF}, {0x025, 0x07}, {0x02B, 0x1C}, {0x283, 0x20}, -+ {0x421, 0x0F}, {0x428, 0x0A}, {0x429, 0x10}, {0x430, 0x00}, -+ {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, -+ {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08}, {0x43C, 0x04}, -+ {0x43D, 0x05}, {0x43E, 0x07}, {0x43F, 0x08}, {0x440, 0x5D}, -+ {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, -+ {0x446, 0x00}, {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xF0}, -+ {0x44A, 0x0F}, {0x44B, 0x3E}, {0x44C, 0x10}, {0x44D, 0x00}, -+ {0x44E, 0x00}, {0x44F, 0x00}, {0x450, 0x00}, {0x451, 0xF0}, -+ {0x452, 0x0F}, {0x453, 0x00}, {0x456, 0x5E}, {0x460, 0x44}, -+ {0x461, 0x44}, {0x4BC, 0xC0}, {0x4C8, 0xFF}, {0x4C9, 0x08}, -+ {0x4CC, 0xFF}, {0x4CD, 0xFF}, {0x4CE, 0x01}, {0x500, 0x26}, -+ {0x501, 0xA2}, {0x502, 0x2F}, {0x503, 0x00}, {0x504, 0x28}, -+ {0x505, 0xA3}, {0x506, 0x5E}, {0x507, 0x00}, {0x508, 0x2B}, -+ {0x509, 0xA4}, {0x50A, 0x5E}, {0x50B, 0x00}, {0x50C, 0x4F}, -+ {0x50D, 0xA4}, {0x50E, 0x00}, {0x50F, 0x00}, {0x512, 0x1C}, -+ {0x514, 0x0A}, {0x516, 0x0A}, {0x525, 0x4F}, {0x550, 0x10}, -+ {0x551, 0x10}, {0x559, 0x02}, {0x55C, 0x28}, {0x55D, 0xFF}, -+ {0x605, 0x30}, {0x608, 0x0E}, {0x609, 0x2A}, {0x620, 0xFF}, -+ {0x621, 0xFF}, {0x622, 0xFF}, {0x623, 0xFF}, {0x624, 0xFF}, -+ {0x625, 0xFF}, {0x626, 0xFF}, {0x627, 0xFF}, {0x638, 0x28}, -+ {0x63C, 0x0A}, {0x63D, 0x0A}, {0x63E, 0x0E}, {0x63F, 0x0E}, -+ {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xC8}, -+ {0x66E, 0x05}, {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65}, -+ {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, {0x70A, 0x65}, -+ {0x70B, 0x87}, -+ {0xffff, 0xff}, -+}; -+ -+static struct rtl8xxxu_reg32val rtl8188fu_phy_init_table[] = { -+ {0x800, 0x80045700}, {0x804, 0x00000001}, -+ {0x808, 0x0000FC00}, {0x80C, 0x0000000A}, -+ {0x810, 0x10001331}, {0x814, 0x020C3D10}, -+ {0x818, 0x00200385}, {0x81C, 0x00000000}, -+ {0x820, 0x01000100}, {0x824, 0x00390204}, -+ {0x828, 0x00000000}, {0x82C, 0x00000000}, -+ {0x830, 0x00000000}, {0x834, 0x00000000}, -+ {0x838, 0x00000000}, {0x83C, 0x00000000}, -+ {0x840, 0x00010000}, {0x844, 0x00000000}, -+ {0x848, 0x00000000}, {0x84C, 0x00000000}, -+ {0x850, 0x00030000}, {0x854, 0x00000000}, -+ {0x858, 0x569A569A}, {0x85C, 0x569A569A}, -+ {0x860, 0x00000130}, {0x864, 0x00000000}, -+ {0x868, 0x00000000}, {0x86C, 0x27272700}, -+ {0x870, 0x00000000}, {0x874, 0x25004000}, -+ {0x878, 0x00000808}, {0x87C, 0x004F0201}, -+ {0x880, 0xB0000B1E}, {0x884, 0x00000007}, -+ {0x888, 0x00000000}, {0x88C, 0xCCC000C0}, -+ {0x890, 0x00000800}, {0x894, 0xFFFFFFFE}, -+ {0x898, 0x40302010}, {0x89C, 0x00706050}, -+ {0x900, 0x00000000}, {0x904, 0x00000023}, -+ {0x908, 0x00000000}, {0x90C, 0x81121111}, -+ {0x910, 0x00000002}, {0x914, 0x00000201}, -+ {0x948, 0x99000000}, {0x94C, 0x00000010}, -+ {0x950, 0x20003000}, {0x954, 0x4A880000}, -+ {0x958, 0x4BC5D87A}, {0x95C, 0x04EB9B79}, -+ {0x96C, 0x00000003}, {0xA00, 0x00D047C8}, -+ {0xA04, 0x80FF800C}, {0xA08, 0x8C898300}, -+ {0xA0C, 0x2E7F120F}, {0xA10, 0x9500BB78}, -+ {0xA14, 0x1114D028}, {0xA18, 0x00881117}, -+ {0xA1C, 0x89140F00}, {0xA20, 0xD1D80000}, -+ {0xA24, 0x5A7DA0BD}, {0xA28, 0x0000223B}, -+ {0xA2C, 0x00D30000}, {0xA70, 0x101FBF00}, -+ {0xA74, 0x00000007}, {0xA78, 0x00000900}, -+ {0xA7C, 0x225B0606}, {0xA80, 0x218075B1}, -+ {0xA84, 0x00120000}, {0xA88, 0x040C0000}, -+ {0xA8C, 0x12345678}, {0xA90, 0xABCDEF00}, -+ {0xA94, 0x001B1B89}, {0xA98, 0x05100000}, -+ {0xA9C, 0x3F000000}, {0xAA0, 0x00000000}, -+ {0xB2C, 0x00000000}, {0xC00, 0x48071D40}, -+ {0xC04, 0x03A05611}, {0xC08, 0x000000E4}, -+ {0xC0C, 0x6C6C6C6C}, {0xC10, 0x18800000}, -+ {0xC14, 0x40000100}, {0xC18, 0x08800000}, -+ {0xC1C, 0x40000100}, {0xC20, 0x00000000}, -+ {0xC24, 0x00000000}, {0xC28, 0x00000000}, -+ {0xC2C, 0x00000000}, {0xC30, 0x69E9CC4A}, -+ {0xC34, 0x31000040}, {0xC38, 0x21688080}, -+ {0xC3C, 0x00001714}, {0xC40, 0x1F78403F}, -+ {0xC44, 0x00010036}, {0xC48, 0xEC020107}, -+ {0xC4C, 0x007F037F}, {0xC50, 0x69553420}, -+ {0xC54, 0x43BC0094}, {0xC58, 0x00013169}, -+ {0xC5C, 0x00250492}, {0xC60, 0x00000000}, -+ {0xC64, 0x7112848B}, {0xC68, 0x47C07BFF}, -+ {0xC6C, 0x00000036}, {0xC70, 0x2C7F000D}, -+ {0xC74, 0x020600DB}, {0xC78, 0x0000001F}, -+ {0xC7C, 0x00B91612}, {0xC80, 0x390000E4}, -+ {0xC84, 0x11F60000}, -+ {0xC88, 0x40000100}, {0xC8C, 0x20200000}, -+ {0xC90, 0x00091521}, {0xC94, 0x00000000}, -+ {0xC98, 0x00121820}, {0xC9C, 0x00007F7F}, -+ {0xCA0, 0x00000000}, {0xCA4, 0x000300A0}, -+ {0xCA8, 0x00000000}, {0xCAC, 0x00000000}, -+ {0xCB0, 0x00000000}, {0xCB4, 0x00000000}, -+ {0xCB8, 0x00000000}, {0xCBC, 0x28000000}, -+ {0xCC0, 0x00000000}, {0xCC4, 0x00000000}, -+ {0xCC8, 0x00000000}, {0xCCC, 0x00000000}, -+ {0xCD0, 0x00000000}, {0xCD4, 0x00000000}, -+ {0xCD8, 0x64B22427}, {0xCDC, 0x00766932}, -+ {0xCE0, 0x00222222}, {0xCE4, 0x10000000}, -+ {0xCE8, 0x37644302}, {0xCEC, 0x2F97D40C}, -+ {0xD00, 0x04030740}, {0xD04, 0x40020401}, -+ {0xD08, 0x0000907F}, {0xD0C, 0x20010201}, -+ {0xD10, 0xA0633333}, {0xD14, 0x3333BC53}, -+ {0xD18, 0x7A8F5B6F}, {0xD2C, 0xCB979975}, -+ {0xD30, 0x00000000}, {0xD34, 0x80608000}, -+ {0xD38, 0x98000000}, {0xD3C, 0x40127353}, -+ {0xD40, 0x00000000}, {0xD44, 0x00000000}, -+ {0xD48, 0x00000000}, {0xD4C, 0x00000000}, -+ {0xD50, 0x6437140A}, {0xD54, 0x00000000}, -+ {0xD58, 0x00000282}, {0xD5C, 0x30032064}, -+ {0xD60, 0x4653DE68}, {0xD64, 0x04518A3C}, -+ {0xD68, 0x00002101}, {0xD6C, 0x2A201C16}, -+ {0xD70, 0x1812362E}, {0xD74, 0x322C2220}, -+ {0xD78, 0x000E3C24}, {0xE00, 0x2D2D2D2D}, -+ {0xE04, 0x2D2D2D2D}, {0xE08, 0x0390272D}, -+ {0xE10, 0x2D2D2D2D}, {0xE14, 0x2D2D2D2D}, -+ {0xE18, 0x2D2D2D2D}, {0xE1C, 0x2D2D2D2D}, -+ {0xE28, 0x00000000}, {0xE30, 0x1000DC1F}, -+ {0xE34, 0x10008C1F}, {0xE38, 0x02140102}, -+ {0xE3C, 0x681604C2}, {0xE40, 0x01007C00}, -+ {0xE44, 0x01004800}, {0xE48, 0xFB000000}, -+ {0xE4C, 0x000028D1}, {0xE50, 0x1000DC1F}, -+ {0xE54, 0x10008C1F}, {0xE58, 0x02140102}, -+ {0xE5C, 0x28160D05}, {0xE60, 0x00000008}, -+ {0xE60, 0x021400A0}, {0xE64, 0x281600A0}, -+ {0xE6C, 0x01C00010}, {0xE70, 0x01C00010}, -+ {0xE74, 0x02000010}, {0xE78, 0x02000010}, -+ {0xE7C, 0x02000010}, {0xE80, 0x02000010}, -+ {0xE84, 0x01C00010}, {0xE88, 0x02000010}, -+ {0xE8C, 0x01C00010}, {0xED0, 0x01C00010}, -+ {0xED4, 0x01C00010}, {0xED8, 0x01C00010}, -+ {0xEDC, 0x00000010}, {0xEE0, 0x00000010}, -+ {0xEEC, 0x03C00010}, {0xF14, 0x00000003}, -+ {0xF4C, 0x00000000}, {0xF00, 0x00000300}, -+ {0xffff, 0xffffffff}, -+}; -+ -+static struct rtl8xxxu_reg32val rtl8188f_agc_table[] = { -+ {0xC78, 0xFC000001}, {0xC78, 0xFB010001}, -+ {0xC78, 0xFA020001}, {0xC78, 0xF9030001}, -+ {0xC78, 0xF8040001}, {0xC78, 0xF7050001}, -+ {0xC78, 0xF6060001}, {0xC78, 0xF5070001}, -+ {0xC78, 0xF4080001}, {0xC78, 0xF3090001}, -+ {0xC78, 0xF20A0001}, {0xC78, 0xF10B0001}, -+ {0xC78, 0xF00C0001}, {0xC78, 0xEF0D0001}, -+ {0xC78, 0xEE0E0001}, {0xC78, 0xED0F0001}, -+ {0xC78, 0xEC100001}, {0xC78, 0xEB110001}, -+ {0xC78, 0xEA120001}, {0xC78, 0xE9130001}, -+ {0xC78, 0xE8140001}, {0xC78, 0xE7150001}, -+ {0xC78, 0xE6160001}, {0xC78, 0xE5170001}, -+ {0xC78, 0xE4180001}, {0xC78, 0xE3190001}, -+ {0xC78, 0xE21A0001}, {0xC78, 0xE11B0001}, -+ {0xC78, 0xE01C0001}, {0xC78, 0xC21D0001}, -+ {0xC78, 0xC11E0001}, {0xC78, 0xC01F0001}, -+ {0xC78, 0xA5200001}, {0xC78, 0xA4210001}, -+ {0xC78, 0xA3220001}, {0xC78, 0xA2230001}, -+ {0xC78, 0xA1240001}, {0xC78, 0xA0250001}, -+ {0xC78, 0x65260001}, {0xC78, 0x64270001}, -+ {0xC78, 0x63280001}, {0xC78, 0x62290001}, -+ {0xC78, 0x612A0001}, {0xC78, 0x442B0001}, -+ {0xC78, 0x432C0001}, {0xC78, 0x422D0001}, -+ {0xC78, 0x412E0001}, {0xC78, 0x402F0001}, -+ {0xC78, 0x21300001}, {0xC78, 0x20310001}, -+ {0xC78, 0x05320001}, {0xC78, 0x04330001}, -+ {0xC78, 0x03340001}, {0xC78, 0x02350001}, -+ {0xC78, 0x01360001}, {0xC78, 0x00370001}, -+ {0xC78, 0x00380001}, {0xC78, 0x00390001}, -+ {0xC78, 0x003A0001}, {0xC78, 0x003B0001}, -+ {0xC78, 0x003C0001}, {0xC78, 0x003D0001}, -+ {0xC78, 0x003E0001}, {0xC78, 0x003F0001}, -+ {0xC50, 0x69553422}, {0xC50, 0x69553420}, -+ {0xffff, 0xffffffff} -+}; -+ -+static struct rtl8xxxu_rfregval rtl8188fu_radioa_init_table[] = { -+ {0x00, 0x00030000}, {0x08, 0x00008400}, -+ {0x18, 0x00000407}, {0x19, 0x00000012}, -+ {0x1B, 0x00001C6C}, -+ {0x1E, 0x00080009}, {0x1F, 0x00000880}, -+ {0x2F, 0x0001A060}, {0x3F, 0x00028000}, -+ {0x42, 0x000060C0}, {0x57, 0x000D0000}, -+ {0x58, 0x000C0160}, {0x67, 0x00001552}, -+ {0x83, 0x00000000}, {0xB0, 0x000FF9F0}, -+ {0xB1, 0x00022218}, {0xB2, 0x00034C00}, -+ {0xB4, 0x0004484B}, {0xB5, 0x0000112A}, -+ {0xB6, 0x0000053E}, {0xB7, 0x00010408}, -+ {0xB8, 0x00010200}, {0xB9, 0x00080001}, -+ {0xBA, 0x00040001}, {0xBB, 0x00000400}, -+ {0xBF, 0x000C0000}, {0xC2, 0x00002400}, -+ {0xC3, 0x00000009}, {0xC4, 0x00040C91}, -+ {0xC5, 0x00099999}, {0xC6, 0x000000A3}, -+ {0xC7, 0x0008F820}, {0xC8, 0x00076C06}, -+ {0xC9, 0x00000000}, {0xCA, 0x00080000}, -+ {0xDF, 0x00000180}, {0xEF, 0x000001A0}, -+ {0x51, 0x000E8333}, {0x52, 0x000FAC2C}, -+ {0x53, 0x00000103}, {0x56, 0x000517F0}, -+ {0x35, 0x00000099}, {0x35, 0x00000199}, -+ {0x35, 0x00000299}, {0x36, 0x00000064}, -+ {0x36, 0x00008064}, {0x36, 0x00010064}, -+ {0x36, 0x00018064}, {0x18, 0x00000C07}, -+ {0x5A, 0x00048000}, {0x19, 0x000739D0}, -+ {0x34, 0x0000ADD6}, {0x34, 0x00009DD3}, -+ {0x34, 0x00008CF4}, {0x34, 0x00007CF1}, -+ {0x34, 0x00006CEE}, {0x34, 0x00005CEB}, -+ {0x34, 0x00004CCE}, {0x34, 0x00003CCB}, -+ {0x34, 0x00002CC8}, {0x34, 0x00001C4B}, -+ {0x34, 0x00000C48}, -+ {0x00, 0x00030159}, {0x84, 0x00048000}, -+ {0x86, 0x0000002A}, {0x87, 0x00000025}, -+ {0x8E, 0x00065540}, {0x8F, 0x00088000}, -+ {0xEF, 0x000020A0}, {0x3B, 0x000F0F00}, -+ {0x3B, 0x000E0B00}, {0x3B, 0x000D0900}, -+ {0x3B, 0x000C0700}, {0x3B, 0x000B0600}, -+ {0x3B, 0x000A0400}, {0x3B, 0x00090200}, -+ {0x3B, 0x00080000}, {0x3B, 0x0007BF00}, -+ {0x3B, 0x00060B00}, {0x3B, 0x0005C900}, -+ {0x3B, 0x00040700}, {0x3B, 0x00030600}, -+ {0x3B, 0x0002D500}, {0x3B, 0x00010200}, -+ {0x3B, 0x0000E000}, {0xEF, 0x000000A0}, -+ {0xEF, 0x00000010}, {0x3B, 0x0000C0A8}, -+ {0x3B, 0x00010400}, {0xEF, 0x00000000}, -+ {0xEF, 0x00080000}, {0x30, 0x00010000}, -+ {0x31, 0x0000000F}, {0x32, 0x00007EFE}, -+ {0xEF, 0x00000000}, {0x00, 0x00010159}, -+ {0x18, 0x0000FC07}, {0xFE, 0x00000000}, -+ {0xFE, 0x00000000}, {0x1F, 0x00080003}, -+ {0xFE, 0x00000000}, {0xFE, 0x00000000}, -+ {0x1E, 0x00000001}, {0x1F, 0x00080000}, -+ {0x00, 0x00033D95}, -+ {0xff, 0xffffffff} -+}; -+ -+static struct rtl8xxxu_rfregval rtl8188fu_cut_b_radioa_init_table[] = { -+ {0x00, 0x00030000}, {0x08, 0x00008400}, -+ {0x18, 0x00000407}, {0x19, 0x00000012}, -+ {0x1B, 0x00001C6C}, -+ {0x1E, 0x00080009}, {0x1F, 0x00000880}, -+ {0x2F, 0x0001A060}, {0x3F, 0x00028000}, -+ {0x42, 0x000060C0}, {0x57, 0x000D0000}, -+ {0x58, 0x000C0160}, {0x67, 0x00001552}, -+ {0x83, 0x00000000}, {0xB0, 0x000FF9F0}, -+ {0xB1, 0x00022218}, {0xB2, 0x00034C00}, -+ {0xB4, 0x0004484B}, {0xB5, 0x0000112A}, -+ {0xB6, 0x0000053E}, {0xB7, 0x00010408}, -+ {0xB8, 0x00010200}, {0xB9, 0x00080001}, -+ {0xBA, 0x00040001}, {0xBB, 0x00000400}, -+ {0xBF, 0x000C0000}, {0xC2, 0x00002400}, -+ {0xC3, 0x00000009}, {0xC4, 0x00040C91}, -+ {0xC5, 0x00099999}, {0xC6, 0x000000A3}, -+ {0xC7, 0x0008F820}, {0xC8, 0x00076C06}, -+ {0xC9, 0x00000000}, {0xCA, 0x00080000}, -+ {0xDF, 0x00000180}, {0xEF, 0x000001A0}, -+ {0x51, 0x000E8231}, {0x52, 0x000FAC2C}, -+ {0x53, 0x00000141}, {0x56, 0x000517F0}, -+ {0x35, 0x00000090}, {0x35, 0x00000190}, -+ {0x35, 0x00000290}, {0x36, 0x00001064}, -+ {0x36, 0x00009064}, {0x36, 0x00011064}, -+ {0x36, 0x00019064}, {0x18, 0x00000C07}, -+ {0x5A, 0x00048000}, {0x19, 0x000739D0}, -+ {0x34, 0x0000ADD2}, {0x34, 0x00009DD0}, -+ {0x34, 0x00008CF3}, {0x34, 0x00007CF0}, -+ {0x34, 0x00006CED}, {0x34, 0x00005CD2}, -+ {0x34, 0x00004CCF}, {0x34, 0x00003CCC}, -+ {0x34, 0x00002CC9}, {0x34, 0x00001C4C}, -+ {0x34, 0x00000C49}, -+ {0x00, 0x00030159}, {0x84, 0x00048000}, -+ {0x86, 0x0000002A}, {0x87, 0x00000025}, -+ {0x8E, 0x00065540}, {0x8F, 0x00088000}, -+ {0xEF, 0x000020A0}, {0x3B, 0x000F0F00}, -+ {0x3B, 0x000E0B00}, {0x3B, 0x000D0900}, -+ {0x3B, 0x000C0700}, {0x3B, 0x000B0600}, -+ {0x3B, 0x000A0400}, {0x3B, 0x00090200}, -+ {0x3B, 0x00080000}, {0x3B, 0x0007BF00}, -+ {0x3B, 0x00060B00}, {0x3B, 0x0005C900}, -+ {0x3B, 0x00040700}, {0x3B, 0x00030600}, -+ {0x3B, 0x0002D500}, {0x3B, 0x00010200}, -+ {0x3B, 0x0000E000}, {0xEF, 0x000000A0}, -+ {0xEF, 0x00000010}, {0x3B, 0x0000C0A8}, -+ {0x3B, 0x00010400}, {0xEF, 0x00000000}, -+ {0xEF, 0x00080000}, {0x30, 0x00010000}, -+ {0x31, 0x0000000F}, {0x32, 0x00007EFE}, -+ {0xEF, 0x00000000}, {0x00, 0x00010159}, -+ {0x18, 0x0000FC07}, {0xFE, 0x00000000}, -+ {0xFE, 0x00000000}, {0x1F, 0x00080003}, -+ {0xFE, 0x00000000}, {0xFE, 0x00000000}, -+ {0x1E, 0x00000001}, {0x1F, 0x00080000}, -+ {0x00, 0x00033D95}, -+ {0xff, 0xffffffff} -+}; -+ -+static void rtl8xxxu_8188f_channel_to_group(int channel, int *group, int *cck_group) -+{ -+ if (channel < 3) -+ *group = 0; -+ else if (channel < 6) -+ *group = 1; -+ else if (channel < 9) -+ *group = 2; -+ else if (channel < 12) -+ *group = 3; -+ else -+ *group = 4; -+ -+ if (channel == 14) -+ *cck_group = 5; -+ else -+ *cck_group = *group; -+} -+ -+static void -+rtl8188f_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) -+{ -+ u32 val32, ofdm, mcs; -+ u8 cck, ofdmbase, mcsbase; -+ int group, cck_group; -+ -+ rtl8xxxu_8188f_channel_to_group(channel, &group, &cck_group); -+ -+ cck = priv->cck_tx_power_index_A[cck_group]; -+ -+ val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); -+ val32 &= 0xffff00ff; -+ val32 |= (cck << 8); -+ rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); -+ -+ val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); -+ val32 &= 0xff; -+ val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); -+ rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); -+ -+ ofdmbase = priv->ht40_1s_tx_power_index_A[group]; -+ ofdmbase += priv->ofdm_tx_power_diff[0].a; -+ ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24; -+ -+ rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); -+ rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); -+ -+ mcsbase = priv->ht40_1s_tx_power_index_A[group]; -+ if (ht40) -+ /* This diff is always 0 - not used in 8188FU. */ -+ mcsbase += priv->ht40_tx_power_diff[0].a; -+ else -+ mcsbase += priv->ht20_tx_power_diff[0].a; -+ mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; -+ -+ rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); -+ rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); -+ rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs); -+ rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs); -+} -+ -+/* A workaround to eliminate the 2400MHz, 2440MHz, 2480MHz spur of 8188F. */ -+static void rtl8188f_spur_calibration(struct rtl8xxxu_priv *priv, u8 channel) -+{ -+ static const u32 frequencies[14 + 1] = { -+ [5] = 0xFCCD, -+ [6] = 0xFC4D, -+ [7] = 0xFFCD, -+ [8] = 0xFF4D, -+ [11] = 0xFDCD, -+ [13] = 0xFCCD, -+ [14] = 0xFF9A -+ }; -+ -+ static const u32 reg_d40[14 + 1] = { -+ [5] = 0x06000000, -+ [6] = 0x00000600, -+ [13] = 0x06000000 -+ }; -+ -+ static const u32 reg_d44[14 + 1] = { -+ [11] = 0x04000000 -+ }; -+ -+ static const u32 reg_d4c[14 + 1] = { -+ [7] = 0x06000000, -+ [8] = 0x00000380, -+ [14] = 0x00180000 -+ }; -+ -+ const u8 threshold = 0x16; -+ bool do_notch, hw_ctrl, sw_ctrl, hw_ctrl_s1, sw_ctrl_s1; -+ u32 val32, initial_gain, reg948; -+ -+ val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_D_SYNC_PATH); -+ val32 |= GENMASK(28, 24); -+ rtl8xxxu_write32(priv, REG_OFDM0_RX_D_SYNC_PATH, val32); -+ -+ /* enable notch filter */ -+ val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_D_SYNC_PATH); -+ val32 |= BIT(9); -+ rtl8xxxu_write32(priv, REG_OFDM0_RX_D_SYNC_PATH, val32); -+ -+ if (channel <= 14 && frequencies[channel] > 0) { -+ reg948 = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); -+ hw_ctrl = reg948 & BIT(6); -+ sw_ctrl = !hw_ctrl; -+ -+ if (hw_ctrl) { -+ val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); -+ val32 &= GENMASK(5, 3); -+ hw_ctrl_s1 = val32 == BIT(3); -+ } else if (sw_ctrl) { -+ sw_ctrl_s1 = !(reg948 & BIT(9)); -+ } -+ -+ if (hw_ctrl_s1 || sw_ctrl_s1) { -+ initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); -+ -+ /* Disable CCK block */ -+ val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); -+ val32 &= ~FPGA_RF_MODE_CCK; -+ rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); -+ -+ val32 = initial_gain & ~OFDM0_X_AGC_CORE1_IGI_MASK; -+ val32 |= 0x30; -+ rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); -+ -+ /* disable 3-wire */ -+ rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); -+ -+ /* Setup PSD */ -+ rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, frequencies[channel]); -+ -+ /* Start PSD */ -+ rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, 0x400000 | frequencies[channel]); -+ -+ msleep(30); -+ -+ do_notch = rtl8xxxu_read32(priv, REG_FPGA0_PSD_REPORT) >= threshold; -+ -+ /* turn off PSD */ -+ rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, frequencies[channel]); -+ -+ /* enable 3-wire */ -+ rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccc000c0); -+ -+ /* Enable CCK block */ -+ val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); -+ val32 |= FPGA_RF_MODE_CCK; -+ rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); -+ -+ rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, initial_gain); -+ -+ if (do_notch) { -+ rtl8xxxu_write32(priv, REG_OFDM1_CSI_FIX_MASK1, reg_d40[channel]); -+ rtl8xxxu_write32(priv, REG_OFDM1_CSI_FIX_MASK2, reg_d44[channel]); -+ rtl8xxxu_write32(priv, 0xd48, 0x0); -+ rtl8xxxu_write32(priv, 0xd4c, reg_d4c[channel]); -+ -+ /* enable CSI mask */ -+ val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); -+ val32 |= BIT(28); -+ rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); -+ -+ return; -+ } -+ } -+ } -+ -+ /* disable CSI mask function */ -+ val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); -+ val32 &= ~BIT(28); -+ rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); -+} -+ -+static void rtl8188fu_config_channel(struct ieee80211_hw *hw) -+{ -+ struct rtl8xxxu_priv *priv = hw->priv; -+ u32 val32; -+ u8 channel, subchannel; -+ bool sec_ch_above; -+ -+ channel = (u8)hw->conf.chandef.chan->hw_value; -+ -+ /* Set channel */ -+ val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); -+ val32 &= ~MODE_AG_CHANNEL_MASK; -+ val32 |= channel; -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); -+ -+ /* Spur calibration */ -+ rtl8188f_spur_calibration(priv, channel); -+ -+ /* Set bandwidth mode */ -+ val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); -+ val32 &= ~FPGA_RF_MODE; -+ val32 |= hw->conf.chandef.width == NL80211_CHAN_WIDTH_40; -+ rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); -+ -+ val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); -+ val32 &= ~FPGA_RF_MODE; -+ val32 |= hw->conf.chandef.width == NL80211_CHAN_WIDTH_40; -+ rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); -+ -+ /* RXADC CLK */ -+ val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); -+ val32 |= GENMASK(10, 8); -+ rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); -+ -+ /* TXDAC CLK */ -+ val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); -+ val32 |= BIT(14) | BIT(12); -+ val32 &= ~BIT(13); -+ rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); -+ -+ /* small BW */ -+ val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); -+ val32 &= ~GENMASK(31, 30); -+ rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); -+ -+ /* adc buffer clk */ -+ val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); -+ val32 &= ~BIT(29); -+ val32 |= BIT(28); -+ rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); -+ -+ /* adc buffer clk */ -+ val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_AFE); -+ val32 &= ~BIT(29); -+ val32 |= BIT(28); -+ rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_AFE, val32); -+ -+ val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); -+ val32 &= ~BIT(19); -+ rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); -+ -+ val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); -+ val32 &= ~GENMASK(23, 20); -+ val32 |= BIT(21); -+ if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 || -+ hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT) -+ val32 |= BIT(20); -+ else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) -+ val32 |= BIT(22); -+ rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); -+ -+ if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) { -+ if (hw->conf.chandef.center_freq1 > -+ hw->conf.chandef.chan->center_freq) { -+ sec_ch_above = 1; -+ channel += 2; -+ } else { -+ sec_ch_above = 0; -+ channel -= 2; -+ } -+ -+ /* Set Control channel to upper or lower. */ -+ val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); -+ val32 &= ~CCK0_SIDEBAND; -+ if (!sec_ch_above) -+ val32 |= CCK0_SIDEBAND; -+ rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); -+ -+ val32 = rtl8xxxu_read32(priv, REG_DATA_SUBCHANNEL); -+ val32 &= ~GENMASK(3, 0); -+ if (sec_ch_above) -+ subchannel = 2; -+ else -+ subchannel = 1; -+ val32 |= subchannel; -+ rtl8xxxu_write32(priv, REG_DATA_SUBCHANNEL, val32); -+ -+ val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); -+ val32 &= ~RSR_RSC_BANDWIDTH_40M; -+ rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); -+ } -+ -+ /* RF TRX_BW */ -+ val32 = channel; -+ if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 || -+ hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT) -+ val32 |= MODE_AG_BW_20MHZ_8723B; -+ else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) -+ val32 |= MODE_AG_BW_40MHZ_8723B; -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); -+ -+ /* FILTER BW&RC Corner (ACPR) */ -+ if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 || -+ hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT) -+ val32 = 0x00065; -+ else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) -+ val32 = 0x00025; -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RXG_MIX_SWBW, val32); -+ -+ if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 || -+ hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT) -+ val32 = 0x0; -+ else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) -+ val32 = 0x01000; -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RX_BB2, val32); -+ -+ /* RC Corner */ -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00140); -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RX_G2, 0x01c6c); -+} -+ -+static void rtl8188fu_init_aggregation(struct rtl8xxxu_priv *priv) -+{ -+ u8 agg_ctrl, rxdma_mode, usb_tx_agg_desc_num = 6; -+ u32 agg_rx, val32; -+ -+ /* TX aggregation */ -+ val32 = rtl8xxxu_read32(priv, REG_DWBCN0_CTRL_8188F); -+ val32 &= ~(0xf << 4); -+ val32 |= usb_tx_agg_desc_num << 4; -+ rtl8xxxu_write32(priv, REG_DWBCN0_CTRL_8188F, val32); -+ rtl8xxxu_write8(priv, REG_DWBCN1_CTRL_8723B, usb_tx_agg_desc_num << 1); -+ -+ /* RX aggregation */ -+ agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); -+ agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; -+ -+ agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH); -+ agg_rx &= ~RXDMA_USB_AGG_ENABLE; -+ agg_rx &= ~0xFF0F; /* reset agg size and timeout */ -+ -+ rxdma_mode = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B); -+ rxdma_mode &= ~BIT(1); -+ -+ rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); -+ rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx); -+ rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, rxdma_mode); -+} -+ -+static void rtl8188fu_init_statistics(struct rtl8xxxu_priv *priv) -+{ -+ u32 val32; -+ -+ /* Time duration for NHM unit: 4us, 0xc350=200ms */ -+ rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0xc350); -+ rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff); -+ rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff50); -+ rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff); -+ -+ /* TH8 */ -+ val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); -+ val32 |= 0xff; -+ rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); -+ -+ /* Enable CCK */ -+ val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B); -+ val32 &= ~(BIT(8) | BIT(9) | BIT(10)); -+ val32 |= BIT(8); -+ rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32); -+ -+ /* Max power amongst all RX antennas */ -+ val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC); -+ val32 |= BIT(7); -+ rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32); -+} -+ -+static int rtl8188fu_parse_efuse(struct rtl8xxxu_priv *priv) -+{ -+ struct rtl8188fu_efuse *efuse = &priv->efuse_wifi.efuse8188fu; -+ int i; -+ -+ if (efuse->rtl_id != cpu_to_le16(0x8129)) -+ return -EINVAL; -+ -+ ether_addr_copy(priv->mac_addr, efuse->mac_addr); -+ -+ memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, -+ sizeof(efuse->tx_power_index_A.cck_base)); -+ -+ memcpy(priv->ht40_1s_tx_power_index_A, -+ efuse->tx_power_index_A.ht40_base, -+ sizeof(efuse->tx_power_index_A.ht40_base)); -+ -+ priv->ofdm_tx_power_diff[0].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.a; -+ priv->ht20_tx_power_diff[0].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.b; -+ -+ priv->xtalk = efuse->xtal_k & 0x3f; -+ -+ dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name); -+ dev_info(&priv->udev->dev, "Product: %.7s\n", efuse->device_name); -+ -+ if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) { -+ unsigned char *raw = priv->efuse_wifi.raw; -+ -+ dev_info(&priv->udev->dev, -+ "%s: dumping efuse (0x%02zx bytes):\n", -+ __func__, sizeof(struct rtl8188fu_efuse)); -+ for (i = 0; i < sizeof(struct rtl8188fu_efuse); i += 8) -+ dev_info(&priv->udev->dev, "%02x: %8ph\n", i, &raw[i]); -+ } -+ -+ return 0; -+} -+ -+static int rtl8188fu_load_firmware(struct rtl8xxxu_priv *priv) -+{ -+ char *fw_name; -+ int ret; -+ -+ fw_name = "rtlwifi/rtl8188fufw.bin"; -+ -+ ret = rtl8xxxu_load_firmware(priv, fw_name); -+ -+ return ret; -+} -+ -+static void rtl8188fu_init_phy_bb(struct rtl8xxxu_priv *priv) -+{ -+ u8 val8; -+ u16 val16; -+ u32 val32; -+ -+ /* Enable BB and RF */ -+ val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); -+ val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF; -+ rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); -+ -+ /* -+ * Per vendor driver, run power sequence before init of RF -+ */ -+ val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; -+ rtl8xxxu_write8(priv, REG_RF_CTRL, val8); -+ -+ usleep_range(10, 20); -+ -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780); -+ -+ val8 = SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_USBA | SYS_FUNC_USBD; -+ rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); -+ -+ rtl8xxxu_init_phy_regs(priv, rtl8188fu_phy_init_table); -+ rtl8xxxu_init_phy_regs(priv, rtl8188f_agc_table); -+ -+ val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); -+ val8 = priv->xtalk; -+ val32 &= ~0x007FF800; -+ val32 |= ((val8 | (val8 << 6)) << 11); -+ rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); -+} -+ -+static int rtl8188fu_init_phy_rf(struct rtl8xxxu_priv *priv) -+{ -+ int ret; -+ -+ if (priv->chip_cut == 1) -+ ret = rtl8xxxu_init_phy_rf(priv, rtl8188fu_cut_b_radioa_init_table, RF_A); -+ else -+ ret = rtl8xxxu_init_phy_rf(priv, rtl8188fu_radioa_init_table, RF_A); -+ -+ return ret; -+} -+ -+static void rtl8188f_phy_lc_calibrate(struct rtl8xxxu_priv *priv) -+{ -+ u32 val32; -+ u32 rf_amode, lstf; -+ int i; -+ -+ /* Check continuous TX and Packet TX */ -+ lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); -+ -+ if (lstf & OFDM_LSTF_MASK) { -+ /* Disable all continuous TX */ -+ val32 = lstf & ~OFDM_LSTF_MASK; -+ rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); -+ } else { -+ /* Deal with Packet TX case */ -+ /* block all queues */ -+ rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); -+ } -+ -+ /* Read original RF mode Path A */ -+ rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); -+ -+ /* Start LC calibration */ -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, rf_amode | 0x08000); -+ -+ for (i = 0; i < 100; i++) { -+ if ((rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG) & 0x08000) == 0) -+ break; -+ msleep(10); -+ } -+ -+ if (i == 100) -+ dev_warn(&priv->udev->dev, "LC calibration timed out.\n"); -+ -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, rf_amode); -+ -+ /* Restore original parameters */ -+ if (lstf & OFDM_LSTF_MASK) -+ rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf); -+ else /* Deal with Packet TX case */ -+ rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); -+} -+ -+static int rtl8188fu_iqk_path_a(struct rtl8xxxu_priv *priv, u32 *lok_result) -+{ -+ u32 reg_eac, reg_e94, reg_e9c, val32; -+ int result = 0; -+ -+ /* -+ * Leave IQK mode -+ */ -+ val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); -+ val32 &= 0x000000ff; -+ rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); -+ -+ /* -+ * Enable path A PA in TX IQK mode -+ */ -+ val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); -+ val32 |= 0x80000; -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000); -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0x07ff7); -+ -+ /* PA,PAD gain adjust */ -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x980); -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x5102a); -+ -+ /* enter IQK mode */ -+ val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); -+ val32 &= 0x000000ff; -+ val32 |= 0x80800000; -+ rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); -+ -+ /* path-A IQK setting */ -+ rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); -+ rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); -+ -+ rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ff); -+ rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000); -+ -+ /* LO calibration setting */ -+ rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); -+ -+ /* One shot, path A LOK & IQK */ -+ rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); -+ rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); -+ -+ mdelay(25); -+ -+ /* -+ * Leave IQK mode -+ */ -+ val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); -+ val32 &= 0x000000ff; -+ rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); -+ -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180); -+ -+ /* save LOK result */ -+ *lok_result = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_TXM_IDAC); -+ -+ /* Check failed */ -+ reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); -+ reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); -+ reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); -+ -+ if (!(reg_eac & BIT(28)) && -+ ((reg_e94 & 0x03ff0000) != 0x01420000) && -+ ((reg_e9c & 0x03ff0000) != 0x00420000)) -+ result |= 0x01; -+ -+ return result; -+} -+ -+static int rtl8188fu_rx_iqk_path_a(struct rtl8xxxu_priv *priv, u32 lok_result) -+{ -+ u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32; -+ int result = 0; -+ -+ /* -+ * Leave IQK mode -+ */ -+ val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); -+ val32 &= 0x000000ff; -+ rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); -+ -+ /* -+ * Enable path A PA in TX IQK mode -+ */ -+ val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); -+ val32 |= 0x80000; -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173); -+ -+ /* PA,PAD gain adjust */ -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x980); -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x5102a); -+ -+ /* -+ * Enter IQK mode -+ */ -+ val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); -+ val32 &= 0x000000ff; -+ val32 |= 0x80800000; -+ rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); -+ -+ /* -+ * Tx IQK setting -+ */ -+ rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); -+ rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); -+ -+ /* path-A IQK setting */ -+ rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1c); -+ rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x30008c1c); -+ -+ rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160fff); -+ rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000); -+ -+ /* LO calibration setting */ -+ rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); -+ -+ /* One shot, path A LOK & IQK */ -+ rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); -+ rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); -+ -+ mdelay(25); -+ -+ /* -+ * Leave IQK mode -+ */ -+ val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); -+ val32 &= 0x000000ff; -+ rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); -+ -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180); -+ -+ /* Check failed */ -+ reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); -+ reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); -+ reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); -+ -+ if (!(reg_eac & BIT(28)) && -+ ((reg_e94 & 0x03ff0000) != 0x01420000) && -+ ((reg_e9c & 0x03ff0000) != 0x00420000)) -+ result |= 0x01; -+ else /* If TX not OK, ignore RX */ -+ goto out; -+ -+ val32 = 0x80007c00 | (reg_e94 & 0x3ff0000) | -+ ((reg_e9c & 0x3ff0000) >> 16); -+ rtl8xxxu_write32(priv, REG_TX_IQK, val32); -+ -+ /* -+ * Modify RX IQK mode table -+ */ -+ val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); -+ val32 &= 0x000000ff; -+ rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); -+ -+ val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); -+ val32 |= 0x80000; -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2); -+ -+ /* -+ * PA, PAD setting -+ */ -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x980); -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000); -+ -+ /* -+ * Enter IQK mode -+ */ -+ val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); -+ val32 &= 0x000000ff; -+ val32 |= 0x80800000; -+ rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); -+ -+ /* -+ * RX IQK setting -+ */ -+ rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); -+ -+ /* path-A IQK setting */ -+ rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x30008c1c); -+ rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1c); -+ -+ rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160000); -+ rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x281613ff); -+ -+ /* LO calibration setting */ -+ rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); -+ -+ /* One shot, path A LOK & IQK */ -+ rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); -+ rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); -+ -+ mdelay(25); -+ -+ /* -+ * Leave IQK mode -+ */ -+ val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); -+ val32 &= 0x000000ff; -+ rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); -+ -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180); -+ -+ /* reload LOK value */ -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXM_IDAC, lok_result); -+ -+ /* Check failed */ -+ reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); -+ reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); -+ -+ if (!(reg_eac & BIT(27)) && -+ ((reg_ea4 & 0x03ff0000) != 0x01320000) && -+ ((reg_eac & 0x03ff0000) != 0x00360000)) -+ result |= 0x02; -+ -+out: -+ return result; -+} -+ -+static void rtl8188fu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, -+ int result[][8], int t) -+{ -+ struct device *dev = &priv->udev->dev; -+ u32 i, val32, rx_initial_gain, lok_result; -+ u32 path_sel_bb, path_sel_rf; -+ int path_a_ok; -+ int retry = 2; -+ static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { -+ REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, -+ REG_RX_WAIT_CCA, REG_TX_CCK_RFON, -+ REG_TX_CCK_BBON, REG_TX_OFDM_RFON, -+ REG_TX_OFDM_BBON, REG_TX_TO_RX, -+ REG_TX_TO_TX, REG_RX_CCK, -+ REG_RX_OFDM, REG_RX_WAIT_RIFS, -+ REG_RX_TO_RX, REG_STANDBY, -+ REG_SLEEP, REG_PMPD_ANAEN -+ }; -+ static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { -+ REG_TXPAUSE, REG_BEACON_CTRL, -+ REG_BEACON_CTRL_1, REG_GPIO_MUXCFG -+ }; -+ static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { -+ REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, -+ REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, -+ REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, -+ REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE -+ }; -+ -+ /* -+ * Note: IQ calibration must be performed after loading -+ * PHY_REG.txt , and radio_a, radio_b.txt -+ */ -+ -+ rx_initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); -+ -+ if (t == 0) { -+ /* Save ADDA parameters, turn Path A ADDA on */ -+ rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, -+ RTL8XXXU_ADDA_REGS); -+ rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); -+ rtl8xxxu_save_regs(priv, iqk_bb_regs, -+ priv->bb_backup, RTL8XXXU_BB_REGS); -+ } -+ -+ rtl8xxxu_path_adda_on(priv, adda_regs, true); -+ -+ if (t == 0) { -+ val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); -+ priv->pi_enabled = val32 & FPGA0_HSSI_PARM1_PI; -+ } -+ -+ /* save RF path */ -+ path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); -+ path_sel_rf = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_S0S1); -+ -+ /* BB setting */ -+ rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); -+ rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); -+ rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x25204000); -+ -+ /* MAC settings */ -+ val32 = rtl8xxxu_read32(priv, REG_TX_PTCL_CTRL); -+ val32 |= 0x00ff0000; -+ rtl8xxxu_write32(priv, REG_TX_PTCL_CTRL, val32); -+ -+ /* IQ calibration setting */ -+ val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); -+ val32 &= 0xff; -+ val32 |= 0x80800000; -+ rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); -+ rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); -+ rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); -+ -+ for (i = 0; i < retry; i++) { -+ path_a_ok = rtl8188fu_iqk_path_a(priv, &lok_result); -+ if (path_a_ok == 0x01) { -+ val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); -+ val32 &= 0xff; -+ rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); -+ -+ val32 = rtl8xxxu_read32(priv, -+ REG_TX_POWER_BEFORE_IQK_A); -+ result[t][0] = (val32 >> 16) & 0x3ff; -+ -+ val32 = rtl8xxxu_read32(priv, -+ REG_TX_POWER_AFTER_IQK_A); -+ result[t][1] = (val32 >> 16) & 0x3ff; -+ break; -+ } -+ } -+ -+ for (i = 0; i < retry; i++) { -+ path_a_ok = rtl8188fu_rx_iqk_path_a(priv, lok_result); -+ if (path_a_ok == 0x03) { -+ val32 = rtl8xxxu_read32(priv, -+ REG_RX_POWER_BEFORE_IQK_A_2); -+ result[t][2] = (val32 >> 16) & 0x3ff; -+ -+ val32 = rtl8xxxu_read32(priv, -+ REG_RX_POWER_AFTER_IQK_A_2); -+ result[t][3] = (val32 >> 16) & 0x3ff; -+ break; -+ } -+ } -+ -+ if (!path_a_ok) -+ dev_dbg(dev, "%s: Path A IQK failed!\n", __func__); -+ -+ /* Back to BB mode, load original value */ -+ val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); -+ val32 &= 0xff; -+ rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); -+ -+ if (t == 0) -+ return; -+ -+ if (!priv->pi_enabled) { -+ /* -+ * Switch back BB to SI mode after finishing -+ * IQ Calibration -+ */ -+ val32 = 0x01000000; -+ rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32); -+ rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32); -+ } -+ -+ /* Reload ADDA power saving parameters */ -+ rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, -+ RTL8XXXU_ADDA_REGS); -+ -+ /* Reload MAC parameters */ -+ rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); -+ -+ /* Reload BB parameters */ -+ rtl8xxxu_restore_regs(priv, iqk_bb_regs, -+ priv->bb_backup, RTL8XXXU_BB_REGS); -+ -+ /* Reload RF path */ -+ rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb); -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, path_sel_rf); -+ -+ /* Restore RX initial gain */ -+ val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); -+ val32 &= 0xffffff00; -+ val32 |= 0x50; -+ rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); -+ val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); -+ val32 &= 0xffffff00; -+ val32 |= rx_initial_gain & 0xff; -+ rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); -+ -+ /* Load 0xe30 IQC default value */ -+ rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); -+ rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); -+} -+ -+static void rtl8188fu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) -+{ -+ struct device *dev = &priv->udev->dev; -+ int result[4][8]; /* last is final result */ -+ int i, candidate; -+ bool path_a_ok; -+ u32 reg_e94, reg_e9c, reg_ea4, reg_eac; -+ u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; -+ s32 reg_tmp = 0; -+ bool simu; -+ u32 path_sel_bb, path_sel_rf; -+ -+ /* Save RF path */ -+ path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); -+ path_sel_rf = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_S0S1); -+ -+ memset(result, 0, sizeof(result)); -+ candidate = -1; -+ -+ path_a_ok = false; -+ -+ for (i = 0; i < 3; i++) { -+ rtl8188fu_phy_iqcalibrate(priv, result, i); -+ -+ if (i == 1) { -+ simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 1); -+ if (simu) { -+ candidate = 0; -+ break; -+ } -+ } -+ -+ if (i == 2) { -+ simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 2); -+ if (simu) { -+ candidate = 0; -+ break; -+ } -+ -+ simu = rtl8xxxu_gen2_simularity_compare(priv, result, 1, 2); -+ if (simu) { -+ candidate = 1; -+ } else { -+ for (i = 0; i < 8; i++) -+ reg_tmp += result[3][i]; -+ -+ if (reg_tmp) -+ candidate = 3; -+ else -+ candidate = -1; -+ } -+ } -+ } -+ -+ for (i = 0; i < 4; i++) { -+ reg_e94 = result[i][0]; -+ reg_e9c = result[i][1]; -+ reg_ea4 = result[i][2]; -+ reg_eac = result[i][3]; -+ reg_eb4 = result[i][4]; -+ reg_ebc = result[i][5]; -+ reg_ec4 = result[i][6]; -+ reg_ecc = result[i][7]; -+ } -+ -+ if (candidate >= 0) { -+ reg_e94 = result[candidate][0]; -+ priv->rege94 = reg_e94; -+ reg_e9c = result[candidate][1]; -+ priv->rege9c = reg_e9c; -+ reg_ea4 = result[candidate][2]; -+ reg_eac = result[candidate][3]; -+ reg_eb4 = result[candidate][4]; -+ priv->regeb4 = reg_eb4; -+ reg_ebc = result[candidate][5]; -+ priv->regebc = reg_ebc; -+ reg_ec4 = result[candidate][6]; -+ reg_ecc = result[candidate][7]; -+ dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); -+ dev_dbg(dev, -+ "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n", -+ __func__, reg_e94, reg_e9c, -+ reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); -+ path_a_ok = true; -+ } else { -+ reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; -+ reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; -+ } -+ -+ if (reg_e94 && candidate >= 0) -+ rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, -+ candidate, (reg_ea4 == 0)); -+ -+ rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, -+ priv->bb_recovery_backup, RTL8XXXU_BB_REGS); -+ -+ rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb); -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, path_sel_rf); -+} -+ -+static void rtl8188f_disabled_to_emu(struct rtl8xxxu_priv *priv) -+{ -+ u16 val8; -+ -+ /* 0x04[12:11] = 2b'01enable WL suspend */ -+ val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); -+ val8 &= ~((APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND) >> 8); -+ rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); -+ -+ /* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode */ -+ val8 = rtl8xxxu_read8(priv, 0xc4); -+ val8 &= ~BIT(4); -+ rtl8xxxu_write8(priv, 0xc4, val8); -+} -+ -+static int rtl8188f_emu_to_active(struct rtl8xxxu_priv *priv) -+{ -+ u8 val8; -+ u32 val32; -+ int count, ret = 0; -+ -+ /* Disable SW LPS */ -+ val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); -+ val8 &= ~(APS_FSMCO_SW_LPS >> 8); -+ rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); -+ -+ /* wait till 0x04[17] = 1 power ready */ -+ for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { -+ val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); -+ if (val32 & BIT(17)) -+ break; -+ -+ udelay(10); -+ } -+ -+ if (!count) { -+ ret = -EBUSY; -+ goto exit; -+ } -+ -+ /* Disable HWPDN */ -+ val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); -+ val8 &= ~(APS_FSMCO_HW_POWERDOWN >> 8); -+ rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); -+ -+ /* Disable WL suspend */ -+ val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); -+ val8 &= ~(APS_FSMCO_HW_SUSPEND >> 8); -+ rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); -+ -+ /* set, then poll until 0 */ -+ val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); -+ val8 |= APS_FSMCO_MAC_ENABLE >> 8; -+ rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); -+ -+ for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { -+ val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); -+ if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { -+ ret = 0; -+ break; -+ } -+ udelay(10); -+ } -+ -+ if (!count) { -+ ret = -EBUSY; -+ goto exit; -+ } -+ -+ /* 0x27<=35 to reduce RF noise */ -+ val8 = rtl8xxxu_write8(priv, 0x27, 0x35); -+exit: -+ return ret; -+} -+ -+static int rtl8188fu_active_to_emu(struct rtl8xxxu_priv *priv) -+{ -+ u8 val8; -+ u32 val32; -+ int count, ret = 0; -+ -+ /* Turn off RF */ -+ rtl8xxxu_write8(priv, REG_RF_CTRL, 0); -+ -+ /* 0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ -+ val8 = rtl8xxxu_read8(priv, 0x4e); -+ val8 &= ~BIT(7); -+ rtl8xxxu_write8(priv, 0x4e, val8); -+ -+ /* 0x27 <= 34, xtal_qsel = 0 to xtal bring up */ -+ rtl8xxxu_write8(priv, 0x27, 0x34); -+ -+ /* 0x04[9] = 1 turn off MAC by HW state machine */ -+ val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); -+ val8 |= APS_FSMCO_MAC_OFF >> 8; -+ rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); -+ -+ for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { -+ val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); -+ if ((val32 & APS_FSMCO_MAC_OFF) == 0) { -+ ret = 0; -+ break; -+ } -+ udelay(10); -+ } -+ -+ if (!count) { -+ ret = -EBUSY; -+ goto exit; -+ } -+ -+exit: -+ return ret; -+} -+ -+static int rtl8188fu_emu_to_disabled(struct rtl8xxxu_priv *priv) -+{ -+ u8 val8; -+ -+ /* 0x04[12:11] = 2b'01 enable WL suspend */ -+ val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); -+ val8 &= ~((APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND) >> 8); -+ val8 |= APS_FSMCO_HW_SUSPEND >> 8; -+ rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); -+ -+ /* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode */ -+ val8 = rtl8xxxu_read8(priv, 0xc4); -+ val8 |= BIT(4); -+ rtl8xxxu_write8(priv, 0xc4, val8); -+ -+ return 0; -+} -+ -+static int rtl8188fu_active_to_lps(struct rtl8xxxu_priv *priv) -+{ -+ struct device *dev = &priv->udev->dev; -+ u8 val8; -+ u16 val16; -+ u32 val32; -+ int retry, retval; -+ -+ /* set RPWM IMR */ -+ val8 = rtl8xxxu_read8(priv, REG_FTIMR + 1); -+ val8 |= IMR0_CPWM >> 8; -+ rtl8xxxu_write8(priv, REG_FTIMR + 1, val8); -+ -+ /* Tx Pause */ -+ rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); -+ -+ retry = 100; -+ retval = -EBUSY; -+ -+ /* -+ * Poll 32 bit wide REG_SCH_TX_CMD for 0x00000000 to ensure no TX is pending. -+ */ -+ do { -+ val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); -+ if (!val32) { -+ retval = 0; -+ break; -+ } -+ } while (retry--); -+ -+ if (!retry) { -+ dev_warn(dev, "Failed to flush TX queue\n"); -+ retval = -EBUSY; -+ goto out; -+ } -+ -+ /* Disable CCK and OFDM, clock gated */ -+ val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); -+ val8 &= ~SYS_FUNC_BBRSTB; -+ rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); -+ -+ udelay(2); -+ -+ /* Whole BB is reset */ -+ val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); -+ val8 &= ~SYS_FUNC_BB_GLB_RSTN; -+ rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); -+ -+ /* Reset MAC TRX */ -+ val16 = rtl8xxxu_read16(priv, REG_CR); -+ val16 |= 0x3f; -+ val16 &= ~(CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | CR_SECURITY_ENABLE); -+ rtl8xxxu_write16(priv, REG_CR, val16); -+ -+ /* Respond TxOK to scheduler */ -+ val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); -+ val8 |= DUAL_TSF_TX_OK; -+ rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); -+ -+out: -+ return retval; -+} -+ -+static int rtl8188fu_power_on(struct rtl8xxxu_priv *priv) -+{ -+ u16 val16; -+ int ret; -+ -+ rtl8188f_disabled_to_emu(priv); -+ -+ ret = rtl8188f_emu_to_active(priv); -+ if (ret) -+ goto exit; -+ -+ rtl8xxxu_write8(priv, REG_CR, 0); -+ -+ val16 = rtl8xxxu_read16(priv, REG_CR); -+ -+ val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | -+ CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | -+ CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | -+ CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); -+ rtl8xxxu_write16(priv, REG_CR, val16); -+ -+exit: -+ return ret; -+} -+ -+static void rtl8188fu_power_off(struct rtl8xxxu_priv *priv) -+{ -+ u8 val8; -+ u16 val16; -+ -+ rtl8xxxu_flush_fifo(priv); -+ -+ val16 = rtl8xxxu_read16(priv, REG_GPIO_MUXCFG); -+ val16 &= ~BIT(12); -+ rtl8xxxu_write16(priv, REG_GPIO_MUXCFG, val16); -+ -+ rtl8xxxu_write32(priv, REG_HISR0, 0xFFFFFFFF); -+ rtl8xxxu_write32(priv, REG_HISR1, 0xFFFFFFFF); -+ -+ /* Stop Tx Report Timer. 0x4EC[Bit1]=b'0 */ -+ val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); -+ val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE; -+ rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); -+ -+ /* Turn off RF */ -+ rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); -+ -+ /* Reset Firmware if running in RAM */ -+ if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) -+ rtl8xxxu_firmware_self_reset(priv); -+ -+ rtl8188fu_active_to_lps(priv); -+ -+ /* Reset MCU */ -+ val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); -+ val16 &= ~SYS_FUNC_CPU_ENABLE; -+ rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); -+ -+ /* Reset MCU ready status */ -+ rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); -+ -+ rtl8188fu_active_to_emu(priv); -+ rtl8188fu_emu_to_disabled(priv); -+} -+ -+#define PPG_BB_GAIN_2G_TXA_OFFSET_8188F 0xee -+#define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0f -+ -+static void rtl8188f_enable_rf(struct rtl8xxxu_priv *priv) -+{ -+ u32 val32; -+ u8 pg_pwrtrim = 0xff, val8; -+ s8 bb_gain; -+ -+ /* Somehow this is not found in the efuse we read earlier. */ -+ rtl8xxxu_read_efuse8(priv, PPG_BB_GAIN_2G_TXA_OFFSET_8188F, &pg_pwrtrim); -+ -+ if (pg_pwrtrim != 0xff) { -+ bb_gain = pg_pwrtrim & PPG_BB_GAIN_2G_TX_OFFSET_MASK; -+ -+ if (bb_gain == PPG_BB_GAIN_2G_TX_OFFSET_MASK) -+ bb_gain = 0; -+ else if (bb_gain & 1) -+ bb_gain = bb_gain >> 1; -+ else -+ bb_gain = -(bb_gain >> 1); -+ -+ val8 = abs(bb_gain); -+ if (bb_gain > 0) -+ val8 |= BIT(5); -+ -+ val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55); -+ val32 &= ~0xfc000; -+ val32 |= val8 << 14; -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, val32); -+ } -+ -+ rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB); -+ -+ val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); -+ val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); -+ val32 |= OFDM_RF_PATH_RX_A | OFDM_RF_PATH_TX_A; -+ rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); -+ -+ rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); -+} -+ -+static void rtl8188f_disable_rf(struct rtl8xxxu_priv *priv) -+{ -+ u32 val32; -+ -+ val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); -+ val32 &= ~OFDM_RF_PATH_TX_MASK; -+ rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); -+ -+ /* Power down RF module */ -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); -+} -+ -+static void rtl8188f_usb_quirks(struct rtl8xxxu_priv *priv) -+{ -+ u16 val16; -+ u32 val32; -+ -+ val16 = rtl8xxxu_read16(priv, REG_CR); -+ val16 |= (CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE); -+ rtl8xxxu_write16(priv, REG_CR, val16); -+ -+ val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK); -+ val32 |= TXDMA_OFFSET_DROP_DATA_EN; -+ rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32); -+} -+ -+struct rtl8xxxu_fileops rtl8188fu_fops = { -+ .parse_efuse = rtl8188fu_parse_efuse, -+ .load_firmware = rtl8188fu_load_firmware, -+ .power_on = rtl8188fu_power_on, -+ .power_off = rtl8188fu_power_off, -+ .reset_8051 = rtl8xxxu_reset_8051, -+ .llt_init = rtl8xxxu_auto_llt_table, -+ .init_phy_bb = rtl8188fu_init_phy_bb, -+ .init_phy_rf = rtl8188fu_init_phy_rf, -+ .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection, -+ .phy_lc_calibrate = rtl8188f_phy_lc_calibrate, -+ .phy_iq_calibrate = rtl8188fu_phy_iq_calibrate, -+ .config_channel = rtl8188fu_config_channel, -+ .parse_rx_desc = rtl8xxxu_parse_rxdesc24, -+ .init_aggregation = rtl8188fu_init_aggregation, -+ .init_statistics = rtl8188fu_init_statistics, -+ .enable_rf = rtl8188f_enable_rf, -+ .disable_rf = rtl8188f_disable_rf, -+ .usb_quirks = rtl8188f_usb_quirks, -+ .set_tx_power = rtl8188f_set_tx_power, -+ .update_rate_mask = rtl8xxxu_gen2_update_rate_mask, -+ .report_connect = rtl8xxxu_gen2_report_connect, -+ .fill_txdesc = rtl8xxxu_fill_txdesc_v2, -+ .writeN_block_size = 128, -+ .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24), -+ .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40), -+ .has_s0s1 = 1, -+ .has_tx_report = 1, -+ .gen2_thermal_meter = 1, -+ .needs_full_init = 1, -+ .adda_1t_init = 0x03c00014, -+ .adda_1t_path_on = 0x03c00014, -+ .trxff_boundary = 0x3f7f, -+ .pbp_rx = PBP_PAGE_SIZE_256, -+ .pbp_tx = PBP_PAGE_SIZE_256, -+ .mactable = rtl8188f_mac_init_table, -+ .total_page_num = TX_TOTAL_PAGE_NUM_8188F, -+ .page_num_hi = TX_PAGE_NUM_HI_PQ_8188F, -+ .page_num_lo = TX_PAGE_NUM_LO_PQ_8188F, -+ .page_num_norm = TX_PAGE_NUM_NORM_PQ_8188F, -+}; -diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192c.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192c.c -index 27c4cb688..dd84da516 100644 ---- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192c.c -+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192c.c -@@ -549,6 +549,7 @@ struct rtl8xxxu_fileops rtl8192cu_fops = { - .llt_init = rtl8xxxu_init_llt_table, - .init_phy_bb = rtl8xxxu_gen1_init_phy_bb, - .init_phy_rf = rtl8192cu_init_phy_rf, -+ .phy_lc_calibrate = rtl8723a_phy_lc_calibrate, - .phy_iq_calibrate = rtl8xxxu_gen1_phy_iq_calibrate, - .config_channel = rtl8xxxu_gen1_config_channel, - .parse_rx_desc = rtl8xxxu_parse_rxdesc16, -diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c -index b06508d0c..c37bae079 100644 ---- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c -+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c -@@ -1680,6 +1680,7 @@ struct rtl8xxxu_fileops rtl8192eu_fops = { - .llt_init = rtl8xxxu_auto_llt_table, - .init_phy_bb = rtl8192eu_init_phy_bb, - .init_phy_rf = rtl8192eu_init_phy_rf, -+ .phy_lc_calibrate = rtl8723a_phy_lc_calibrate, - .phy_iq_calibrate = rtl8192eu_phy_iq_calibrate, - .config_channel = rtl8xxxu_gen2_config_channel, - .parse_rx_desc = rtl8xxxu_parse_rxdesc24, -diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.c -index 4f93f8871..e18ddd441 100644 ---- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.c -+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.c -@@ -366,6 +366,7 @@ struct rtl8xxxu_fileops rtl8723au_fops = { - .llt_init = rtl8xxxu_init_llt_table, - .init_phy_bb = rtl8xxxu_gen1_init_phy_bb, - .init_phy_rf = rtl8723au_init_phy_rf, -+ .phy_lc_calibrate = rtl8723a_phy_lc_calibrate, - .phy_iq_calibrate = rtl8xxxu_gen1_phy_iq_calibrate, - .config_channel = rtl8xxxu_gen1_config_channel, - .parse_rx_desc = rtl8xxxu_parse_rxdesc16, -diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c -index a71e1816e..7c9b8432a 100644 ---- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c -+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c -@@ -518,7 +518,7 @@ static int rtl8723bu_init_phy_rf(struct rtl8xxxu_priv *priv) - return ret; - } - --static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv) -+void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv) - { - u32 val32; - -@@ -1650,6 +1650,7 @@ struct rtl8xxxu_fileops rtl8723bu_fops = { - .init_phy_bb = rtl8723bu_init_phy_bb, - .init_phy_rf = rtl8723bu_init_phy_rf, - .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection, -+ .phy_lc_calibrate = rtl8723a_phy_lc_calibrate, - .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate, - .config_channel = rtl8xxxu_gen2_config_channel, - .parse_rx_desc = rtl8xxxu_parse_rxdesc24, -diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c -index e9c1b62c9..75576c839 100644 ---- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c -+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c -@@ -52,6 +52,7 @@ MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin"); - MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin"); - MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin"); - MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin"); -+MODULE_FIRMWARE("rtlwifi/rtl8188fufw.bin"); - - module_param_named(debug, rtl8xxxu_debug, int, 0600); - MODULE_PARM_DESC(debug, "Set debug mask"); -@@ -1606,6 +1607,7 @@ static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv) - - static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv) - { -+ const struct usb_device_descriptor *descriptor = &priv->udev->descriptor; - struct device *dev = &priv->udev->dev; - struct ieee80211_hw *hw = priv->hw; - u32 val32, bonding, sys_cfg; -@@ -1619,6 +1621,17 @@ static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv) - return -ENOTSUPP; - } - -+ if (descriptor->idVendor == USB_VENDOR_ID_REALTEK && -+ descriptor->idProduct == 0xf179) { -+ sprintf(priv->chip_name, "8188FU"); -+ priv->rtl_chip = RTL8188F; -+ priv->rf_paths = 1; -+ priv->rx_paths = 1; -+ priv->tx_paths = 1; -+ priv->has_wifi = 1; -+ goto skip_complicated_chip_detection; -+ } -+ - if (sys_cfg & SYS_CFG_BT_FUNC) { - if (priv->chip_cut >= 3) { - sprintf(priv->chip_name, "8723BU"); -@@ -1685,11 +1698,14 @@ static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv) - priv->has_wifi = 1; - } - -+ skip_complicated_chip_detection: -+ - hw->wiphy->available_antennas_tx = BIT(priv->tx_paths) - 1; - hw->wiphy->available_antennas_rx = BIT(priv->rx_paths) - 1; - - switch (priv->rtl_chip) { - case RTL8188E: -+ case RTL8188F: - case RTL8192E: - case RTL8723B: - switch (sys_cfg & SYS_CFG_VENDOR_EXT_MASK) { -@@ -1720,7 +1736,18 @@ static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv) - val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); - priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28; - -- val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX); -+ /* -+ * 8188FU vendor driver doesn't use REG_NORMAL_SIE_EP_TX, -+ * it just decides the queue mapping based on nr_out_eps. -+ * However, reading the register returns "0x321" which -+ * results in a wrong ep_tx_count of 3 and most frames -+ * not being transmitted. -+ */ -+ if (priv->rtl_chip == RTL8188F) -+ val16 = 0; -+ else -+ val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX); -+ - if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) { - priv->ep_tx_high_queue = 1; - priv->ep_tx_count++; -@@ -1763,7 +1790,7 @@ static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv) - return 0; - } - --static int -+int - rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data) - { - int i; -@@ -1979,7 +2006,7 @@ static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv) - /* - * Init H2C command - */ -- if (priv->rtl_chip == RTL8723B) -+ if (priv->rtl_chip == RTL8723B || priv->rtl_chip == RTL8188F) - rtl8xxxu_write8(priv, REG_HMTFR, 0x0f); - exit: - return ret; -@@ -2099,6 +2126,7 @@ int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name) - case 0x88c0: - case 0x5300: - case 0x2300: -+ case 0x88f0: - break; - default: - ret = -EINVAL; -@@ -2166,7 +2194,9 @@ rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv) - } - } - -- if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E) -+ if (priv->rtl_chip != RTL8723B && -+ priv->rtl_chip != RTL8192E && -+ priv->rtl_chip != RTL8188F) - rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a); - - return 0; -@@ -3427,7 +3457,7 @@ void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv) - priv->bb_recovery_backup, RTL8XXXU_BB_REGS); - } - --static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv) -+void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv) - { - u32 val32; - u32 rf_amode, rf_bmode = 0, lstf; -@@ -4031,6 +4061,9 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw) - if (priv->rtl_chip == RTL8192E) { - rtl8xxxu_write32(priv, REG_HIMR0, 0x00); - rtl8xxxu_write32(priv, REG_HIMR1, 0x00); -+ } else if (priv->rtl_chip == RTL8188F) { -+ rtl8xxxu_write32(priv, REG_HISR0, 0xffffffff); -+ rtl8xxxu_write32(priv, REG_HISR1, 0xffffffff); - } else { - /* - * Enable all interrupts - not obvious USB needs to do this -@@ -4050,11 +4083,25 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw) - RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC; - rtl8xxxu_write32(priv, REG_RCR, val32); - -- /* -- * Accept all multicast -- */ -- rtl8xxxu_write32(priv, REG_MAR, 0xffffffff); -- rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff); -+ if (priv->rtl_chip == RTL8188F) { -+ /* Accept all data frames */ -+ rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff); -+ -+ /* -+ * Since ADF is removed from RCR, ps-poll will not be indicate to driver, -+ * RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. -+ */ -+ rtl8xxxu_write16(priv, REG_RXFLTMAP1, 0x400); -+ -+ /* Accept all management frames */ -+ rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff); -+ } else { -+ /* -+ * Accept all multicast -+ */ -+ rtl8xxxu_write32(priv, REG_MAR, 0xffffffff); -+ rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff); -+ } - - /* - * Init adaptive controls -@@ -4105,14 +4152,17 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw) - val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8); - rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16); - rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404); -- rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME); -+ if (priv->rtl_chip != RTL8188F) -+ /* Firmware will control REG_DRVERLYINT when power saving is enable, */ -+ /* so don't set this register on STA mode. */ -+ rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME); - rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME); - rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F); - - /* - * Initialize burst parameters - */ -- if (priv->rtl_chip == RTL8723B) { -+ if (priv->rtl_chip == RTL8723B || priv->rtl_chip == RTL8188F) { - /* - * For USB high speed set 512B packets - */ -@@ -4130,13 +4180,27 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw) - rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8); - - rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14); -- rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 0x5e); -+ if (priv->rtl_chip == RTL8723B) -+ val8 = 0x5e; -+ else if (priv->rtl_chip == RTL8188F) -+ val8 = 0x70; /* 0x5e would make it very slow */ -+ rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, val8); - rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff); - rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18); - rtl8xxxu_write8(priv, REG_PIFS, 0x00); -- rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, 0x50); -- rtl8xxxu_write8(priv, REG_USTIME_EDCA, 0x50); -- -+ -+ if (priv->rtl_chip == RTL8188F) { -+ rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, FWHW_TXQ_CTRL_AMPDU_RETRY); -+ rtl8xxxu_write32(priv, REG_FAST_EDCA_CTRL, 0x03086666); -+ } -+ if (priv->rtl_chip == RTL8723B) -+ val8 = 0x50; -+ else if (priv->rtl_chip == RTL8188F) -+ val8 = 0x28; /* 0x50 would make the upload slow */ -+ rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, val8); -+ rtl8xxxu_write8(priv, REG_USTIME_EDCA, val8); -+ -+ /* to prevent mac is reseted by bus. */ - val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); - val8 |= BIT(5) | BIT(6); - rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); -@@ -4145,6 +4209,11 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw) - if (fops->init_aggregation) - fops->init_aggregation(priv); - -+ if (priv->rtl_chip == RTL8188F) { -+ rtl8xxxu_write16(priv, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */ -+ rtl8xxxu_write16(priv, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */ -+ } -+ - /* - * Enable CCK and OFDM block - */ -@@ -4163,7 +4232,7 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw) - fops->set_tx_power(priv, 1, false); - - /* Let the 8051 take control of antenna setting */ -- if (priv->rtl_chip != RTL8192E) { -+ if (priv->rtl_chip != RTL8192E && priv->rtl_chip != RTL8188F) { - val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); - val8 |= LEDCFG2_DPDT_SELECT; - rtl8xxxu_write8(priv, REG_LEDCFG2, val8); -@@ -4174,7 +4243,8 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw) - /* Disable BAR - not sure if this has any effect on USB */ - rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff); - -- rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0); -+ if (priv->rtl_chip != RTL8188F) -+ rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0); - - if (fops->init_statistics) - fops->init_statistics(priv); -@@ -4191,20 +4261,38 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw) - * Reset USB mode switch setting - */ - rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00); -+ } else if (priv->rtl_chip == RTL8188F) { -+ /* -+ * Init GPIO settings for 8188f -+ */ -+ val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG); -+ val8 &= ~GPIO_MUXCFG_IO_SEL_ENBT; -+ rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8); - } - -- rtl8723a_phy_lc_calibrate(priv); -+ if (priv->rtl_chip == RTL8188F) -+ /* CCK PD */ -+ rtl8xxxu_write8(priv, REG_CCK_PD_THRESH, CCK_PD_TYPE1_LV1_TH); -+ -+ fops->phy_lc_calibrate(priv); - - fops->phy_iq_calibrate(priv); - - /* - * This should enable thermal meter - */ -- if (fops->gen2_thermal_meter) -- rtl8xxxu_write_rfreg(priv, -- RF_A, RF6052_REG_T_METER_8723B, 0x37cf8); -- else -+ if (fops->gen2_thermal_meter) { -+ if (priv->rtl_chip == RTL8188F) { -+ val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B); -+ val32 |= 0x30000; -+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B, val32); -+ } else { -+ rtl8xxxu_write_rfreg(priv, -+ RF_A, RF6052_REG_T_METER_8723B, 0x37cf8); -+ } -+ } else { - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60); -+ } - - /* Set NAV_UPPER to 30000us */ - val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT); -@@ -6678,6 +6766,7 @@ static int rtl8xxxu_probe(struct usb_interface *interface, - case 0x8178: - case 0x817f: - case 0x818b: -+ case 0xf179: - untested = 0; - break; - } -@@ -6890,6 +6979,9 @@ static const struct usb_device_id dev_table[] = { - .driver_info = (unsigned long)&rtl8723bu_fops}, - {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xa611, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8723bu_fops}, -+/* RTL8188FU */ -+{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xf179, 0xff, 0xff, 0xff), -+ .driver_info = (unsigned long)&rtl8188fu_fops}, - #ifdef CONFIG_RTL8XXXU_UNTESTED - /* Still supported by rtlwifi */ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff), -diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h -index 438b65ba9..35bde1404 100644 ---- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h -+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h -@@ -135,6 +135,7 @@ - #define REG_CAL_TIMER 0x003c - #define REG_ACLK_MON 0x003e - #define REG_GPIO_MUXCFG 0x0040 -+#define GPIO_MUXCFG_IO_SEL_ENBT BIT(5) - #define REG_GPIO_IO_SEL 0x0042 - #define REG_MAC_PINMUX_CFG 0x0043 - #define REG_GPIO_PIN_CTRL 0x0044 -@@ -391,6 +392,7 @@ - #define REG_CPWM 0x012f - #define REG_FWIMR 0x0130 - #define REG_FWISR 0x0134 -+#define REG_FTIMR 0x0138 - #define REG_PKTBUF_DBG_CTRL 0x0140 - #define REG_PKTBUF_DBG_DATA_L 0x0144 - #define REG_PKTBUF_DBG_DATA_H 0x0148 -@@ -440,6 +442,9 @@ - - #define REG_FIFOPAGE 0x0204 - #define REG_TDECTRL 0x0208 -+ -+#define REG_DWBCN0_CTRL_8188F REG_TDECTRL -+ - #define REG_TXDMA_OFFSET_CHK 0x020c - #define TXDMA_OFFSET_DROP_DATA_EN BIT(9) - #define REG_TXDMA_STATUS 0x0210 -@@ -925,6 +930,7 @@ - - #define REG_FPGA0_XA_LSSI_READBACK 0x08a0 /* Tranceiver LSSI Readback */ - #define REG_FPGA0_XB_LSSI_READBACK 0x08a4 -+#define REG_FPGA0_PSD_REPORT 0x08b4 - #define REG_HSPI_XA_READBACK 0x08b8 /* Transceiver A HSPI read */ - #define REG_HSPI_XB_READBACK 0x08bc /* Transceiver B HSPI read */ - -@@ -936,6 +942,7 @@ - #define REG_RFE_PATH_SELECT 0x0940 /* 8723BU */ - #define REG_RFE_BUFFER 0x0944 /* 8723BU */ - #define REG_S0S1_PATH_SWITCH 0x0948 /* 8723BU */ -+#define REG_OFDM_RX_DFIR 0x954 - - #define REG_CCK0_SYSTEM 0x0a00 - #define CCK0_SIDEBAND BIT(4) -@@ -946,6 +953,13 @@ - #define CCK0_AFE_RX_ANT_A 0 - #define CCK0_AFE_RX_ANT_B (BIT(24) | BIT(26)) - -+#define REG_CCK_PD_THRESH 0x0a0a -+#define CCK_PD_TYPE1_LV0_TH 0x40 -+#define CCK_PD_TYPE1_LV1_TH 0x83 -+#define CCK_PD_TYPE1_LV2_TH 0xcd -+#define CCK_PD_TYPE1_LV3_TH 0xdd -+#define CCK_PD_TYPE1_LV4_TH 0xed -+ - #define REG_CONFIG_ANT_A 0x0b68 - #define REG_CONFIG_ANT_B 0x0b6c - -@@ -965,6 +979,7 @@ - - #define REG_OFDM0_FA_RSTC 0x0c0c - -+#define REG_OFDM0_XA_RX_AFE 0x0c10 - #define REG_OFDM0_XA_RX_IQ_IMBALANCE 0x0c14 - #define REG_OFDM0_XB_RX_IQ_IMBALANCE 0x0c1c - -@@ -1011,6 +1026,9 @@ - #define OFDM_LSTF_MASK 0x70000000 - - #define REG_OFDM1_TRX_PATH_ENABLE 0x0d04 -+#define REG_OFDM1_CFO_TRACKING 0x0d2c -+#define REG_OFDM1_CSI_FIX_MASK1 0x0d40 -+#define REG_OFDM1_CSI_FIX_MASK2 0x0d44 - - #define REG_TX_AGC_A_RATE18_06 0x0e00 - #define REG_TX_AGC_A_RATE54_24 0x0e04 -@@ -1202,6 +1220,7 @@ - #define RF6052_REG_UNKNOWN_43 0x43 - #define RF6052_REG_UNKNOWN_55 0x55 - #define RF6052_REG_UNKNOWN_56 0x56 -+#define RF6052_REG_RXG_MIX_SWBW 0x87 - #define RF6052_REG_S0S1 0xb0 - #define RF6052_REG_UNKNOWN_DF 0xdf - #define RF6052_REG_UNKNOWN_ED 0xed diff --git a/projects/Rockchip/packages/linux/patches/RK3399/007-rk3399-vpu.patch b/projects/Rockchip/packages/linux/patches/RK3399/007-rk3399-vpu.patch deleted file mode 100644 index e570d12b9..000000000 --- a/projects/Rockchip/packages/linux/patches/RK3399/007-rk3399-vpu.patch +++ /dev/null @@ -1,8577 +0,0 @@ -diff -rupN linux.orig/Documentation/devicetree/bindings/media/rockchip,vdec.yaml linux/Documentation/devicetree/bindings/media/rockchip,vdec.yaml ---- linux.orig/Documentation/devicetree/bindings/media/rockchip,vdec.yaml 2024-01-03 20:53:28.383294161 +0000 -+++ linux/Documentation/devicetree/bindings/media/rockchip,vdec.yaml 2024-01-03 21:26:02.707011192 +0000 -@@ -53,6 +53,18 @@ properties: - iommus: - maxItems: 1 - -+ resets: -+ maxItems: 6 -+ -+ reset-names: -+ items: -+ - const: video_h -+ - const: video_a -+ - const: video_core -+ - const: video_cabac -+ - const: niu_a -+ - const: niu_h -+ - required: - - compatible - - reg -@@ -60,6 +72,8 @@ required: - - clocks - - clock-names - - power-domains -+ - resets -+ - reset-names - - additionalProperties: false - -@@ -78,6 +92,11 @@ examples: - clock-names = "axi", "ahb", "cabac", "core"; - power-domains = <&power RK3399_PD_VDU>; - iommus = <&vdec_mmu>; -+ resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>, -+ <&cru SRST_VDU_CORE>, <&cru SRST_VDU_CA>, -+ <&cru SRST_A_VDU_NOC>, <&cru SRST_H_VDU_NOC>; -+ reset-names = "video_h", "video_a", "video_core", "video_cabac", -+ "niu_a", "niu_h"; - }; - - ... -diff -rupN linux.orig/Documentation/devicetree/bindings/media/rockchip-iep.yaml linux/Documentation/devicetree/bindings/media/rockchip-iep.yaml ---- linux.orig/Documentation/devicetree/bindings/media/rockchip-iep.yaml 1970-01-01 00:00:00.000000000 +0000 -+++ linux/Documentation/devicetree/bindings/media/rockchip-iep.yaml 2024-01-03 21:28:43.674043912 +0000 -@@ -0,0 +1,73 @@ -+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/media/rockchip-iep.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Rockchip Image Enhancement Processor (IEP) -+ -+description: -+ Rockchip IEP supports various image enhancement operations for YUV and RGB domains. -+ Deinterlacing, spatial and temporal sampling noise reduction are supported by the -+ YUV block. Gamma adjustment, edge enhancement, detail enhancement are supported in -+ the RGB block. Brightness, Saturation, Contrast, Hue adjustment is supported for -+ both domains. Furthermore it supports converting RGB to YUV / YUV to RGB. -+ -+maintainers: -+ - Heiko Stuebner -+ -+properties: -+ compatible: -+ oneOf: -+ - const: rockchip,rk3228-iep -+ - items: -+ - enum: -+ - rockchip,rk3288-iep -+ - rockchip,rk3328-iep -+ - rockchip,rk3368-iep -+ - rockchip,rk3399-iep -+ - const: rockchip,rk3228-iep -+ -+ reg: -+ maxItems: 1 -+ -+ interrupts: -+ maxItems: 1 -+ -+ clocks: -+ maxItems: 2 -+ -+ clock-names: -+ items: -+ - const: axi -+ - const: ahb -+ -+ power-domains: -+ maxItems: 1 -+ -+ iommus: -+ maxItems: 1 -+ -+required: -+ - compatible -+ - reg -+ - interrupts -+ - clocks -+ - clock-names -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ #include -+ #include -+ iep: iep@20070000 { -+ compatible = "rockchip,rk3228-iep"; -+ reg = <0x20070000 0x800>; -+ interrupts = ; -+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; -+ clock-names = "axi", "ahb"; -+ iommus = <&iep_mmu>; -+ power-domains = <&power RK3228_PD_VIO>; -+ }; -diff -rupN linux.orig/arch/arm/boot/dts/rk3288-miqi.dts linux/arch/arm/boot/dts/rk3288-miqi.dts ---- linux.orig/arch/arm/boot/dts/rk3288-miqi.dts 2024-01-03 20:53:28.931301546 +0000 -+++ linux/arch/arm/boot/dts/rk3288-miqi.dts 2024-01-03 21:27:13.822235237 +0000 -@@ -78,6 +78,21 @@ - regulator-always-on; - regulator-boot-on; - }; -+ -+ sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,name = "HDMI"; -+ simple-audio-card,mclk-fs = <512>; -+ -+ simple-audio-card,codec { -+ sound-dai = <&hdmi>; -+ }; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&i2s>; -+ }; -+ }; - }; - - &cpu0 { -@@ -130,6 +145,8 @@ - - &hdmi { - ddc-i2c-bus = <&i2c5>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hdmi_cec_c0>; - status = "okay"; - }; - -@@ -283,6 +300,11 @@ - status = "okay"; - }; - -+&i2s { -+ #sound-dai-cells = <0>; -+ status = "okay"; -+}; -+ - &io_domains { - status = "okay"; - -diff -rupN linux.orig/arch/arm/boot/dts/rk3288-tinker.dtsi linux/arch/arm/boot/dts/rk3288-tinker.dtsi ---- linux.orig/arch/arm/boot/dts/rk3288-tinker.dtsi 2024-01-03 20:53:28.931301546 +0000 -+++ linux/arch/arm/boot/dts/rk3288-tinker.dtsi 2024-01-03 21:27:13.822235237 +0000 -@@ -73,7 +73,7 @@ - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; -- simple-audio-card,name = "rockchip,tinker-codec"; -+ simple-audio-card,name = "HDMI"; - simple-audio-card,mclk-fs = <512>; - - simple-audio-card,codec { -diff -rupN linux.orig/arch/arm/boot/dts/rk3288.dtsi linux/arch/arm/boot/dts/rk3288.dtsi ---- linux.orig/arch/arm/boot/dts/rk3288.dtsi 2024-01-03 20:53:28.935301600 +0000 -+++ linux/arch/arm/boot/dts/rk3288.dtsi 2024-01-03 21:28:43.674043912 +0000 -@@ -984,14 +984,25 @@ - reset-names = "crypto-rst"; - }; - -+ iep: iep@ff90000 { -+ compatible = "rockchip,rk3288-iep", "rockchip,rk3228-iep"; -+ reg = <0x0 0xff900000 0x0 0x800>; -+ interrupts = ; -+ interrupt-names = "iep"; -+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; -+ clock-names = "axi", "ahb"; -+ power-domains = <&power RK3288_PD_VIO>; -+ iommus = <&iep_mmu>; -+ }; -+ - iep_mmu: iommu@ff900800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff900800 0x0 0x40>; - interrupts = ; - clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; - clock-names = "aclk", "iface"; -+ power-domains = <&power RK3288_PD_VIO>; - #iommu-cells = <0>; -- status = "disabled"; - }; - - isp_mmu: iommu@ff914000 { -@@ -1017,7 +1028,7 @@ - }; - - vopb: vop@ff930000 { -- compatible = "rockchip,rk3288-vop"; -+ compatible = "rockchip,rk3288-vop-big"; - reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>; - interrupts = ; - clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; -@@ -1026,6 +1037,8 @@ - resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vopb_mmu>; -+ assigned-clocks = <&cru DCLK_VOP0>; -+ assigned-clock-parents = <&cru PLL_NPLL>; - status = "disabled"; - - vopb_out: port { -@@ -1066,7 +1079,7 @@ - }; - - vopl: vop@ff940000 { -- compatible = "rockchip,rk3288-vop"; -+ compatible = "rockchip,rk3288-vop-lit"; - reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>; - interrupts = ; - clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; -@@ -1081,11 +1094,6 @@ - #address-cells = <1>; - #size-cells = <0>; - -- vopl_out_hdmi: endpoint@0 { -- reg = <0>; -- remote-endpoint = <&hdmi_in_vopl>; -- }; -- - vopl_out_edp: endpoint@1 { - reg = <1>; - remote-endpoint = <&edp_in_vopl>; -@@ -1226,10 +1234,6 @@ - reg = <0>; - remote-endpoint = <&vopb_out_hdmi>; - }; -- hdmi_in_vopl: endpoint@1 { -- reg = <1>; -- remote-endpoint = <&vopl_out_hdmi>; -- }; - }; - }; - }; -@@ -1256,6 +1260,25 @@ - power-domains = <&power RK3288_PD_VIDEO>; - }; - -+ hevc: hevc@ff9c0000 { -+ compatible = "rockchip,rk3288-hevc"; -+ reg = <0x0 0xff9c0000 0x0 0x400>; -+ interrupts = ; -+ interrupt-names = "irq_dec"; -+ clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, <&cru SCLK_HEVC_CABAC>, -+ <&cru SCLK_HEVC_CORE>; -+ clock-names = "axi", "ahb", "cabac", "core"; -+ assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, -+ <&cru SCLK_HEVC_CORE>, -+ <&cru SCLK_HEVC_CABAC>; -+ assigned-clock-rates = <400000000>, <100000000>, -+ <300000000>, <300000000>; -+ iommus = <&hevc_mmu>; -+ power-domains = <&power RK3288_PD_HEVC>; -+ resets = <&cru SRST_HEVC>; -+ reset-names = "video_core"; -+ }; -+ - hevc_mmu: iommu@ff9c0440 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; -@@ -1263,7 +1286,7 @@ - clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; -- status = "disabled"; -+ power-domains = <&power RK3288_PD_HEVC>; - }; - - gpu: gpu@ffa30000 { -diff -rupN linux.orig/arch/arm64/boot/dts/rockchip/rk3328-a1.dts linux/arch/arm64/boot/dts/rockchip/rk3328-a1.dts ---- linux.orig/arch/arm64/boot/dts/rockchip/rk3328-a1.dts 2024-01-03 20:53:29.227305541 +0000 -+++ linux/arch/arm64/boot/dts/rockchip/rk3328-a1.dts 2024-01-03 21:27:13.822235237 +0000 -@@ -57,6 +57,24 @@ - gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; - linux,rc-map-name = "rc-beelink-gs1"; - }; -+ -+ spdif_sound: spdif-sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,name = "SPDIF"; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&spdif>; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&spdif_dit>; -+ }; -+ }; -+ -+ spdif_dit: spdif-dit { -+ compatible = "linux,spdif-dit"; -+ #sound-dai-cells = <0>; -+ }; - }; - - &analog_sound { -@@ -129,6 +147,14 @@ - }; - }; - -+&gmac2phy { -+ clock_in_out = "output"; -+ assigned-clock-rate = <50000000>; -+ assigned-clocks = <&cru SCLK_MAC2PHY>; -+ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; -+ status = "okay"; -+}; -+ - &gpu { - mali-supply = <&vdd_logic>; - }; -@@ -325,6 +351,11 @@ - status = "okay"; - }; - -+&spdif { -+ pinctrl-0 = <&spdifm0_tx>; -+ status = "okay"; -+}; -+ - &tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; -@@ -358,6 +389,11 @@ - status = "okay"; - }; - -+&usbdrd3 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ - &vop { - status = "okay"; - }; -diff -rupN linux.orig/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts linux/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts ---- linux.orig/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts 2024-01-03 20:53:29.227305541 +0000 -+++ linux/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts 2024-01-03 21:27:13.822235237 +0000 -@@ -88,6 +88,13 @@ - regulator-boot-on; - }; - -+ ir-receiver { -+ compatible = "gpio-ir-receiver"; -+ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; -+ pinctrl-0 = <&ir_int>; -+ pinctrl-names = "default"; -+ }; -+ - leds { - compatible = "gpio-leds"; - -@@ -164,6 +171,10 @@ - status = "okay"; - }; - -+&gpu { -+ mali-supply = <&vdd_logic>; -+}; -+ - &hdmi { - status = "okay"; - }; -@@ -306,6 +317,13 @@ - }; - - &pinctrl { -+ -+ ir { -+ ir_int: ir-int { -+ rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; -diff -rupN linux.orig/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts linux/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts ---- linux.orig/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts 2024-01-03 20:53:29.227305541 +0000 -+++ linux/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts 2024-01-03 21:27:13.822235237 +0000 -@@ -162,6 +162,10 @@ - status = "okay"; - }; - -+&gpu { -+ mali-supply = <&vdd_logic>; -+}; -+ - &hdmi { - status = "okay"; - }; -diff -rupN linux.orig/arch/arm64/boot/dts/rockchip/rk3328.dtsi linux/arch/arm64/boot/dts/rockchip/rk3328.dtsi ---- linux.orig/arch/arm64/boot/dts/rockchip/rk3328.dtsi 2024-01-03 20:53:29.227305541 +0000 -+++ linux/arch/arm64/boot/dts/rockchip/rk3328.dtsi 2024-01-03 21:32:47.747235430 +0000 -@@ -300,6 +300,11 @@ - #address-cells = <1>; - #size-cells = <0>; - -+ power-domain@RK3328_PD_GPU { -+ reg = ; -+ clocks = <&cru ACLK_GPU>; -+ #power-domain-cells = <0>; -+ }; - power-domain@RK3328_PD_HEVC { - reg = ; - #power-domain-cells = <0>; -@@ -539,6 +544,11 @@ - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - contribution = <4096>; - }; -+ map1 { -+ trip = <&target>; -+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ contribution = <4096>; -+ }; - }; - }; - -@@ -620,7 +630,32 @@ - "ppmmu1"; - clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; - clock-names = "bus", "core"; -+ operating-points-v2 = <&gpu_opp_table>; -+ power-domains = <&power RK3328_PD_GPU>; - resets = <&cru SRST_GPU_A>; -+ #cooling-cells = <2>; -+ }; -+ -+ gpu_opp_table: gpu-opp-table { -+ compatible = "operating-points-v2"; -+ -+ opp-200000000 { -+ opp-hz = /bits/ 64 <200000000>; -+ opp-microvolt = <1075000>; -+ }; -+ opp-300000000 { -+ opp-hz = /bits/ 64 <300000000>; -+ opp-microvolt = <1075000>; -+ }; -+ opp-400000000 { -+ opp-hz = /bits/ 64 <400000000>; -+ opp-microvolt = <1075000>; -+ }; -+ opp-500000000 { -+ opp-hz = /bits/ 64 <500000000>; -+ opp-microvolt = <1150000>; -+ status = "disabled"; -+ }; - }; - - h265e_mmu: iommu@ff330200 { -@@ -674,6 +709,11 @@ - assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, - <&cru SCLK_VDEC_CORE>; - assigned-clock-rates = <400000000>, <400000000>, <300000000>; -+ resets = <&cru SRST_VDEC_H>, <&cru SRST_VDEC_A>, -+ <&cru SRST_VDEC_CORE>, <&cru SRST_VDEC_CABAC>, -+ <&cru SRST_VDEC_NIU_A>, <&cru SRST_VDEC_NIU_H>; -+ reset-names = "video_h", "video_a", "video_core", "video_cabac", -+ "niu_a", "niu_h"; - iommus = <&vdec_mmu>; - power-domains = <&power RK3328_PD_VIDEO>; - }; -@@ -720,6 +760,28 @@ - status = "disabled"; - }; - -+ iep: iep@ff3a0000 { -+ compatible = "rockchip,rk3328-iep", "rockchip,rk3228-iep"; -+ reg = <0x0 0xff3a0000 0x0 0x800>; -+ interrupts = ; -+ interrupt-names = "iep"; -+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; -+ clock-names = "axi", "ahb"; -+ power-domains = <&power RK3328_PD_VIDEO>; -+ iommus = <&iep_mmu>; -+ }; -+ -+ iep_mmu: iommu@ff3a0800 { -+ compatible = "rockchip,iommu"; -+ reg = <0x0 0xff3a0800 0x0 0x40>; -+ interrupts = ; -+ interrupt-names = "iep_mmu"; -+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; -+ clock-names = "aclk", "iface"; -+ power-domains = <&power RK3328_PD_VIDEO>; -+ #iommu-cells = <0>; -+ }; -+ - hdmi: hdmi@ff3c0000 { - compatible = "rockchip,rk3328-dw-hdmi"; - reg = <0x0 0xff3c0000 0x0 0x20000>; -@@ -811,8 +873,8 @@ - <0>, <24000000>, - <24000000>, <24000000>, - <15000000>, <15000000>, -- <100000000>, <100000000>, -- <100000000>, <100000000>, -+ <300000000>, <100000000>, -+ <400000000>, <100000000>, - <50000000>, <100000000>, - <100000000>, <100000000>, - <50000000>, <50000000>, -@@ -871,6 +933,8 @@ - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; -+ resets = <&cru SRST_MMC0>; -+ reset-names = "reset"; - status = "disabled"; - }; - -@@ -883,6 +947,8 @@ - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; -+ resets = <&cru SRST_SDIO>; -+ reset-names = "reset"; - status = "disabled"; - }; - -@@ -895,6 +961,8 @@ - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; -+ resets = <&cru SRST_EMMC>; -+ reset-names = "reset"; - status = "disabled"; - }; - -@@ -993,6 +1061,20 @@ - status = "disabled"; - }; - -+ sdmmc_ext: mmc@ff5f0000 { -+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; -+ reg = <0x0 0xff5f0000 0x0 0x4000>; -+ interrupts = ; -+ clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>, -+ <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>; -+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; -+ fifo-depth = <0x100>; -+ max-frequency = <150000000>; -+ resets = <&cru SRST_SDMMCEXT>; -+ reset-names = "reset"; -+ status = "disabled"; -+ }; -+ - usbdrd3: usb@ff600000 { - compatible = "rockchip,rk3328-dwc3", "snps,dwc3"; - reg = <0x0 0xff600000 0x0 0x100000>; -diff -rupN linux.orig/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi linux/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi ---- linux.orig/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi 2024-01-03 20:53:29.231305593 +0000 -+++ linux/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi 2024-01-03 21:27:13.822235237 +0000 -@@ -215,7 +215,7 @@ - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; -- regulator-min-microvolt = <450000>; -+ regulator-min-microvolt = <430000>; - regulator-max-microvolt = <1400000>; - pwm-supply = <&vcc3v3_sys>; - }; -@@ -536,7 +536,7 @@ - pinctrl-names = "default"; - pinctrl-0 = <&fusb1_int>; - vbus-supply = <&vcc_vbus_typec1>; -- status = "okay"; -+ status = "disabled"; - }; - }; - -@@ -553,7 +553,7 @@ - pinctrl-names = "default"; - pinctrl-0 = <&fusb0_int>; - vbus-supply = <&vcc_vbus_typec0>; -- status = "okay"; -+ status = "disabled"; - }; - - mp8859: regulator@66 { -diff -rupN linux.orig/arch/arm64/boot/dts/rockchip/rk3399.dtsi linux/arch/arm64/boot/dts/rockchip/rk3399.dtsi ---- linux.orig/arch/arm64/boot/dts/rockchip/rk3399.dtsi 2024-01-03 20:53:29.231305593 +0000 -+++ linux/arch/arm64/boot/dts/rockchip/rk3399.dtsi 2024-01-03 21:28:43.674043912 +0000 -@@ -1347,6 +1347,11 @@ - clock-names = "axi", "ahb", "cabac", "core"; - iommus = <&vdec_mmu>; - power-domains = <&power RK3399_PD_VDU>; -+ resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>, -+ <&cru SRST_VDU_CORE>, <&cru SRST_VDU_CA>, -+ <&cru SRST_A_VDU_NOC>, <&cru SRST_H_VDU_NOC>; -+ reset-names = "video_h", "video_a", "video_core", "video_cabac", -+ "niu_a", "niu_h"; - }; - - vdec_mmu: iommu@ff660480 { -@@ -1359,14 +1364,25 @@ - #iommu-cells = <0>; - }; - -+ iep: iep@ff670000 { -+ compatible = "rockchip,rk3399-iep", "rockchip,rk3228-iep"; -+ reg = <0x0 0xff670000 0x0 0x800>; -+ interrupts = ; -+ interrupt-names = "iep"; -+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; -+ clock-names = "axi", "ahb"; -+ power-domains = <&power RK3399_PD_IEP>; -+ iommus = <&iep_mmu>; -+ }; -+ - iep_mmu: iommu@ff670800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff670800 0x0 0x40>; - interrupts = ; - clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; - clock-names = "aclk", "iface"; -+ power-domains = <&power RK3399_PD_IEP>; - #iommu-cells = <0>; -- status = "disabled"; - }; - - rga: rga@ff680000 { -@@ -1471,7 +1487,7 @@ - <1000000000>, - <150000000>, <75000000>, - <37500000>, -- <100000000>, <100000000>, -+ <300000000>, <100000000>, - <50000000>, <600000000>, - <100000000>, <50000000>, - <400000000>, <400000000>, -@@ -1730,11 +1746,6 @@ - remote-endpoint = <&edp_in_vopl>; - }; - -- vopl_out_hdmi: endpoint@2 { -- reg = <2>; -- remote-endpoint = <&hdmi_in_vopl>; -- }; -- - vopl_out_mipi1: endpoint@3 { - reg = <3>; - remote-endpoint = <&mipi1_in_vopl>; -@@ -1892,7 +1903,7 @@ - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; -- simple-audio-card,name = "hdmi-sound"; -+ simple-audio-card,name = "HDMI"; - status = "disabled"; - - simple-audio-card,cpu { -@@ -1928,10 +1939,6 @@ - reg = <0>; - remote-endpoint = <&vopb_out_hdmi>; - }; -- hdmi_in_vopl: endpoint@1 { -- reg = <1>; -- remote-endpoint = <&vopl_out_hdmi>; -- }; - }; - }; - }; -diff -rupN linux.orig/drivers/clk/rockchip/clk-rk3228.c linux/drivers/clk/rockchip/clk-rk3228.c ---- linux.orig/drivers/clk/rockchip/clk-rk3228.c 2024-01-03 20:53:29.851313959 +0000 -+++ linux/drivers/clk/rockchip/clk-rk3228.c 2024-01-03 21:17:09.402615966 +0000 -@@ -409,7 +409,7 @@ static struct rockchip_clk_branch rk3228 - RK2928_CLKSEL_CON(29), 0, 3, DFLAGS), - DIV(0, "sclk_vop_pre", "sclk_vop_src", 0, - RK2928_CLKSEL_CON(27), 8, 8, DFLAGS), -- MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, 0, -+ MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - RK2928_CLKSEL_CON(27), 1, 1, MFLAGS), - - FACTOR(0, "xin12m", "xin24m", 0, 1, 2), -diff -rupN linux.orig/drivers/clk/rockchip/clk-rk3288.c linux/drivers/clk/rockchip/clk-rk3288.c ---- linux.orig/drivers/clk/rockchip/clk-rk3288.c 2024-01-03 20:53:29.851313959 +0000 -+++ linux/drivers/clk/rockchip/clk-rk3288.c 2024-01-03 21:17:09.402615966 +0000 -@@ -121,6 +121,43 @@ static struct rockchip_pll_rate_table rk - { /* sentinel */ }, - }; - -+static struct rockchip_pll_rate_table rk3288_npll_rates[] = { -+ RK3066_PLL_RATE_NB(594000000, 1, 198, 8, 1), -+ RK3066_PLL_RATE_NB(585000000, 6, 585, 4, 32), -+ RK3066_PLL_RATE_NB(432000000, 3, 216, 4, 32), -+ RK3066_PLL_RATE_NB(426000000, 3, 213, 4, 32), -+ RK3066_PLL_RATE_NB(400000000, 1, 100, 6, 32), -+ RK3066_PLL_RATE(348500000, 8, 697, 6), -+ RK3066_PLL_RATE_NB(342000000, 3, 171, 4, 32), -+ RK3066_PLL_RATE_NB(297000000, 2, 198, 8, 16), -+ RK3066_PLL_RATE_NB(270000000, 1, 135, 12, 32), -+ RK3066_PLL_RATE_NB(260000000, 1, 130, 12, 32), -+ RK3066_PLL_RATE(241500000, 2, 161, 8), -+ RK3066_PLL_RATE(162000000, 1, 81, 12), -+ RK3066_PLL_RATE(154000000, 6, 539, 14), -+ RK3066_PLL_RATE_NB(148500000, 1, 99, 16, 32), -+ RK3066_PLL_RATE(148352000, 13, 1125, 14), -+ RK3066_PLL_RATE_NB(146250000, 6, 585, 16, 32), -+ RK3066_PLL_RATE(121750000, 6, 487, 16), -+ RK3066_PLL_RATE(119000000, 3, 238, 16), -+ RK3066_PLL_RATE_NB(108000000, 1, 54, 12, 32), -+ RK3066_PLL_RATE_NB(106500000, 4, 213, 12, 32), -+ RK3066_PLL_RATE(101000000, 3, 202, 16), -+ RK3066_PLL_RATE(88750000, 6, 355, 16), -+ RK3066_PLL_RATE_NB(85500000, 4, 171, 12, 32), -+ RK3066_PLL_RATE(83500000, 3, 167, 16), -+ RK3066_PLL_RATE(79500000, 1, 53, 16), -+ RK3066_PLL_RATE_NB(74250000, 4, 198, 16, 32), -+ RK3066_PLL_RATE(74176000, 26, 1125, 14), -+ RK3066_PLL_RATE(72000000, 1, 48, 16), -+ RK3066_PLL_RATE(71000000, 3, 142, 16), -+ RK3066_PLL_RATE(68250000, 2, 91, 16), -+ RK3066_PLL_RATE(65000000, 3, 130, 16), -+ RK3066_PLL_RATE(40000000, 3, 80, 16), -+ RK3066_PLL_RATE(33750000, 2, 45, 16), -+ { /* sentinel */ }, -+}; -+ - #define RK3288_DIV_ACLK_CORE_M0_MASK 0xf - #define RK3288_DIV_ACLK_CORE_M0_SHIFT 0 - #define RK3288_DIV_ACLK_CORE_MP_MASK 0xf -@@ -195,8 +232,9 @@ PNAME(mux_ddrphy_p) = { "dpll_ddr", "gp - PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu" }; - - PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" }; --PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" }; --PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" }; -+PNAME(mux_pll_src_npll_cpll_gpll_p) = { "prevent:npll", "cpll", "gpll" }; -+PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "prevent:npll" }; -+PNAME(vop0_mux_pll_src_cpll_gpll_npll_p) = { "prevent:cpll", "prevent:gpll", "npll" }; - PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "unstable:usbphy480m_src" }; - PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "unstable:usbphy480m_src", "npll" }; - -@@ -232,7 +270,7 @@ static struct rockchip_pll_clock rk3288_ - [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12), - RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates), - [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16), -- RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates), -+ RK3288_MODE_CON, 14, 9, 0, rk3288_npll_rates), - }; - - static struct clk_div_table div_hclk_cpu_t[] = { -@@ -442,7 +480,7 @@ static struct rockchip_clk_branch rk3288 - RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS, - RK3288_CLKGATE_CON(3), 4, GFLAGS), - -- COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0, -+ COMPOSITE(DCLK_VOP0, "dclk_vop0", vop0_mux_pll_src_cpll_gpll_npll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, - RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS, - RK3288_CLKGATE_CON(3), 1, GFLAGS), - COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0, -diff -rupN linux.orig/drivers/clk/rockchip/clk-rk3399.c linux/drivers/clk/rockchip/clk-rk3399.c ---- linux.orig/drivers/clk/rockchip/clk-rk3399.c 2024-01-03 20:53:29.851313959 +0000 -+++ linux/drivers/clk/rockchip/clk-rk3399.c 2024-01-03 21:17:09.402615966 +0000 -@@ -105,6 +105,39 @@ static struct rockchip_pll_rate_table rk - { /* sentinel */ }, - }; - -+static struct rockchip_pll_rate_table rk3399_vpll_rates[] = { -+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ -+ RK3036_PLL_RATE( 594000000, 1, 74, 3, 1, 0, 4194304), /* vco = 1782000000 fout = 594000000 */ -+ RK3036_PLL_RATE( 593406592, 1, 74, 3, 1, 0, 2949838), /* vco = 1780219777 fout = 593406592.36908 */ -+ RK3036_PLL_RATE( 319750000, 1, 79, 6, 1, 0, 15728640), /* vco = 1918500000 fout = 319750000 */ -+ RK3036_PLL_RATE( 297000000, 1, 74, 6, 1, 0, 4194304), /* vco = 1782000000 fout = 297000000 */ -+ RK3036_PLL_RATE( 296703296, 1, 74, 6, 1, 0, 2949838), /* vco = 1780219777 fout = 296703296.18454 */ -+ RK3036_PLL_RATE( 241500000, 1, 60, 6, 1, 0, 6291456), /* vco = 1449000000 fout = 241500000 */ -+ RK3036_PLL_RATE( 162000000, 1, 67, 5, 2, 0, 8388608), /* vco = 1620000000 fout = 162000000 */ -+ RK3036_PLL_RATE( 148500000, 1, 74, 6, 2, 0, 4194304), /* vco = 1782000000 fout = 148500000*/ -+ RK3036_PLL_RATE( 148351648, 1, 74, 6, 2, 0, 2949838), /* vco = 1780219777 fout = 148351648.09227 */ -+ RK3036_PLL_RATE( 136750000, 1, 68, 2, 6, 0, 6291456), /* vco = 1641000000 fout = 136750000 */ -+ RK3036_PLL_RATE( 135000000, 1, 56, 5, 2, 0, 4194304), /* vco = 1350000000 fout = 135000000 */ -+ RK3036_PLL_RATE( 119000000, 1, 59, 6, 2, 0, 8388608), /* vco = 1428000000 fout = 119000000 */ -+ RK3036_PLL_RATE( 108000000, 1, 63, 7, 2, 1, 0), /* vco = 1512000000 fout = 108000000 */ -+ RK3036_PLL_RATE( 106500000, 1, 62, 7, 2, 0, 2097152), /* vco = 1491000000 fout = 106500000 */ -+ RK3036_PLL_RATE( 88750000, 1, 55, 5, 3, 0, 7864320), /* vco = 1331250000 fout = 88750000 */ -+ RK3036_PLL_RATE( 85500000, 1, 57, 4, 4, 1, 0), /* vco = 1368000000 fout = 85500000 */ -+ RK3036_PLL_RATE( 78750000, 1, 59, 6, 3, 0, 1048576), /* vco = 1417500000 fout = 78750000 */ -+ RK3036_PLL_RATE( 74250000, 1, 74, 6, 4, 0, 4194304), /* vco = 1782000000 fout = 74250000 */ -+ RK3036_PLL_RATE( 74175824, 1, 74, 6, 4, 0, 2949838), /* vco = 1780219777 fout = 74175824.046135 */ -+ RK3036_PLL_RATE( 71000000, 1, 71, 6, 4, 1, 0), /* vco = 1704000000 fout = 71000000 */ -+ RK3036_PLL_RATE( 65000000, 1, 65, 6, 4, 0, 0), /* vco = 1560000000 fout = 65000000 */ -+ RK3036_PLL_RATE( 59340659, 1, 59, 6, 4, 0, 5715310), /* vco = 1424175816 fout = 59340659.022331 */ -+ RK3036_PLL_RATE( 54000000, 1, 63, 7, 4, 1, 0), /* vco = 1512000000 fout = 54000000 */ -+ RK3036_PLL_RATE( 49500000, 1, 72, 5, 7, 0, 3145728), /* vco = 1732500000 fout = 49500000 */ -+ RK3036_PLL_RATE( 40000000, 1, 70, 7, 6, 1, 0), /* vco = 1680000000 fout = 40000000 */ -+ RK3036_PLL_RATE( 31500000, 1, 55, 7, 6, 0, 2097152), /* vco = 1323000000 fout = 31500000 */ -+ RK3036_PLL_RATE( 27000000, 1, 55, 7, 7, 0, 2097152), /* vco = 1323000000 fout = 27000000 */ -+ RK3036_PLL_RATE( 26973026, 1, 55, 7, 7, 0, 1173214), /* vco = 1321678296 fout = 26973026.450799 */ -+ { /* sentinel */ }, -+}; -+ - /* CRU parents */ - PNAME(mux_pll_p) = { "xin24m", "xin32k" }; - -@@ -123,7 +156,7 @@ PNAME(mux_ddrclk_p) = { "clk_ddrc_lpl - PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src", - "gpll_aclk_cci_src", - "npll_aclk_cci_src", -- "vpll_aclk_cci_src" }; -+ "prevent:vpll" }; - PNAME(mux_cci_trace_p) = { "cpll_cci_trace", - "gpll_cci_trace" }; - PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs", -@@ -149,10 +182,12 @@ PNAME(mux_pll_src_cpll_gpll_npll_upll_24 - PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", - "ppll", "upll", "xin24m" }; - --PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" }; --PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll", "cpll", "gpll", -+PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "prevent:vpll", "cpll", "gpll" }; -+PNAME(vop0_mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "prevent:cpll", "prevent:gpll" }; -+ -+PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "prevent:vpll", "cpll", "gpll", - "npll" }; --PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "vpll", "cpll", "gpll", -+PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "prevent:vpll", "cpll", "gpll", - "xin24m" }; - - PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div", -@@ -229,7 +264,7 @@ static struct rockchip_pll_clock rk3399_ - [npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40), - RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), - [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48), -- RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), -+ RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_vpll_rates), - }; - - static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = { -@@ -279,7 +314,7 @@ static struct rockchip_clk_branch rk3399 - RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS); - - static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata = -- MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT, -+ MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - RK3399_CLKSEL_CON(49), 11, 1, MFLAGS); - - static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata = -@@ -1162,7 +1197,7 @@ static struct rockchip_clk_branch rk3399 - GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED, - RK3399_CLKGATE_CON(28), 0, GFLAGS), - -- COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, 0, -+ COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", vop0_mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS, - RK3399_CLKGATE_CON(10), 12, GFLAGS), - -diff -rupN linux.orig/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c linux/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c ---- linux.orig/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c 2024-01-03 20:53:30.399321361 +0000 -+++ linux/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c 2024-01-03 21:27:13.822235237 +0000 -@@ -4,6 +4,7 @@ - * - * Copyright (C) 2015-2017 Russell King. - */ -+#include - #include - #include - #include -@@ -129,8 +130,15 @@ static irqreturn_t dw_hdmi_cec_hardirq(i - - dw_hdmi_write(cec, stat, HDMI_IH_CEC_STAT0); - -- if (stat & CEC_STAT_ERROR_INIT) { -- cec->tx_status = CEC_TX_STATUS_ERROR; -+ /* Status with both done and error_initiator bits have been seen -+ * on Rockchip RK3328 devices, transmit attempt seems to have failed -+ * when this happens, report as low drive and block cec-framework -+ * 100ms before core retransmits the failed message, this seems to -+ * mitigate the issue with failed transmit attempts. -+ */ -+ if ((stat & (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) == (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) { -+ pr_debug("dw_hdmi_cec_hardirq: stat=%02x LOW_DRIVE\n", stat); -+ cec->tx_status = CEC_TX_STATUS_LOW_DRIVE; - cec->tx_done = true; - ret = IRQ_WAKE_THREAD; - } else if (stat & CEC_STAT_DONE) { -@@ -141,6 +149,10 @@ static irqreturn_t dw_hdmi_cec_hardirq(i - cec->tx_status = CEC_TX_STATUS_NACK; - cec->tx_done = true; - ret = IRQ_WAKE_THREAD; -+ } else if (stat & CEC_STAT_ERROR_INIT) { -+ cec->tx_status = CEC_TX_STATUS_ERROR; -+ cec->tx_done = true; -+ ret = IRQ_WAKE_THREAD; - } - - if (stat & CEC_STAT_EOM) { -@@ -173,6 +185,8 @@ static irqreturn_t dw_hdmi_cec_thread(in - - if (cec->tx_done) { - cec->tx_done = false; -+ if (cec->tx_status == CEC_TX_STATUS_LOW_DRIVE) -+ msleep(100); - cec_transmit_attempt_done(adap, cec->tx_status); - } - if (cec->rx_done) { -diff -rupN linux.orig/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c linux/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c ---- linux.orig/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c 2024-01-03 20:53:30.399321361 +0000 -+++ linux/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c 2024-01-03 21:27:13.822235237 +0000 -@@ -34,9 +34,9 @@ static inline u8 hdmi_read(struct dw_hdm - return audio->read(hdmi, offset); - } - --static int dw_hdmi_i2s_hw_params(struct device *dev, void *data, -- struct hdmi_codec_daifmt *fmt, -- struct hdmi_codec_params *hparms) -+static int dw_hdmi_i2s_prepare(struct device *dev, void *data, -+ struct hdmi_codec_daifmt *fmt, -+ struct hdmi_codec_params *hparms) - { - struct dw_hdmi_i2s_audio_data *audio = data; - struct dw_hdmi *hdmi = audio->hdmi; -@@ -178,7 +178,7 @@ static int dw_hdmi_i2s_hook_plugged_cb(s - } - - static const struct hdmi_codec_ops dw_hdmi_i2s_ops = { -- .hw_params = dw_hdmi_i2s_hw_params, -+ .prepare = dw_hdmi_i2s_prepare, - .audio_startup = dw_hdmi_i2s_audio_startup, - .audio_shutdown = dw_hdmi_i2s_audio_shutdown, - .get_eld = dw_hdmi_i2s_get_eld, -diff -rupN linux.orig/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c linux/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ---- linux.orig/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c 2024-01-03 20:53:30.399321361 +0000 -+++ linux/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c 2024-01-03 21:17:09.402615966 +0000 -@@ -82,15 +82,15 @@ static const u16 csc_coeff_rgb_out_eitu7 - }; - - static const u16 csc_coeff_rgb_in_eitu601[3][4] = { -- { 0x2591, 0x1322, 0x074b, 0x0000 }, -- { 0x6535, 0x2000, 0x7acc, 0x0200 }, -- { 0x6acd, 0x7534, 0x2000, 0x0200 } -+ { 0x2040, 0x1080, 0x0640, 0x0040 }, -+ { 0xe880, 0x1c00, 0xfb80, 0x0200 }, -+ { 0xed80, 0xf680, 0x1c00, 0x0200 } - }; - - static const u16 csc_coeff_rgb_in_eitu709[3][4] = { -- { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, -- { 0x62f0, 0x2000, 0x7d11, 0x0200 }, -- { 0x6756, 0x78ab, 0x2000, 0x0200 } -+ { 0x2740, 0x0bc0, 0x0400, 0x0040 }, -+ { 0xe680, 0x1c00, 0xfd80, 0x0200 }, -+ { 0xea40, 0xf980, 0x1c00, 0x0200 } - }; - - static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = { -@@ -138,7 +138,8 @@ struct dw_hdmi_phy_data { - bool has_svsret; - int (*configure)(struct dw_hdmi *hdmi, - const struct dw_hdmi_plat_data *pdata, -- unsigned long mpixelclock); -+ unsigned long mpixelclock, -+ unsigned long mtmdsclock); - }; - - struct dw_hdmi { -@@ -1585,13 +1586,17 @@ static int dw_hdmi_phy_power_on(struct d - */ - static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, - const struct dw_hdmi_plat_data *pdata, -- unsigned long mpixelclock) -+ unsigned long mpixelclock, -+ unsigned long mtmdsclock) - { - const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; - const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; - const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; -+ int depth; - -- /* TOFIX Will need 420 specific PHY configuration tables */ -+ if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) && -+ pdata->mpll_cfg_420) -+ mpll_config = pdata->mpll_cfg_420; - - /* PLL/MPLL Cfg - always match on final entry */ - for (; mpll_config->mpixelclock != ~0UL; mpll_config++) -@@ -1599,11 +1604,11 @@ static int hdmi_phy_configure_dwc_hdmi_3 - break; - - for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) -- if (mpixelclock <= curr_ctrl->mpixelclock) -+ if (mtmdsclock <= curr_ctrl->mpixelclock) - break; - - for (; phy_config->mpixelclock != ~0UL; phy_config++) -- if (mpixelclock <= phy_config->mpixelclock) -+ if (mtmdsclock <= phy_config->mpixelclock) - break; - - if (mpll_config->mpixelclock == ~0UL || -@@ -1611,11 +1616,17 @@ static int hdmi_phy_configure_dwc_hdmi_3 - phy_config->mpixelclock == ~0UL) - return -EINVAL; - -- dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, -+ depth = hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); -+ if (depth > 8 && mpixelclock != mtmdsclock) -+ depth = fls(depth - 8) - 1; -+ else -+ depth = 0; -+ -+ dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].cpce, - HDMI_3D_TX_PHY_CPCE_CTRL); -- dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, -+ dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].gmp, - HDMI_3D_TX_PHY_GMPCTRL); -- dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], -+ dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[depth], - HDMI_3D_TX_PHY_CURRCTRL); - - dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); -@@ -1660,9 +1671,9 @@ static int hdmi_phy_configure(struct dw_ - - /* Write to the PHY as configured by the platform */ - if (pdata->configure_phy) -- ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock); -+ ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock, mtmdsclock); - else -- ret = phy->configure(hdmi, pdata, mpixelclock); -+ ret = phy->configure(hdmi, pdata, mpixelclock, mtmdsclock); - if (ret) { - dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n", - mpixelclock); -@@ -1779,6 +1790,7 @@ static void hdmi_config_AVI(struct dw_hd - const struct drm_connector *connector, - const struct drm_display_mode *mode) - { -+ const struct drm_connector_state *conn_state = connector->state; - struct hdmi_avi_infoframe frame; - u8 val; - -@@ -1836,6 +1848,8 @@ static void hdmi_config_AVI(struct dw_hd - HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; - } - -+ drm_hdmi_avi_infoframe_content_type(&frame, conn_state); -+ - /* - * The Designware IP uses a different byte format from standard - * AVI info frames, though generally the bits are in the correct -@@ -1992,6 +2006,21 @@ static void hdmi_config_drm_infoframe(st - HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN); - } - -+static unsigned int -+hdmi_get_tmdsclock(unsigned int bus_format, unsigned int pixelclock) -+{ -+ int color_depth = hdmi_bus_fmt_color_depth(bus_format); -+ unsigned int tmdsclock = pixelclock; -+ -+ if (!hdmi_bus_fmt_is_yuv422(bus_format) && color_depth > 8) -+ tmdsclock = (u64)pixelclock * color_depth / 8; -+ -+ if (hdmi_bus_fmt_is_yuv420(bus_format)) -+ tmdsclock /= 2; -+ -+ return tmdsclock; -+} -+ - static void hdmi_av_composer(struct dw_hdmi *hdmi, - const struct drm_display_info *display, - const struct drm_display_mode *mode) -@@ -2003,29 +2032,11 @@ static void hdmi_av_composer(struct dw_h - unsigned int vdisplay, hdisplay; - - vmode->mpixelclock = mode->clock * 1000; -+ vmode->mtmdsclock = -+ hdmi_get_tmdsclock(hdmi->hdmi_data.enc_out_bus_format, -+ vmode->mpixelclock); - - dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock); -- -- vmode->mtmdsclock = vmode->mpixelclock; -- -- if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { -- switch (hdmi_bus_fmt_color_depth( -- hdmi->hdmi_data.enc_out_bus_format)) { -- case 16: -- vmode->mtmdsclock = vmode->mpixelclock * 2; -- break; -- case 12: -- vmode->mtmdsclock = vmode->mpixelclock * 3 / 2; -- break; -- case 10: -- vmode->mtmdsclock = vmode->mpixelclock * 5 / 4; -- break; -- } -- } -- -- if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) -- vmode->mtmdsclock /= 2; -- - dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock); - - /* Set up HDMI_FC_INVIDCONF */ -@@ -2543,7 +2554,8 @@ static int dw_hdmi_connector_atomic_chec - if (!crtc) - return 0; - -- if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { -+ if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state) || -+ old_state->content_type != new_state->content_type) { - crtc_state = drm_atomic_get_crtc_state(state, crtc); - if (IS_ERR(crtc_state)) - return PTR_ERR(crtc_state); -@@ -2611,6 +2623,8 @@ static int dw_hdmi_connector_create(stru - - drm_connector_attach_max_bpc_property(connector, 8, 16); - -+ drm_connector_attach_content_type_property(connector); -+ - if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe) - drm_connector_attach_hdr_output_metadata_property(connector); - -@@ -2652,8 +2666,21 @@ static int dw_hdmi_connector_create(stru - * - MEDIA_BUS_FMT_RGB888_1X24, - */ - --/* Can return a maximum of 11 possible output formats for a mode/connector */ --#define MAX_OUTPUT_SEL_FORMATS 11 -+/* Can return a maximum of 15 possible output formats for a mode/connector */ -+#define MAX_OUTPUT_SEL_FORMATS 15 -+ -+static bool is_tmds_allowed(struct drm_display_info *info, -+ struct drm_display_mode *mode, -+ u32 bus_format) -+{ -+ unsigned long tmdsclock = hdmi_get_tmdsclock(bus_format, mode->clock); -+ int max_tmds_clock = info->max_tmds_clock ? info->max_tmds_clock : 340000; -+ -+ if (max_tmds_clock >= tmdsclock) -+ return true; -+ -+ return false; -+} - - static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, - struct drm_bridge_state *bridge_state, -@@ -2665,8 +2692,6 @@ static u32 *dw_hdmi_bridge_atomic_get_ou - struct drm_display_info *info = &conn->display_info; - struct drm_display_mode *mode = &crtc_state->mode; - u8 max_bpc = conn_state->max_requested_bpc; -- bool is_hdmi2_sink = info->hdmi.scdc.supported || -- (info->color_formats & DRM_COLOR_FORMAT_YCBCR420); - u32 *output_fmts; - unsigned int i = 0; - -@@ -2690,29 +2715,33 @@ static u32 *dw_hdmi_bridge_atomic_get_ou - * If the current mode enforces 4:2:0, force the output but format - * to 4:2:0 and do not add the YUV422/444/RGB formats - */ -- if (conn->ycbcr_420_allowed && -- (drm_mode_is_420_only(info, mode) || -- (is_hdmi2_sink && drm_mode_is_420_also(info, mode)))) { -+ if (conn->ycbcr_420_allowed && drm_mode_is_420(info, mode) && -+ (info->color_formats & DRM_COLOR_FORMAT_YCBCR420)) { - - /* Order bus formats from 16bit to 8bit if supported */ - if (max_bpc >= 16 && info->bpc == 16 && -- (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)) -+ (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) && -+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYYVYY16_0_5X48)) - output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY16_0_5X48; - - if (max_bpc >= 12 && info->bpc >= 12 && -- (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)) -+ (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) && -+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYYVYY12_0_5X36)) - output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY12_0_5X36; - - if (max_bpc >= 10 && info->bpc >= 10 && -- (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)) -+ (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) && -+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYYVYY10_0_5X30)) - output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY10_0_5X30; - - /* Default 8bit fallback */ -- output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24; -+ if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYYVYY8_0_5X24)) -+ output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24; - - *num_output_fmts = i; - -- return output_fmts; -+ if (drm_mode_is_420_only(info, mode)) -+ return output_fmts; - } - - /* -@@ -2721,39 +2750,50 @@ static u32 *dw_hdmi_bridge_atomic_get_ou - */ - - /* Default 8bit RGB fallback */ -- output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; -+ if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB888_1X24)) -+ output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; - - if (max_bpc >= 16 && info->bpc == 16) { -- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) -+ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR444) && -+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_YUV16_1X48)) - output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; - -- output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; -+ if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB161616_1X48)) -+ output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; - } - - if (max_bpc >= 12 && info->bpc >= 12) { -- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) -+ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR422) && -+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYVY12_1X24)) - output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; - -- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) -+ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR444) && -+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_YUV12_1X36)) - output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; - -- output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; -+ if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB121212_1X36)) -+ output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; - } - - if (max_bpc >= 10 && info->bpc >= 10) { -- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) -+ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR422) && -+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYVY10_1X20)) - output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; - -- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) -+ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR444) && -+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_YUV10_1X30)) - output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; - -- output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; -+ if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB101010_1X30)) -+ output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; - } - -- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) -+ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR422) && -+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYVY8_1X16)) - output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; - -- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) -+ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR444) && -+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_YUV8_1X24)) - output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; - - *num_output_fmts = i; -@@ -2935,11 +2975,20 @@ dw_hdmi_bridge_mode_valid(struct drm_bri - struct dw_hdmi *hdmi = bridge->driver_private; - const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; - enum drm_mode_status mode_status = MODE_OK; -+ int max_tmds_clock = info->max_tmds_clock ? info->max_tmds_clock : 340000; -+ int clock = mode->clock; - - /* We don't support double-clocked modes */ - if (mode->flags & DRM_MODE_FLAG_DBLCLK) - return MODE_BAD; - -+ if (pdata->ycbcr_420_allowed && drm_mode_is_420(info, mode) && -+ (info->color_formats & DRM_COLOR_FORMAT_YCBCR420)) -+ clock /= 2; -+ -+ if (clock > max_tmds_clock) -+ return MODE_CLOCK_HIGH; -+ - if (pdata->mode_valid) - mode_status = pdata->mode_valid(hdmi, pdata->priv_data, info, - mode); -@@ -3130,12 +3179,6 @@ static irqreturn_t dw_hdmi_irq(int irq, - phy_stat & HDMI_PHY_HPD, - phy_stat & HDMI_PHY_RX_SENSE); - -- if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) { -- mutex_lock(&hdmi->cec_notifier_mutex); -- cec_notifier_phys_addr_invalidate(hdmi->cec_notifier); -- mutex_unlock(&hdmi->cec_notifier_mutex); -- } -- - if (phy_stat & HDMI_PHY_HPD) - status = connector_status_connected; - -@@ -3152,6 +3195,14 @@ static irqreturn_t dw_hdmi_irq(int irq, - drm_helper_hpd_irq_event(hdmi->bridge.dev); - drm_bridge_hpd_notify(&hdmi->bridge, status); - } -+ -+ if (status == connector_status_disconnected && -+ (phy_stat & HDMI_PHY_RX_SENSE) && -+ (phy_int_pol & HDMI_PHY_RX_SENSE)) { -+ mutex_lock(&hdmi->cec_notifier_mutex); -+ cec_notifier_phys_addr_invalidate(hdmi->cec_notifier); -+ mutex_unlock(&hdmi->cec_notifier_mutex); -+ } - } - - hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); -diff -rupN linux.orig/drivers/gpu/drm/drm_fourcc.c linux/drivers/gpu/drm/drm_fourcc.c ---- linux.orig/drivers/gpu/drm/drm_fourcc.c 2024-01-03 20:53:30.403321415 +0000 -+++ linux/drivers/gpu/drm/drm_fourcc.c 2024-01-03 21:08:03.815052659 +0000 -@@ -299,6 +299,14 @@ const struct drm_format_info *__drm_form - .num_planes = 2, .char_per_block = { 5, 5, 0 }, - .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 2, - .vsub = 2, .is_yuv = true }, -+ { .format = DRM_FORMAT_NV20, .depth = 0, -+ .num_planes = 2, .char_per_block = { 5, 5, 0 }, -+ .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 2, -+ .vsub = 1, .is_yuv = true }, -+ { .format = DRM_FORMAT_NV30, .depth = 0, -+ .num_planes = 2, .char_per_block = { 5, 5, 0 }, -+ .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 1, -+ .vsub = 1, .is_yuv = true }, - { .format = DRM_FORMAT_Q410, .depth = 0, - .num_planes = 3, .char_per_block = { 2, 2, 2 }, - .block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, .hsub = 1, -diff -rupN linux.orig/drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c linux/drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c ---- linux.orig/drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c 2024-01-03 20:53:30.535323197 +0000 -+++ linux/drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c 2024-01-03 21:17:09.402615966 +0000 -@@ -53,7 +53,8 @@ rcar_hdmi_mode_valid(struct dw_hdmi *hdm - } - - static int rcar_hdmi_phy_configure(struct dw_hdmi *hdmi, void *data, -- unsigned long mpixelclock) -+ unsigned long mpixelclock, -+ unsigned long mtmdsclock) - { - const struct rcar_hdmi_phy_params *params = rcar_hdmi_phy_params; - -diff -rupN linux.orig/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c linux/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c ---- linux.orig/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c 2024-01-03 20:53:30.535323197 +0000 -+++ linux/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c 2024-01-03 21:17:09.402615966 +0000 -@@ -5,6 +5,7 @@ - - #include - #include -+#include - #include - #include - #include -@@ -67,11 +68,13 @@ struct rockchip_hdmi_chip_data { - int lcdsel_grf_reg; - u32 lcdsel_big; - u32 lcdsel_lit; -+ bool ycbcr_444_allowed; - }; - - struct rockchip_hdmi { - struct device *dev; - struct regmap *regmap; -+ struct drm_bridge bridge; - struct rockchip_encoder encoder; - const struct rockchip_hdmi_chip_data *chip_data; - struct clk *ref_clk; -@@ -82,89 +85,177 @@ struct rockchip_hdmi { - struct phy *phy; - }; - --static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder) --{ -- struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -+#define to_crtc_state(x) container_of(x, struct drm_crtc_state, x) - -- return container_of(rkencoder, struct rockchip_hdmi, encoder); -+static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_bridge *bridge) -+{ -+ return container_of(bridge, struct rockchip_hdmi, bridge); - } - - static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { - { -- 27000000, { -- { 0x00b3, 0x0000}, -- { 0x2153, 0x0000}, -- { 0x40f3, 0x0000} -- }, -- }, { -- 36000000, { -- { 0x00b3, 0x0000}, -- { 0x2153, 0x0000}, -- { 0x40f3, 0x0000} -- }, -- }, { -- 40000000, { -- { 0x00b3, 0x0000}, -- { 0x2153, 0x0000}, -- { 0x40f3, 0x0000} -- }, -- }, { -- 54000000, { -- { 0x0072, 0x0001}, -- { 0x2142, 0x0001}, -- { 0x40a2, 0x0001}, -- }, -- }, { -- 65000000, { -- { 0x0072, 0x0001}, -- { 0x2142, 0x0001}, -- { 0x40a2, 0x0001}, -- }, -- }, { -- 66000000, { -- { 0x013e, 0x0003}, -- { 0x217e, 0x0002}, -- { 0x4061, 0x0002} -- }, -- }, { -- 74250000, { -- { 0x0072, 0x0001}, -- { 0x2145, 0x0002}, -- { 0x4061, 0x0002} -- }, -- }, { -- 83500000, { -- { 0x0072, 0x0001}, -- }, -- }, { -- 108000000, { -- { 0x0051, 0x0002}, -- { 0x2145, 0x0002}, -- { 0x4061, 0x0002} -- }, -- }, { -- 106500000, { -- { 0x0051, 0x0002}, -- { 0x2145, 0x0002}, -- { 0x4061, 0x0002} -- }, -- }, { -- 146250000, { -- { 0x0051, 0x0002}, -- { 0x2145, 0x0002}, -- { 0x4061, 0x0002} -- }, -- }, { -- 148500000, { -- { 0x0051, 0x0003}, -- { 0x214c, 0x0003}, -- { 0x4064, 0x0003} -+ 30666000, { -+ { 0x00b3, 0x0000 }, -+ { 0x2153, 0x0000 }, -+ { 0x40f3, 0x0000 }, -+ }, -+ }, { -+ 36800000, { -+ { 0x00b3, 0x0000 }, -+ { 0x2153, 0x0000 }, -+ { 0x40a2, 0x0001 }, -+ }, -+ }, { -+ 46000000, { -+ { 0x00b3, 0x0000 }, -+ { 0x2142, 0x0001 }, -+ { 0x40a2, 0x0001 }, -+ }, -+ }, { -+ 61333000, { -+ { 0x0072, 0x0001 }, -+ { 0x2142, 0x0001 }, -+ { 0x40a2, 0x0001 }, -+ }, -+ }, { -+ 73600000, { -+ { 0x0072, 0x0001 }, -+ { 0x2142, 0x0001 }, -+ { 0x4061, 0x0002 }, -+ }, -+ }, { -+ 92000000, { -+ { 0x0072, 0x0001 }, -+ { 0x2145, 0x0002 }, -+ { 0x4061, 0x0002 }, -+ }, -+ }, { -+ 122666000, { -+ { 0x0051, 0x0002 }, -+ { 0x2145, 0x0002 }, -+ { 0x4061, 0x0002 }, -+ }, -+ }, { -+ 147200000, { -+ { 0x0051, 0x0002 }, -+ { 0x2145, 0x0002 }, -+ { 0x4064, 0x0003 }, -+ }, -+ }, { -+ 184000000, { -+ { 0x0051, 0x0002 }, -+ { 0x214c, 0x0003 }, -+ { 0x4064, 0x0003 }, -+ }, -+ }, { -+ 226666000, { -+ { 0x0040, 0x0003 }, -+ { 0x214c, 0x0003 }, -+ { 0x4064, 0x0003 }, -+ }, -+ }, { -+ 272000000, { -+ { 0x0040, 0x0003 }, -+ { 0x214c, 0x0003 }, -+ { 0x5a64, 0x0003 }, -+ }, -+ }, { -+ 340000000, { -+ { 0x0040, 0x0003 }, -+ { 0x3b4c, 0x0003 }, -+ { 0x5a64, 0x0003 }, -+ }, -+ }, { -+ 600000000, { -+ { 0x1a40, 0x0003 }, -+ { 0x3b4c, 0x0003 }, -+ { 0x5a64, 0x0003 }, -+ }, -+ }, { -+ ~0UL, { -+ { 0x0000, 0x0000 }, -+ { 0x0000, 0x0000 }, -+ { 0x0000, 0x0000 }, -+ }, -+ } -+}; -+ -+static const struct dw_hdmi_mpll_config rockchip_mpll_cfg_420[] = { -+ { -+ 30666000, { -+ { 0x00b7, 0x0000 }, -+ { 0x2157, 0x0000 }, -+ { 0x40f7, 0x0000 }, -+ }, -+ }, { -+ 92000000, { -+ { 0x00b7, 0x0000 }, -+ { 0x2143, 0x0001 }, -+ { 0x40a3, 0x0001 }, -+ }, -+ }, { -+ 184000000, { -+ { 0x0073, 0x0001 }, -+ { 0x2146, 0x0002 }, -+ { 0x4062, 0x0002 }, -+ }, -+ }, { -+ 340000000, { -+ { 0x0052, 0x0003 }, -+ { 0x214d, 0x0003 }, -+ { 0x4065, 0x0003 }, -+ }, -+ }, { -+ 600000000, { -+ { 0x0041, 0x0003 }, -+ { 0x3b4d, 0x0003 }, -+ { 0x5a65, 0x0003 }, -+ }, -+ }, { -+ ~0UL, { -+ { 0x0000, 0x0000 }, -+ { 0x0000, 0x0000 }, -+ { 0x0000, 0x0000 }, -+ }, -+ } -+}; -+ -+static const struct dw_hdmi_mpll_config rockchip_rk3288w_mpll_cfg_420[] = { -+ { -+ 30666000, { -+ { 0x00b7, 0x0000 }, -+ { 0x2157, 0x0000 }, -+ { 0x40f7, 0x0000 }, -+ }, -+ }, { -+ 92000000, { -+ { 0x00b7, 0x0000 }, -+ { 0x2143, 0x0001 }, -+ { 0x40a3, 0x0001 }, -+ }, -+ }, { -+ 184000000, { -+ { 0x0073, 0x0001 }, -+ { 0x2146, 0x0002 }, -+ { 0x4062, 0x0002 }, -+ }, -+ }, { -+ 340000000, { -+ { 0x0052, 0x0003 }, -+ { 0x214d, 0x0003 }, -+ { 0x4065, 0x0003 }, -+ }, -+ }, { -+ 600000000, { -+ { 0x0040, 0x0003 }, -+ { 0x3b4c, 0x0003 }, -+ { 0x5a65, 0x0003 }, - }, -- }, { -+ }, { - ~0UL, { -- { 0x00a0, 0x000a }, -- { 0x2001, 0x000f }, -- { 0x4002, 0x000f }, -+ { 0x0000, 0x0000 }, -+ { 0x0000, 0x0000 }, -+ { 0x0000, 0x0000 }, - }, - } - }; -@@ -172,20 +263,8 @@ static const struct dw_hdmi_mpll_config - static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { - /* pixelclk bpp8 bpp10 bpp12 */ - { -- 40000000, { 0x0018, 0x0018, 0x0018 }, -- }, { -- 65000000, { 0x0028, 0x0028, 0x0028 }, -- }, { -- 66000000, { 0x0038, 0x0038, 0x0038 }, -- }, { -- 74250000, { 0x0028, 0x0038, 0x0038 }, -- }, { -- 83500000, { 0x0028, 0x0038, 0x0038 }, -- }, { -- 146250000, { 0x0038, 0x0038, 0x0038 }, -- }, { -- 148500000, { 0x0000, 0x0038, 0x0038 }, -- }, { -+ 600000000, { 0x0000, 0x0000, 0x0000 }, -+ }, { - ~0UL, { 0x0000, 0x0000, 0x0000}, - } - }; -@@ -193,8 +272,9 @@ static const struct dw_hdmi_curr_ctrl ro - static const struct dw_hdmi_phy_config rockchip_phy_config[] = { - /*pixelclk symbol term vlev*/ - { 74250000, 0x8009, 0x0004, 0x0272}, -- { 148500000, 0x802b, 0x0004, 0x028d}, -+ { 165000000, 0x802b, 0x0004, 0x0209}, - { 297000000, 0x8039, 0x0005, 0x028d}, -+ { 594000000, 0x8039, 0x0000, 0x019d}, - { ~0UL, 0x0000, 0x0000, 0x0000} - }; - -@@ -245,45 +325,52 @@ dw_hdmi_rockchip_mode_valid(struct dw_hd - const struct drm_display_info *info, - const struct drm_display_mode *mode) - { -- const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg; -- int pclk = mode->clock * 1000; -- bool valid = false; -- int i; -+ struct dw_hdmi_plat_data *pdata = (struct dw_hdmi_plat_data *)data; -+ const struct dw_hdmi_mpll_config *mpll_cfg = pdata->mpll_cfg; -+ int clock = mode->clock; -+ unsigned int i = 0; - -- for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) { -- if (pclk == mpll_cfg[i].mpixelclock) { -- valid = true; -- break; -- } -+ if (pdata->ycbcr_420_allowed && drm_mode_is_420(info, mode) && -+ (info->color_formats & DRM_COLOR_FORMAT_YCBCR420)) { -+ clock /= 2; -+ mpll_cfg = pdata->mpll_cfg_420; - } - -- return (valid) ? MODE_OK : MODE_BAD; --} -+ if ((!mpll_cfg && clock > 340000) || -+ (info->max_tmds_clock && clock > info->max_tmds_clock)) -+ return MODE_CLOCK_HIGH; - --static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder) --{ --} -+ if (mpll_cfg) { -+ while ((clock * 1000) < mpll_cfg[i].mpixelclock && -+ mpll_cfg[i].mpixelclock != (~0UL)) -+ i++; - --static bool --dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder, -- const struct drm_display_mode *mode, -- struct drm_display_mode *adj_mode) --{ -- return true; --} -+ if (mpll_cfg[i].mpixelclock == (~0UL)) -+ return MODE_CLOCK_HIGH; -+ } - --static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder, -- struct drm_display_mode *mode, -- struct drm_display_mode *adj_mode) -+ return MODE_OK; -+} -+static void -+dw_hdmi_rockchip_bridge_mode_set(struct drm_bridge *bridge, -+ const struct drm_display_mode *mode, -+ const struct drm_display_mode *adjusted_mode) - { -- struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); -+ struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge); -+ struct drm_crtc_state *crtc_state = to_crtc_state(adjusted_mode); -+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); - -- clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000); -+ if (hdmi->phy) -+ phy_set_bus_width(hdmi->phy, s->bus_width); -+ -+ clk_set_rate(hdmi->ref_clk, adjusted_mode->clock * 1000); - } - --static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) -+static void dw_hdmi_rockchip_bridge_enable(struct drm_bridge *bridge) - { -- struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); -+ struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge); -+ struct drm_encoder *encoder = bridge->encoder; -+ - u32 val; - int ret; - -@@ -311,25 +398,143 @@ static void dw_hdmi_rockchip_encoder_ena - ret ? "LIT" : "BIG"); - } - -+static bool is_rgb(u32 format) -+{ -+ switch (format) { -+ case MEDIA_BUS_FMT_RGB888_1X24: -+ case MEDIA_BUS_FMT_RGB101010_1X30: -+ return true; -+ default: -+ return false; -+ } -+} -+ -+static bool is_yuv444(u32 format) -+{ -+ switch (format) { -+ case MEDIA_BUS_FMT_YUV10_1X30: -+ case MEDIA_BUS_FMT_YUV8_1X24: -+ return true; -+ default: -+ return false; -+ } -+} -+ -+static bool is_yuv420(u32 format) -+{ -+ switch (format) { -+ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: -+ case MEDIA_BUS_FMT_UYYVYY8_0_5X24: -+ return true; -+ default: -+ return false; -+ } -+} -+ -+static bool is_10bit(u32 format) -+{ -+ switch (format) { -+ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: -+ case MEDIA_BUS_FMT_RGB101010_1X30: -+ case MEDIA_BUS_FMT_YUV10_1X30: -+ return true; -+ default: -+ return false; -+ } -+} -+ - static int --dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder, -- struct drm_crtc_state *crtc_state, -- struct drm_connector_state *conn_state) -+dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state, -+ struct drm_crtc_state *crtc_state, -+ struct drm_connector_state *conn_state) - { - struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); -+ struct drm_atomic_state *state = bridge_state->base.state; -+ struct drm_crtc_state *old_crtc_state; -+ struct rockchip_crtc_state *old_state; -+ struct drm_bridge *next_bridge; -+ struct drm_bridge_state *next_bridge_state; -+ u32 format = bridge_state->output_bus_cfg.format; - - s->output_mode = ROCKCHIP_OUT_MODE_AAAA; - s->output_type = DRM_MODE_CONNECTOR_HDMIA; -+ s->output_bpc = 10; -+ s->bus_format = format; -+ -+ next_bridge = drm_bridge_get_next_bridge(bridge); -+ if (next_bridge) { -+ next_bridge_state = drm_atomic_get_new_bridge_state(state, -+ next_bridge); -+ format = next_bridge_state->output_bus_cfg.format; -+ } -+ -+ s->bus_width = is_10bit(format) ? 10 : 8; -+ -+ if (is_yuv420(format)) { -+ s->output_mode = ROCKCHIP_OUT_MODE_YUV420; -+ s->bus_width /= 2; -+ } -+ -+ old_crtc_state = drm_atomic_get_old_crtc_state(state, conn_state->crtc); -+ if (old_crtc_state && !crtc_state->mode_changed) { -+ old_state = to_rockchip_crtc_state(old_crtc_state); -+ if (s->bus_format != old_state->bus_format || -+ s->bus_width != old_state->bus_width) -+ crtc_state->mode_changed = true; -+ } - - return 0; - } - --static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = { -- .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup, -- .mode_set = dw_hdmi_rockchip_encoder_mode_set, -- .enable = dw_hdmi_rockchip_encoder_enable, -- .disable = dw_hdmi_rockchip_encoder_disable, -- .atomic_check = dw_hdmi_rockchip_encoder_atomic_check, -+static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state, -+ struct drm_crtc_state *crtc_state, -+ struct drm_connector_state *conn_state, -+ u32 output_fmt, -+ unsigned int *num_input_fmts) -+{ -+ struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge); -+ struct drm_encoder *encoder = bridge->encoder; -+ struct drm_connector *connector = conn_state->connector; -+ u32 *input_fmt; -+ bool has_10bit = true; -+ -+ *num_input_fmts = 0; -+ -+ if (drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder)) -+ has_10bit = false; -+ -+ if (!has_10bit && is_10bit(output_fmt)) -+ return NULL; -+ -+ if (is_yuv444(output_fmt)) { -+ if (!hdmi->chip_data->ycbcr_444_allowed) -+ return NULL; -+ } else if (is_yuv420(output_fmt)) { -+ if (!connector->ycbcr_420_allowed) -+ return NULL; -+ } else if (!is_rgb(output_fmt)) -+ return NULL; -+ -+ input_fmt = kzalloc(sizeof(*input_fmt), GFP_KERNEL); -+ if (!input_fmt) -+ return NULL; -+ -+ *num_input_fmts = 1; -+ *input_fmt = output_fmt; -+ -+ return input_fmt; -+} -+ -+static const struct drm_bridge_funcs dw_hdmi_rockchip_bridge_funcs = { -+ .mode_set = dw_hdmi_rockchip_bridge_mode_set, -+ .enable = dw_hdmi_rockchip_bridge_enable, -+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, -+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, -+ .atomic_get_input_bus_fmts = dw_hdmi_rockchip_get_input_bus_fmts, -+ .atomic_check = dw_hdmi_rockchip_bridge_atomic_check, -+ .atomic_reset = drm_atomic_helper_bridge_reset, - }; - - static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data, -@@ -338,6 +543,8 @@ static int dw_hdmi_rockchip_genphy_init( - { - struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; - -+ dw_hdmi_set_high_tmds_clock_ratio(dw_hdmi, display); -+ - return phy_power_on(hdmi->phy); - } - -@@ -422,17 +629,16 @@ static const struct dw_hdmi_phy_ops rk32 - - static struct rockchip_hdmi_chip_data rk3228_chip_data = { - .lcdsel_grf_reg = -1, -+ .ycbcr_444_allowed = true, - }; - - static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = { - .mode_valid = dw_hdmi_rockchip_mode_valid, -- .mpll_cfg = rockchip_mpll_cfg, -- .cur_ctr = rockchip_cur_ctr, -- .phy_config = rockchip_phy_config, - .phy_data = &rk3228_chip_data, - .phy_ops = &rk3228_hdmi_phy_ops, - .phy_name = "inno_dw_hdmi_phy2", - .phy_force_vendor = true, -+ .ycbcr_420_allowed = true, - }; - - static struct rockchip_hdmi_chip_data rk3288_chip_data = { -@@ -444,6 +650,7 @@ static struct rockchip_hdmi_chip_data rk - static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = { - .mode_valid = dw_hdmi_rockchip_mode_valid, - .mpll_cfg = rockchip_mpll_cfg, -+ .mpll_cfg_420 = rockchip_rk3288w_mpll_cfg_420, - .cur_ctr = rockchip_cur_ctr, - .phy_config = rockchip_phy_config, - .phy_data = &rk3288_chip_data, -@@ -459,18 +666,17 @@ static const struct dw_hdmi_phy_ops rk33 - - static struct rockchip_hdmi_chip_data rk3328_chip_data = { - .lcdsel_grf_reg = -1, -+ .ycbcr_444_allowed = true, - }; - - static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { - .mode_valid = dw_hdmi_rockchip_mode_valid, -- .mpll_cfg = rockchip_mpll_cfg, -- .cur_ctr = rockchip_cur_ctr, -- .phy_config = rockchip_phy_config, - .phy_data = &rk3328_chip_data, - .phy_ops = &rk3328_hdmi_phy_ops, - .phy_name = "inno_dw_hdmi_phy2", - .phy_force_vendor = true, - .use_drm_infoframe = true, -+ .ycbcr_420_allowed = true, - }; - - static struct rockchip_hdmi_chip_data rk3399_chip_data = { -@@ -482,6 +688,7 @@ static struct rockchip_hdmi_chip_data rk - static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = { - .mode_valid = dw_hdmi_rockchip_mode_valid, - .mpll_cfg = rockchip_mpll_cfg, -+ .mpll_cfg_420 = rockchip_mpll_cfg_420, - .cur_ctr = rockchip_cur_ctr, - .phy_config = rockchip_phy_config, - .phy_data = &rk3399_chip_data, -@@ -528,6 +735,7 @@ static int dw_hdmi_rockchip_bind(struct - struct dw_hdmi_plat_data *plat_data; - const struct of_device_id *match; - struct drm_device *drm = data; -+ struct drm_bridge *next_bridge; - struct drm_encoder *encoder; - struct rockchip_hdmi *hdmi; - int ret; -@@ -546,6 +754,7 @@ static int dw_hdmi_rockchip_bind(struct - return -ENOMEM; - - hdmi->dev = &pdev->dev; -+ plat_data->priv_data = plat_data; - hdmi->chip_data = plat_data->phy_data; - plat_data->phy_data = hdmi; - encoder = &hdmi->encoder.encoder; -@@ -574,7 +783,7 @@ static int dw_hdmi_rockchip_bind(struct - if (IS_ERR(hdmi->phy)) { - ret = PTR_ERR(hdmi->phy); - if (ret != -EPROBE_DEFER) -- DRM_DEV_ERROR(hdmi->dev, "failed to get phy\n"); -+ DRM_DEV_ERROR(hdmi->dev, "Failed to get phy: %d\n", ret); - return ret; - } - -@@ -605,15 +814,21 @@ static int dw_hdmi_rockchip_bind(struct - RK3568_HDMI_SCLIN_MSK)); - } - -- drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs); -- drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); -+ ret = drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); -+ if (ret) { -+ DRM_DEV_ERROR(hdmi->dev, "Failed to init encoder: %d\n", ret); -+ goto err_disable_clk; -+ } -+ -+ hdmi->bridge.funcs = &dw_hdmi_rockchip_bridge_funcs; -+ drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0); - - platform_set_drvdata(pdev, hdmi); - -- hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data); -+ hdmi->hdmi = dw_hdmi_probe(pdev, plat_data); - - /* -- * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(), -+ * If dw_hdmi_probe() fails we'll never call dw_hdmi_unbind(), - * which would have called the encoder cleanup. Do it manually. - */ - if (IS_ERR(hdmi->hdmi)) { -@@ -621,10 +836,26 @@ static int dw_hdmi_rockchip_bind(struct - goto err_bind; - } - -+ next_bridge = of_drm_find_bridge(pdev->dev.of_node); -+ if (!next_bridge) { -+ ret = -EPROBE_DEFER; -+ goto err_dw_hdmi_remove; -+ } -+ -+ ret = drm_bridge_attach(encoder, next_bridge, &hdmi->bridge, 0); -+ if (ret) { -+ if (ret != -EPROBE_DEFER) -+ DRM_DEV_ERROR(hdmi->dev, "Failed to attach dw-hdmi bridge: %d\n", ret); -+ goto err_dw_hdmi_remove; -+ } -+ - return 0; - -+err_dw_hdmi_remove: -+ dw_hdmi_remove(hdmi->hdmi); - err_bind: - drm_encoder_cleanup(encoder); -+err_disable_clk: - clk_disable_unprepare(hdmi->ref_clk); - err_clk: - regulator_disable(hdmi->avdd_1v8); -@@ -639,7 +870,7 @@ static void dw_hdmi_rockchip_unbind(stru - { - struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); - -- dw_hdmi_unbind(hdmi->hdmi); -+ dw_hdmi_remove(hdmi->hdmi); - drm_encoder_cleanup(&hdmi->encoder.encoder); - clk_disable_unprepare(hdmi->ref_clk); - -diff -rupN linux.orig/drivers/gpu/drm/rockchip/rockchip_drm_drv.h linux/drivers/gpu/drm/rockchip/rockchip_drm_drv.h ---- linux.orig/drivers/gpu/drm/rockchip/rockchip_drm_drv.h 2024-01-03 20:53:30.535323197 +0000 -+++ linux/drivers/gpu/drm/rockchip/rockchip_drm_drv.h 2024-01-03 21:17:09.402615966 +0000 -@@ -34,6 +34,7 @@ struct rockchip_crtc_state { - u32 bus_format; - u32 bus_flags; - int color_space; -+ int bus_width; - }; - #define to_rockchip_crtc_state(s) \ - container_of(s, struct rockchip_crtc_state, base) -diff -rupN linux.orig/drivers/gpu/drm/rockchip/rockchip_drm_fb.c linux/drivers/gpu/drm/rockchip/rockchip_drm_fb.c ---- linux.orig/drivers/gpu/drm/rockchip/rockchip_drm_fb.c 2024-01-03 20:53:30.539323252 +0000 -+++ linux/drivers/gpu/drm/rockchip/rockchip_drm_fb.c 2024-01-03 21:17:09.402615966 +0000 -@@ -133,6 +133,8 @@ void rockchip_drm_mode_config_init(struc - dev->mode_config.max_width = 4096; - dev->mode_config.max_height = 4096; - -+ dev->mode_config.normalize_zpos = true; -+ - dev->mode_config.funcs = &rockchip_drm_mode_config_funcs; - dev->mode_config.helper_private = &rockchip_mode_config_helpers; - -diff -rupN linux.orig/drivers/gpu/drm/rockchip/rockchip_drm_vop.c linux/drivers/gpu/drm/rockchip/rockchip_drm_vop.c ---- linux.orig/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 2024-01-03 20:53:30.539323252 +0000 -+++ linux/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 2024-01-03 21:17:09.402615966 +0000 -@@ -10,6 +10,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -281,6 +282,18 @@ static bool has_uv_swapped(uint32_t form - } - } - -+static bool is_fmt_10(uint32_t format) -+{ -+ switch (format) { -+ case DRM_FORMAT_NV15: -+ case DRM_FORMAT_NV20: -+ case DRM_FORMAT_NV30: -+ return true; -+ default: -+ return false; -+ } -+} -+ - static enum vop_data_format vop_convert_format(uint32_t format) - { - switch (format) { -@@ -296,12 +309,15 @@ static enum vop_data_format vop_convert_ - case DRM_FORMAT_BGR565: - return VOP_FMT_RGB565; - case DRM_FORMAT_NV12: -+ case DRM_FORMAT_NV15: - case DRM_FORMAT_NV21: - return VOP_FMT_YUV420SP; - case DRM_FORMAT_NV16: -+ case DRM_FORMAT_NV20: - case DRM_FORMAT_NV61: - return VOP_FMT_YUV422SP; - case DRM_FORMAT_NV24: -+ case DRM_FORMAT_NV30: - case DRM_FORMAT_NV42: - return VOP_FMT_YUV444SP; - default: -@@ -333,6 +349,30 @@ static int vop_convert_afbc_format(uint3 - return -EINVAL; - } - -+static bool is_yuv_output(uint32_t bus_format) -+{ -+ switch (bus_format) { -+ case MEDIA_BUS_FMT_YUV8_1X24: -+ case MEDIA_BUS_FMT_YUV10_1X30: -+ case MEDIA_BUS_FMT_UYYVYY8_0_5X24: -+ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: -+ return true; -+ default: -+ return false; -+ } -+} -+ -+static bool bus_fmt_has_uv_swapped(uint32_t bus_format) -+{ -+ switch (bus_format) { -+ case MEDIA_BUS_FMT_YUV8_1X24: -+ case MEDIA_BUS_FMT_YUV10_1X30: -+ return true; -+ default: -+ return false; -+ } -+} -+ - static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, - uint32_t dst, bool is_horizontal, - int vsu_mode, int *vskiplines) -@@ -385,8 +425,8 @@ static void scl_vop_cal_scl_fac(struct v - if (info->is_yuv) - is_yuv = true; - -- if (dst_w > 3840) { -- DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); -+ if (dst_w > 4096) { -+ DRM_DEV_ERROR(vop->dev, "Maximum dst width (4096) exceeded\n"); - return; - } - -@@ -927,6 +967,7 @@ static void vop_plane_atomic_update(stru - int format; - int is_yuv = fb->format->is_yuv; - int i; -+ int skiplines = 0; - - /* - * can't update plane when vop is disabled. -@@ -945,8 +986,14 @@ static void vop_plane_atomic_update(stru - obj = fb->obj[0]; - rk_obj = to_rockchip_obj(obj); - -+ /* -+ * Force skip lines when image is yuv and 3840 width, -+ * fixes a "jumping" green lines issue on RK3328. -+ */ - actual_w = drm_rect_width(src) >> 16; -- actual_h = drm_rect_height(src) >> 16; -+ if (actual_w == 3840 && is_yuv) -+ skiplines = 1; -+ actual_h = drm_rect_height(src) >> (16 + skiplines); - act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); - - dsp_info = (drm_rect_height(dest) - 1) << 16; -@@ -956,7 +1003,12 @@ static void vop_plane_atomic_update(stru - dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; - dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); - -- offset = (src->x1 >> 16) * fb->format->cpp[0]; -+ if (fb->format->block_w[0]) -+ offset = (src->x1 >> 16) * fb->format->char_per_block[0] / -+ fb->format->block_w[0]; -+ else -+ offset = (src->x1 >> 16) * fb->format->cpp[0]; -+ - offset += (src->y1 >> 16) * fb->pitches[0]; - dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; - -@@ -982,7 +1034,8 @@ static void vop_plane_atomic_update(stru - } - - VOP_WIN_SET(vop, win, format, format); -- VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); -+ VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format)); -+ VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4 >> skiplines)); - VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); - VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); - VOP_WIN_SET(vop, win, y_mir_en, -@@ -998,11 +1051,15 @@ static void vop_plane_atomic_update(stru - uv_obj = fb->obj[1]; - rk_uv_obj = to_rockchip_obj(uv_obj); - -- offset = (src->x1 >> 16) * bpp / hsub; -+ if (fb->format->block_w[1]) -+ offset = (src->x1 >> 16) * bpp / -+ fb->format->block_w[1] / hsub; -+ else -+ offset = (src->x1 >> 16) * bpp / hsub; - offset += (src->y1 >> 16) * fb->pitches[1] / vsub; - - dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; -- VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); -+ VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4 >> skiplines)); - VOP_WIN_SET(vop, win, uv_mst, dma_addr); - - for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) { -@@ -1183,6 +1240,79 @@ static void vop_crtc_disable_vblank(stru - spin_unlock_irqrestore(&vop->irq_lock, flags); - } - -+static bool vop_crtc_is_tmds(struct drm_crtc *crtc) -+{ -+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); -+ struct drm_encoder *encoder; -+ -+ switch (s->output_type) { -+ case DRM_MODE_CONNECTOR_LVDS: -+ case DRM_MODE_CONNECTOR_DSI: -+ return false; -+ case DRM_MODE_CONNECTOR_eDP: -+ case DRM_MODE_CONNECTOR_HDMIA: -+ case DRM_MODE_CONNECTOR_DisplayPort: -+ return true; -+ } -+ -+ drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) -+ if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) -+ return true; -+ -+ return false; -+} -+ -+static enum drm_mode_status vop_crtc_size_valid(struct drm_crtc *crtc, -+ const struct drm_display_mode *mode) -+{ -+ struct vop *vop = to_vop(crtc); -+ const struct vop_rect *max_output = &vop->data->max_output; -+ -+ if (max_output->width && max_output->height) { -+ /* only the size of the resulting rect matters */ -+ if(drm_mode_validate_size(mode, max_output->width, -+ max_output->height) != MODE_OK) { -+ return drm_mode_validate_size(mode, max_output->height, -+ max_output->width); -+ } -+ } -+ -+ return MODE_OK; -+} -+ -+/* -+ * The VESA DMT standard specifies a 0.5% pixel clock frequency tolerance. -+ * The CVT spec reuses that tolerance in its examples. -+ */ -+#define CLOCK_TOLERANCE_PER_MILLE 5 -+ -+static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, -+ const struct drm_display_mode *mode) -+{ -+ struct vop *vop = to_vop(crtc); -+ long rounded_rate; -+ long lowest, highest; -+ -+ if (mode->flags & DRM_MODE_FLAG_INTERLACE) -+ return MODE_NO_INTERLACE; -+ -+ if (vop_crtc_is_tmds(crtc)) { -+ rounded_rate = clk_round_rate(vop->dclk, mode->clock * 1000 + 999); -+ if (rounded_rate < 0) -+ return MODE_NOCLOCK; -+ -+ lowest = mode->clock * (1000 - CLOCK_TOLERANCE_PER_MILLE); -+ if (rounded_rate < lowest) -+ return MODE_CLOCK_LOW; -+ -+ highest = mode->clock * (1000 + CLOCK_TOLERANCE_PER_MILLE); -+ if (rounded_rate > highest) -+ return MODE_CLOCK_HIGH; -+ } -+ -+ return vop_crtc_size_valid(crtc, mode); -+} -+ - static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, - const struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) -@@ -1190,6 +1320,9 @@ static bool vop_crtc_mode_fixup(struct d - struct vop *vop = to_vop(crtc); - unsigned long rate; - -+ if (vop_crtc_size_valid(crtc, adjusted_mode) != MODE_OK) -+ return false; -+ - /* - * Clock craziness. - * -@@ -1356,6 +1489,7 @@ static void vop_crtc_atomic_enable(struc - u16 vact_end = vact_st + vdisplay; - uint32_t pin_pol, val; - int dither_bpc = s->output_bpc ? s->output_bpc : 10; -+ bool yuv_output = is_yuv_output(s->bus_format); - int ret; - - if (old_state && old_state->self_refresh_active) { -@@ -1421,6 +1555,8 @@ static void vop_crtc_atomic_enable(struc - !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) - s->output_mode = ROCKCHIP_OUT_MODE_P888; - -+ VOP_REG_SET(vop, common, dsp_data_swap, bus_fmt_has_uv_swapped(s->bus_format) ? 2 : 0); -+ - if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) - VOP_REG_SET(vop, common, pre_dither_down, 1); - else -@@ -1436,6 +1572,24 @@ static void vop_crtc_atomic_enable(struc - - VOP_REG_SET(vop, common, out_mode, s->output_mode); - -+ VOP_REG_SET(vop, common, dclk_ddr, -+ s->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0); -+ -+ VOP_REG_SET(vop, common, overlay_mode, yuv_output); -+ VOP_REG_SET(vop, common, dsp_out_yuv, yuv_output); -+ -+ /* -+ * Background color is 10bit depth if vop version >= 3.5 -+ */ -+ if (!yuv_output) -+ val = 0; -+ else if (VOP_MAJOR(vop_data->version) == 3 && -+ VOP_MINOR(vop_data->version) >= 5) -+ val = 0x20010200; -+ else -+ val = 0x801080; -+ VOP_REG_SET(vop, common, dsp_background, val); -+ - VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); - val = hact_st << 16; - val |= hact_end; -@@ -1594,6 +1748,7 @@ static void vop_crtc_atomic_flush(struct - } - - static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { -+ .mode_valid = vop_crtc_mode_valid, - .mode_fixup = vop_crtc_mode_fixup, - .atomic_check = vop_crtc_atomic_check, - .atomic_begin = vop_crtc_atomic_begin, -@@ -1817,8 +1972,23 @@ out: - return ret; - } - --static void vop_plane_add_properties(struct drm_plane *plane, -- const struct vop_win_data *win_data) -+static bool plane_supports_yuv_format(const struct drm_plane *plane) -+{ -+ const struct drm_format_info *info; -+ int i; -+ -+ for (i = 0; i < plane->format_count; i++) { -+ info = drm_format_info(plane->format_types[i]); -+ if (info->is_yuv) -+ return true; -+ } -+ -+ return false; -+} -+ -+static void vop_plane_add_properties(struct drm_plane *plane, int zpos, -+ const struct vop_win_data *win_data, -+ const struct vop_data *vop_data) - { - unsigned int flags = 0; - -@@ -1827,6 +1997,21 @@ static void vop_plane_add_properties(str - if (flags) - drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, - DRM_MODE_ROTATE_0 | flags); -+ -+ drm_plane_create_zpos_immutable_property(plane, zpos); -+ -+ if (!plane_supports_yuv_format(plane)) -+ return; -+ -+ flags = BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709); -+ if (vop_data->feature & VOP_FEATURE_OUTPUT_RGB10) -+ flags |= BIT(DRM_COLOR_YCBCR_BT2020); -+ -+ drm_plane_create_color_properties(plane, flags, -+ BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | -+ BIT(DRM_COLOR_YCBCR_FULL_RANGE), -+ DRM_COLOR_YCBCR_BT601, -+ DRM_COLOR_YCBCR_LIMITED_RANGE); - } - - static int vop_create_crtc(struct vop *vop) -@@ -1840,19 +2025,10 @@ static int vop_create_crtc(struct vop *v - int ret; - int i; - -- /* -- * Create drm_plane for primary and cursor planes first, since we need -- * to pass them to drm_crtc_init_with_planes, which sets the -- * "possible_crtcs" to the newly initialized crtc. -- */ - for (i = 0; i < vop_data->win_size; i++) { - struct vop_win *vop_win = &vop->win[i]; - const struct vop_win_data *win_data = vop_win->data; - -- if (win_data->type != DRM_PLANE_TYPE_PRIMARY && -- win_data->type != DRM_PLANE_TYPE_CURSOR) -- continue; -- - ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, - 0, &vop_plane_funcs, - win_data->phy->data_formats, -@@ -1867,7 +2043,7 @@ static int vop_create_crtc(struct vop *v - - plane = &vop_win->base; - drm_plane_helper_add(plane, &plane_helper_funcs); -- vop_plane_add_properties(plane, win_data); -+ vop_plane_add_properties(plane, i, win_data, vop_data); - if (plane->type == DRM_PLANE_TYPE_PRIMARY) - primary = plane; - else if (plane->type == DRM_PLANE_TYPE_CURSOR) -@@ -1885,32 +2061,13 @@ static int vop_create_crtc(struct vop *v - drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size); - } - -- /* -- * Create drm_planes for overlay windows with possible_crtcs restricted -- * to the newly created crtc. -- */ -+ /* Set possible_crtcs to the newly created crtc for overlay windows */ - for (i = 0; i < vop_data->win_size; i++) { - struct vop_win *vop_win = &vop->win[i]; -- const struct vop_win_data *win_data = vop_win->data; -- unsigned long possible_crtcs = drm_crtc_mask(crtc); -- -- if (win_data->type != DRM_PLANE_TYPE_OVERLAY) -- continue; - -- ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, -- possible_crtcs, -- &vop_plane_funcs, -- win_data->phy->data_formats, -- win_data->phy->nformats, -- win_data->phy->format_modifiers, -- win_data->type, NULL); -- if (ret) { -- DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", -- ret); -- goto err_cleanup_crtc; -- } -- drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); -- vop_plane_add_properties(&vop_win->base, win_data); -+ plane = &vop_win->base; -+ if (plane->type == DRM_PLANE_TYPE_OVERLAY) -+ plane->possible_crtcs = drm_crtc_mask(crtc); - } - - port = of_get_child_by_name(dev->of_node, "port"); -diff -rupN linux.orig/drivers/gpu/drm/rockchip/rockchip_drm_vop.h linux/drivers/gpu/drm/rockchip/rockchip_drm_vop.h ---- linux.orig/drivers/gpu/drm/rockchip/rockchip_drm_vop.h 2024-01-03 20:53:30.539323252 +0000 -+++ linux/drivers/gpu/drm/rockchip/rockchip_drm_vop.h 2024-01-03 21:17:09.402615966 +0000 -@@ -119,10 +119,17 @@ struct vop_common { - struct vop_reg mmu_en; - struct vop_reg out_mode; - struct vop_reg standby; -+ -+ struct vop_reg overlay_mode; -+ struct vop_reg dclk_ddr; -+ struct vop_reg dsp_data_swap; -+ struct vop_reg dsp_out_yuv; -+ struct vop_reg dsp_background; - }; - - struct vop_misc { - struct vop_reg global_regdone_en; -+ struct vop_reg win_channel[4]; - }; - - struct vop_intr { -@@ -181,6 +188,7 @@ struct vop_win_phy { - struct vop_reg enable; - struct vop_reg gate; - struct vop_reg format; -+ struct vop_reg fmt_10; - struct vop_reg rb_swap; - struct vop_reg uv_swap; - struct vop_reg act_info; -@@ -213,6 +221,11 @@ struct vop_win_data { - enum drm_plane_type type; - }; - -+struct vop_rect { -+ int width; -+ int height; -+}; -+ - struct vop_data { - uint32_t version; - const struct vop_intr *intr; -@@ -225,6 +238,7 @@ struct vop_data { - const struct vop_win_data *win; - unsigned int win_size; - unsigned int lut_size; -+ struct vop_rect max_output; - - #define VOP_FEATURE_OUTPUT_RGB10 BIT(0) - #define VOP_FEATURE_INTERNAL_RGB BIT(1) -@@ -273,11 +287,12 @@ struct vop_data { - /* - * display output interface supported by rockchip lcdc - */ --#define ROCKCHIP_OUT_MODE_P888 0 --#define ROCKCHIP_OUT_MODE_P666 1 --#define ROCKCHIP_OUT_MODE_P565 2 -+#define ROCKCHIP_OUT_MODE_P888 0 -+#define ROCKCHIP_OUT_MODE_P666 1 -+#define ROCKCHIP_OUT_MODE_P565 2 -+#define ROCKCHIP_OUT_MODE_YUV420 14 - /* for use special outface */ --#define ROCKCHIP_OUT_MODE_AAAA 15 -+#define ROCKCHIP_OUT_MODE_AAAA 15 - - /* output flags */ - #define ROCKCHIP_OUTPUT_DSI_DUAL BIT(0) -diff -rupN linux.orig/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h linux/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h ---- linux.orig/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h 2024-01-03 20:53:30.539323252 +0000 -+++ linux/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h 2024-01-03 21:17:09.398615878 +0000 -@@ -27,11 +27,6 @@ enum win_dly_mode { - VOP2_DLY_MODE_MAX, - }; - --struct vop_rect { -- int width; -- int height; --}; -- - enum vop2_scale_up_mode { - VOP2_SCALE_UP_NRST_NBOR, - VOP2_SCALE_UP_BIL, -diff -rupN linux.orig/drivers/gpu/drm/rockchip/rockchip_vop_reg.c linux/drivers/gpu/drm/rockchip/rockchip_vop_reg.c ---- linux.orig/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 2024-01-03 20:53:30.539323252 +0000 -+++ linux/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 2024-01-03 21:17:09.402615966 +0000 -@@ -53,6 +53,23 @@ static const uint32_t formats_win_full[] - DRM_FORMAT_NV42, - }; - -+static const uint32_t formats_win_full_10[] = { -+ DRM_FORMAT_XRGB8888, -+ DRM_FORMAT_ARGB8888, -+ DRM_FORMAT_XBGR8888, -+ DRM_FORMAT_ABGR8888, -+ DRM_FORMAT_RGB888, -+ DRM_FORMAT_BGR888, -+ DRM_FORMAT_RGB565, -+ DRM_FORMAT_BGR565, -+ DRM_FORMAT_NV12, -+ DRM_FORMAT_NV16, -+ DRM_FORMAT_NV24, -+ DRM_FORMAT_NV15, -+ DRM_FORMAT_NV20, -+ DRM_FORMAT_NV30, -+}; -+ - static const uint64_t format_modifiers_win_full[] = { - DRM_FORMAT_MOD_LINEAR, - DRM_FORMAT_MOD_INVALID, -@@ -621,11 +638,12 @@ static const struct vop_scl_regs rk3288_ - - static const struct vop_win_phy rk3288_win01_data = { - .scl = &rk3288_win_full_scl, -- .data_formats = formats_win_full, -- .nformats = ARRAY_SIZE(formats_win_full), -+ .data_formats = formats_win_full_10, -+ .nformats = ARRAY_SIZE(formats_win_full_10), - .format_modifiers = format_modifiers_win_full, - .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0), - .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1), -+ .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4), - .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), - .uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15), - .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), -@@ -687,6 +705,12 @@ static const struct vop_common rk3288_co - .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18), - .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0), - .cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0), -+ -+ .overlay_mode = VOP_REG(RK3288_SYS_CTRL, 0x1, 16), -+ .dclk_ddr = VOP_REG(RK3288_DSP_CTRL0, 0x1, 8), -+ .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12), -+ .dsp_out_yuv = VOP_REG(RK3288_POST_SCL_CTRL, 0x1, 2), -+ .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0), - }; - - /* -@@ -722,9 +746,23 @@ static const struct vop_intr rk3288_vop_ - .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8), - }; - --static const struct vop_data rk3288_vop = { -+static const struct vop_data rk3288_vop_big = { - .version = VOP_VERSION(3, 1), - .feature = VOP_FEATURE_OUTPUT_RGB10, -+ .max_output = { 3840, 2160 }, -+ .intr = &rk3288_vop_intr, -+ .common = &rk3288_common, -+ .modeset = &rk3288_modeset, -+ .output = &rk3288_output, -+ .win = rk3288_vop_win_data, -+ .win_size = ARRAY_SIZE(rk3288_vop_win_data), -+ .lut_size = 1024, -+}; -+ -+static const struct vop_data rk3288_vop_lit = { -+ .version = VOP_VERSION(3, 1), -+ .feature = VOP_FEATURE_OUTPUT_RGB10, -+ .max_output = { 2560, 1600 }, - .intr = &rk3288_vop_intr, - .common = &rk3288_common, - .modeset = &rk3288_modeset, -@@ -756,11 +794,12 @@ static const struct vop_intr rk3368_vop_ - - static const struct vop_win_phy rk3368_win01_data = { - .scl = &rk3288_win_full_scl, -- .data_formats = formats_win_full, -- .nformats = ARRAY_SIZE(formats_win_full), -+ .data_formats = formats_win_full_10, -+ .nformats = ARRAY_SIZE(formats_win_full_10), - .format_modifiers = format_modifiers_win_full, - .enable = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 0), - .format = VOP_REG(RK3368_WIN0_CTRL0, 0x7, 1), -+ .fmt_10 = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 4), - .rb_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 12), - .uv_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 15), - .x_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 21), -@@ -826,6 +865,7 @@ static const struct vop_misc rk3368_misc - - static const struct vop_data rk3368_vop = { - .version = VOP_VERSION(3, 2), -+ .max_output = { 4096, 2160 }, - .intr = &rk3368_vop_intr, - .common = &rk3288_common, - .modeset = &rk3288_modeset, -@@ -847,6 +887,7 @@ static const struct vop_intr rk3366_vop_ - - static const struct vop_data rk3366_vop = { - .version = VOP_VERSION(3, 4), -+ .max_output = { 4096, 2160 }, - .intr = &rk3366_vop_intr, - .common = &rk3288_common, - .modeset = &rk3288_modeset, -@@ -891,6 +932,11 @@ static const struct vop_common rk3399_co - .dsp_blank = VOP_REG(RK3399_DSP_CTRL0, 0x3, 18), - .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0), - .cfg_done = VOP_REG_SYNC(RK3399_REG_CFG_DONE, 0x1, 0), -+ -+ .overlay_mode = VOP_REG(RK3399_SYS_CTRL, 0x1, 16), -+ .dsp_data_swap = VOP_REG(RK3399_DSP_CTRL0, 0x1f, 12), -+ .dsp_out_yuv = VOP_REG(RK3288_POST_SCL_CTRL, 0x1, 2), -+ .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0), - }; - - static const struct vop_yuv2yuv_phy rk3399_yuv2yuv_win01_data = { -@@ -924,11 +970,12 @@ static const struct vop_win_yuv2yuv_data - - static const struct vop_win_phy rk3399_win01_data = { - .scl = &rk3288_win_full_scl, -- .data_formats = formats_win_full, -- .nformats = ARRAY_SIZE(formats_win_full), -+ .data_formats = formats_win_full_10, -+ .nformats = ARRAY_SIZE(formats_win_full_10), - .format_modifiers = format_modifiers_win_full_afbc, - .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0), - .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1), -+ .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4), - .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), - .uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15), - .x_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 21), -@@ -974,6 +1021,7 @@ static const struct vop_afbc rk3399_vop_ - static const struct vop_data rk3399_vop_big = { - .version = VOP_VERSION(3, 5), - .feature = VOP_FEATURE_OUTPUT_RGB10, -+ .max_output = { 4096, 2160 }, - .intr = &rk3366_vop_intr, - .common = &rk3399_common, - .modeset = &rk3288_modeset, -@@ -1001,6 +1049,7 @@ static const struct vop_win_yuv2yuv_data - - static const struct vop_data rk3399_vop_lit = { - .version = VOP_VERSION(3, 6), -+ .max_output = { 2560, 1600 }, - .intr = &rk3366_vop_intr, - .common = &rk3399_common, - .modeset = &rk3288_modeset, -@@ -1022,6 +1071,7 @@ static const struct vop_win_data rk3228_ - static const struct vop_data rk3228_vop = { - .version = VOP_VERSION(3, 7), - .feature = VOP_FEATURE_OUTPUT_RGB10, -+ .max_output = { 4096, 2160 }, - .intr = &rk3366_vop_intr, - .common = &rk3288_common, - .modeset = &rk3288_modeset, -@@ -1057,6 +1107,10 @@ static const struct vop_output rk3328_ou - - static const struct vop_misc rk3328_misc = { - .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11), -+ -+ .win_channel[0] = VOP_REG(RK3328_WIN0_CTRL2, 0xff, 0), -+ .win_channel[1] = VOP_REG(RK3328_WIN1_CTRL2, 0xff, 0), -+ .win_channel[2] = VOP_REG(RK3328_WIN2_CTRL2, 0xff, 0), - }; - - static const struct vop_common rk3328_common = { -@@ -1069,6 +1123,12 @@ static const struct vop_common rk3328_co - .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18), - .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0), - .cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0), -+ -+ .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16), -+ .dclk_ddr = VOP_REG(RK3328_DSP_CTRL0, 0x1, 8), -+ .dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12), -+ .dsp_out_yuv = VOP_REG(RK3328_POST_SCL_CTRL, 0x1, 2), -+ .dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0), - }; - - static const struct vop_intr rk3328_vop_intr = { -@@ -1093,6 +1153,7 @@ static const struct vop_win_data rk3328_ - static const struct vop_data rk3328_vop = { - .version = VOP_VERSION(3, 8), - .feature = VOP_FEATURE_OUTPUT_RGB10, -+ .max_output = { 4096, 2160 }, - .intr = &rk3328_vop_intr, - .common = &rk3328_common, - .modeset = &rk3328_modeset, -@@ -1115,8 +1176,10 @@ static const struct of_device_id vop_dri - .data = &rk3066_vop }, - { .compatible = "rockchip,rk3188-vop", - .data = &rk3188_vop }, -- { .compatible = "rockchip,rk3288-vop", -- .data = &rk3288_vop }, -+ { .compatible = "rockchip,rk3288-vop-big", -+ .data = &rk3288_vop_big }, -+ { .compatible = "rockchip,rk3288-vop-lit", -+ .data = &rk3288_vop_lit }, - { .compatible = "rockchip,rk3368-vop", - .data = &rk3368_vop }, - { .compatible = "rockchip,rk3366-vop", -diff -rupN linux.orig/drivers/media/cec/core/cec-adap.c linux/drivers/media/cec/core/cec-adap.c ---- linux.orig/drivers/media/cec/core/cec-adap.c 2024-01-03 20:53:30.727325791 +0000 -+++ linux/drivers/media/cec/core/cec-adap.c 2024-01-03 21:17:09.402615966 +0000 -@@ -1679,8 +1679,15 @@ void cec_s_phys_addr(struct cec_adapter - if (IS_ERR_OR_NULL(adap)) - return; - -+ cancel_delayed_work_sync(&adap->debounce_work); -+ - mutex_lock(&adap->lock); -- __cec_s_phys_addr(adap, phys_addr, block); -+ if (cec_debounce_ms > 0 && !block && phys_addr == CEC_PHYS_ADDR_INVALID && -+ adap->phys_addr != phys_addr) -+ schedule_delayed_work(&adap->debounce_work, -+ msecs_to_jiffies(cec_debounce_ms)); -+ else -+ __cec_s_phys_addr(adap, phys_addr, block); - mutex_unlock(&adap->lock); - } - EXPORT_SYMBOL_GPL(cec_s_phys_addr); -diff -rupN linux.orig/drivers/media/cec/core/cec-core.c linux/drivers/media/cec/core/cec-core.c ---- linux.orig/drivers/media/cec/core/cec-core.c 2024-01-03 20:53:30.727325791 +0000 -+++ linux/drivers/media/cec/core/cec-core.c 2024-01-03 21:17:09.402615966 +0000 -@@ -40,6 +40,10 @@ static bool debug_phys_addr; - module_param(debug_phys_addr, bool, 0644); - MODULE_PARM_DESC(debug_phys_addr, "add CEC_CAP_PHYS_ADDR if set"); - -+int cec_debounce_ms; -+module_param_named(debounce_ms, cec_debounce_ms, int, 0644); -+MODULE_PARM_DESC(debounce_ms, "debounce invalid phys addr"); -+ - static dev_t cec_dev_t; - - /* Active devices */ -@@ -188,6 +192,8 @@ static void cec_devnode_unregister(struc - - mutex_unlock(&devnode->lock); - -+ cancel_delayed_work_sync(&adap->debounce_work); -+ - mutex_lock(&adap->lock); - __cec_s_phys_addr(adap, CEC_PHYS_ADDR_INVALID, false); - __cec_s_log_addrs(adap, NULL, false); -@@ -248,6 +254,17 @@ static const struct file_operations cec_ - }; - #endif - -+static void cec_s_phys_addr_debounce(struct work_struct *work) -+{ -+ struct delayed_work *delayed_work = to_delayed_work(work); -+ struct cec_adapter *adap = -+ container_of(delayed_work, struct cec_adapter, debounce_work); -+ -+ mutex_lock(&adap->lock); -+ __cec_s_phys_addr(adap, CEC_PHYS_ADDR_INVALID, false); -+ mutex_unlock(&adap->lock); -+} -+ - struct cec_adapter *cec_allocate_adapter(const struct cec_adap_ops *ops, - void *priv, const char *name, u32 caps, - u8 available_las) -@@ -285,6 +302,7 @@ struct cec_adapter *cec_allocate_adapter - INIT_LIST_HEAD(&adap->transmit_queue); - INIT_LIST_HEAD(&adap->wait_queue); - init_waitqueue_head(&adap->kthread_waitq); -+ INIT_DELAYED_WORK(&adap->debounce_work, cec_s_phys_addr_debounce); - - /* adap->devnode initialization */ - INIT_LIST_HEAD(&adap->devnode.fhs); -diff -rupN linux.orig/drivers/media/cec/core/cec-priv.h linux/drivers/media/cec/core/cec-priv.h ---- linux.orig/drivers/media/cec/core/cec-priv.h 2024-01-03 20:53:30.727325791 +0000 -+++ linux/drivers/media/cec/core/cec-priv.h 2024-01-03 21:17:09.402615966 +0000 -@@ -37,6 +37,7 @@ static inline bool msg_is_raw(const stru - - /* cec-core.c */ - extern int cec_debug; -+extern int cec_debounce_ms; - int cec_get_device(struct cec_devnode *devnode); - void cec_put_device(struct cec_devnode *devnode); - -diff -rupN linux.orig/drivers/media/platform/rockchip/Kconfig linux/drivers/media/platform/rockchip/Kconfig ---- linux.orig/drivers/media/platform/rockchip/Kconfig 2024-01-03 20:53:30.799326767 +0000 -+++ linux/drivers/media/platform/rockchip/Kconfig 2024-01-03 21:28:43.674043912 +0000 -@@ -2,5 +2,6 @@ - - comment "Rockchip media platform drivers" - -+source "drivers/media/platform/rockchip/iep/Kconfig" - source "drivers/media/platform/rockchip/rga/Kconfig" - source "drivers/media/platform/rockchip/rkisp1/Kconfig" -diff -rupN linux.orig/drivers/media/platform/rockchip/Makefile linux/drivers/media/platform/rockchip/Makefile ---- linux.orig/drivers/media/platform/rockchip/Makefile 2024-01-03 20:53:30.799326767 +0000 -+++ linux/drivers/media/platform/rockchip/Makefile 2024-01-03 21:28:43.674043912 +0000 -@@ -1,3 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0-only -+obj-y += iep/ - obj-y += rga/ - obj-y += rkisp1/ -diff -rupN linux.orig/drivers/media/platform/rockchip/iep/Kconfig linux/drivers/media/platform/rockchip/iep/Kconfig ---- linux.orig/drivers/media/platform/rockchip/iep/Kconfig 1970-01-01 00:00:00.000000000 +0000 -+++ linux/drivers/media/platform/rockchip/iep/Kconfig 2024-01-03 21:28:43.674043912 +0000 -@@ -0,0 +1,16 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+config VIDEO_ROCKCHIP_IEP -+ tristate "Rockchip Image Enhancement Processor" -+ depends on V4L_MEM2MEM_DRIVERS -+ depends on VIDEO_DEV -+ depends on ARCH_ROCKCHIP || COMPILE_TEST -+ select VIDEOBUF2_DMA_CONTIG -+ select V4L2_MEM2MEM_DEV -+ help -+ This is a v4l2 driver for Rockchip Image Enhancement Processor (IEP) -+ found in most Rockchip RK3xxx SoCs. -+ Rockchip IEP supports various enhancement operations for RGB and YUV -+ images. The driver currently implements YUV deinterlacing only. -+ To compile this driver as a module, choose M here: the module -+ will be called rockchip-iep -diff -rupN linux.orig/drivers/media/platform/rockchip/iep/Makefile linux/drivers/media/platform/rockchip/iep/Makefile ---- linux.orig/drivers/media/platform/rockchip/iep/Makefile 1970-01-01 00:00:00.000000000 +0000 -+++ linux/drivers/media/platform/rockchip/iep/Makefile 2024-01-03 21:28:43.674043912 +0000 -@@ -0,0 +1,5 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+rockchip-iep-objs := iep.o -+ -+obj-$(CONFIG_VIDEO_ROCKCHIP_IEP) += rockchip-iep.o -diff -rupN linux.orig/drivers/media/platform/rockchip/iep/iep-regs.h linux/drivers/media/platform/rockchip/iep/iep-regs.h ---- linux.orig/drivers/media/platform/rockchip/iep/iep-regs.h 1970-01-01 00:00:00.000000000 +0000 -+++ linux/drivers/media/platform/rockchip/iep/iep-regs.h 2024-01-03 21:28:43.674043912 +0000 -@@ -0,0 +1,291 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Rockchip Image Enhancement Processor (IEP) driver -+ * -+ * Copyright (C) 2020 Alex Bee -+ * -+ */ -+ -+#ifndef __IEP_REGS_H__ -+#define __IEP_REGS_H__ -+ -+/* IEP Registers addresses */ -+#define IEP_CONFIG0 0x000 /* Configuration register0 */ -+#define IEP_VOP_DIRECT_PATH BIT(0) -+#define IEP_DEIN_HIGH_FREQ_SHFT 1 -+#define IEP_DEIN_HIGH_FREQ_MASK (0x7f << IEP_DEIN_HIGH_FREQ_SHFT) -+#define IEP_DEIN_MODE_SHFT 8 -+#define IEP_DEIN_MODE_MASK (7 << IEP_DEIN_MODE_SHFT) -+#define IEP_DEIN_HIGH_FREQ_EN BIT(11) -+#define IEP_DEIN_EDGE_INTPOL_EN BIT(12) -+#define IEP_YUV_DENOISE_EN BIT(13) -+#define IEP_YUV_ENHNC_EN BIT(14) -+#define IEP_DEIN_EDGE_INTPOL_SMTH_EN BIT(15) -+#define IEP_RGB_CLR_ENHNC_EN BIT(16) -+#define IEP_RGB_CNTRST_ENHNC_EN BIT(17) -+#define IEP_RGB_ENHNC_MODE_BYPASS (0 << 18) -+#define IEP_RGB_ENHNC_MODE_DNS BIT(18) -+#define IEP_RGB_ENHNC_MODE_DTL (2 << 18) -+#define IEP_RGB_ENHNC_MODE_EDG (3 << 18) -+#define IEP_RGB_ENHNC_MODE_MASK (3 << 18) -+#define IEP_RGB_CNTRST_ENHNC_DDE_FRST BIT(20) -+#define IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT 21 -+#define IEP_DEIN_EDGE_INTPOL_RADIUS_MASK (3 << IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT) -+#define IEP_DEIN_EDGE_INTPOL_SELECT BIT(23) -+ -+#define IEP_CONFIG1 0x004 /* Configuration register1 */ -+#define IEP_SRC_FMT_SHFT 0 -+#define IEP_SRC_FMT_MASK (3 << IEP_SRC_FMT_SHFT) -+#define IEP_SRC_RGB_SWP_SHFT 2 -+#define IEP_SRC_RGB_SWP_MASK (2 << IEP_SRC_RGB_SWP_SHFT) -+#define IEP_SRC_YUV_SWP_SHFT 4 -+#define IEP_SRC_YUV_SWP_MASK (3 << IEP_SRC_YUV_SWP_SHFT) -+#define IEP_DST_FMT_SHFT 8 -+#define IEP_DST_FMT_MASK (3 << IEP_DST_FMT_SHFT) -+#define IEP_DST_RGB_SWP_SHFT 10 -+#define IEP_DST_RGB_SWP_MASK (2 << IEP_DST_RGB_SWP_SHFT) -+#define IEP_DST_YUV_SWP_SHFT 12 -+#define IEP_DST_YUV_SWP_MASK (3 << IEP_DST_YUV_SWP_SHFT) -+#define IEP_DTH_UP_EN BIT(14) -+#define IEP_DTH_DWN_EN BIT(15) -+#define IEP_YUV2RGB_COE_BT601_1 (0 << 16) -+#define IEP_YUV2RGB_COE_BT601_F BIT(16) -+#define IEP_YUV2RGB_COE_BT709_1 (2 << 16) -+#define IEP_YUV2RGB_COE_BT709_F (3 << 16) -+#define IEP_YUV2RGB_COE_MASK (3 << 16) -+#define IEP_RGB2YUV_COE_BT601_1 (0 << 18) -+#define IEP_RGB2YUV_COE_BT601_F BIT(18) -+#define IEP_RGB2YUV_COE_BT709_1 (2 << 18) -+#define IEP_RGB2YUV_COE_BT709_F (3 << 18) -+#define IEP_RGB2YUV_COE_MASK (3 << 18) -+#define IEP_YUV2RGB_EN BIT(20) -+#define IEP_RGB2YUV_EN BIT(21) -+#define IEP_YUV2RGB_CLIP_EN BIT(22) -+#define IEP_RGB2YUV_CLIP_EN BIT(23) -+#define IEP_GLB_ALPHA_SHFT 24 -+#define IEP_GLB_ALPHA_MASK (0x7f << IEP_GLB_ALPHA_SHFT) -+ -+#define IEP_STATUS 0x008 /* Status register */ -+#define IEP_STATUS_YUV_DNS BIT(0) -+#define IEP_STATUS_SCL BIT(1) -+#define IEP_STATUS_DIL BIT(2) -+#define IEP_STATUS_DDE BIT(3) -+#define IEP_STATUS_DMA_WR_YUV BIT(4) -+#define IEP_STATUS_DMA_RE_YUV BIT(5) -+#define IEP_STATUS_DMA_WR_RGB BIT(6) -+#define IEP_STATUS_DMA_RE_RGB BIT(7) -+#define IEP_STATUS_VOP_DIRECT_PATH BIT(8) -+#define IEP_STATUS_DMA_IA_WR_YUV BIT(16) -+#define IEP_STATUS_DMA_IA_RE_YUV BIT(17) -+#define IEP_STATUS_DMA_IA_WR_RGB BIT(18) -+#define IEP_STATUS_DMA_IA_RE_RGB BIT(19) -+ -+#define IEP_INT 0x00c /* Interrupt register*/ -+#define IEP_INT_FRAME_DONE BIT(0) /* Frame process done interrupt */ -+#define IEP_INT_FRAME_DONE_EN BIT(8) /* Frame process done interrupt enable */ -+#define IEP_INT_FRAME_DONE_CLR BIT(16) /* Frame process done interrupt clear */ -+ -+#define IEP_FRM_START 0x010 /* Frame start */ -+#define IEP_SRST 0x014 /* Soft reset */ -+#define IEP_CONFIG_DONE 0x018 /* Configuration done */ -+#define IEP_FRM_CNT 0x01c /* Frame counter */ -+ -+#define IEP_VIR_IMG_WIDTH 0x020 /* Image virtual width */ -+#define IEP_IMG_SCL_FCT 0x024 /* Scaling factor */ -+#define IEP_SRC_IMG_SIZE 0x028 /* src image width/height */ -+#define IEP_DST_IMG_SIZE 0x02c /* dst image width/height */ -+#define IEP_DST_IMG_WIDTH_TILE0 0x030 /* dst image tile0 width */ -+#define IEP_DST_IMG_WIDTH_TILE1 0x034 /* dst image tile1 width */ -+#define IEP_DST_IMG_WIDTH_TILE2 0x038 /* dst image tile2 width */ -+#define IEP_DST_IMG_WIDTH_TILE3 0x03c /* dst image tile3 width */ -+ -+#define IEP_ENH_YUV_CNFG_0 0x040 /* Brightness, contrast, saturation adjustment */ -+#define IEP_YUV_BRIGHTNESS_SHFT 0 -+#define IEP_YUV_BRIGHTNESS_MASK (0x3f << IEP_YUV_BRIGHTNESS_SHFT) -+#define IEP_YUV_CONTRAST_SHFT 8 -+#define IEP_YUV_CONTRAST_MASK (0xff << IEP_YUV_CONTRAST_SHFT) -+#define IEP_YUV_SATURATION_SHFT 16 -+#define IEP_YUV_SATURATION_MASK (0x1ff << IEP_YUV_SATURATION_SHFT) -+ -+#define IEP_ENH_YUV_CNFG_1 0x044 /* Hue configuration */ -+#define IEP_YUV_COS_HUE_SHFT 0 -+#define IEP_YUV_COS_HUE_MASK (0xff << IEP_YUV_COS_HUE_SHFT) -+#define IEP_YUV_SIN_HUE_SHFT 8 -+#define IEP_YUV_SIN_HUE_MASK (0xff << IEP_YUV_SIN_HUE_SHFT) -+ -+#define IEP_ENH_YUV_CNFG_2 0x048 /* Color bar configuration */ -+#define IEP_YUV_COLOR_BAR_Y_SHFT 0 -+#define IEP_YUV_COLOR_BAR_Y_MASK (0xff << IEP_YUV_COLOR_BAR_Y_SHFT) -+#define IEP_YUV_COLOR_BAR_U_SHFT 8 -+#define IEP_YUV_COLOR_BAR_U_MASK (0xff << IEP_YUV_COLOR_BAR_U_SHFT) -+#define IEP_YUV_COLOR_BAR_V_SHFT 16 -+#define IEP_YUV_COLOR_BAR_V_MASK (0xff << IEP_YUV_COLOR_BAR_V_SHFT) -+#define IEP_YUV_VIDEO_MODE_SHFT 24 -+#define IEP_YUV_VIDEO_MODE_MASK (3 << IEP_YUV_VIDEO_MODE_SHFT) -+ -+#define IEP_ENH_RGB_CNFG 0x04c /* RGB enhancement configuration */ -+#define IEP_ENH_RGB_C_COE 0x050 /* RGB color enhancement coefficient */ -+ -+#define IEP_RAW_CONFIG0 0x058 /* Raw configuration register0 */ -+#define IEP_RAW_CONFIG1 0x05c /* Raw configuration register1 */ -+#define IEP_RAW_VIR_IMG_WIDTH 0x060 /* Raw image virtual width */ -+#define IEP_RAW_IMG_SCL_FCT 0x064 /* Raw scaling factor */ -+#define IEP_RAW_SRC_IMG_SIZE 0x068 /* Raw src image width/height */ -+#define IEP_RAW_DST_IMG_SIZE 0x06c /* Raw src image width/height */ -+#define IEP_RAW_ENH_YUV_CNFG_0 0x070 /* Raw brightness,contrast,saturation adjustment */ -+#define IEP_RAW_ENH_YUV_CNFG_1 0x074 /* Raw hue configuration */ -+#define IEP_RAW_ENH_YUV_CNFG_2 0x078 /* Raw color bar configuration */ -+#define IEP_RAW_ENH_RGB_CNFG 0x07c /* Raw RGB enhancement configuration */ -+ -+#define IEP_SRC_ADDR_Y_RGB 0x080 /* Start addr. of src image 0 (Y/RGB) */ -+#define IEP_SRC_ADDR_CBCR 0x084 /* Start addr. of src image 0 (Cb/Cr) */ -+#define IEP_SRC_ADDR_CR 0x088 /* Start addr. of src image 0 (Cr) */ -+#define IEP_SRC_ADDR_Y1 0x08c /* Start addr. of src image 1 (Y) */ -+#define IEP_SRC_ADDR_CBCR1 0x090 /* Start addr. of src image 1 (Cb/Cr) */ -+#define IEP_SRC_ADDR_CR1 0x094 /* Start addr. of src image 1 (Cr) */ -+#define IEP_SRC_ADDR_Y_ITEMP 0x098 /* Start addr. of src image(Y int part) */ -+#define IEP_SRC_ADDR_CBCR_ITEMP 0x09c /* Start addr. of src image(CBCR int part) */ -+#define IEP_SRC_ADDR_CR_ITEMP 0x0a0 /* Start addr. of src image(CR int part) */ -+#define IEP_SRC_ADDR_Y_FTEMP 0x0a4 /* Start addr. of src image(Y frac part) */ -+#define IEP_SRC_ADDR_CBCR_FTEMP 0x0a8 /* Start addr. of src image(CBCR frac part) */ -+#define IEP_SRC_ADDR_CR_FTEMP 0x0ac /* Start addr. of src image(CR frac part) */ -+ -+#define IEP_DST_ADDR_Y_RGB 0x0b0 /* Start addr. of dst image 0 (Y/RGB) */ -+#define IEP_DST_ADDR_CBCR 0x0b4 /* Start addr. of dst image 0 (Cb/Cr) */ -+#define IEP_DST_ADDR_CR 0x0b8 /* Start addr. of dst image 0 (Cr) */ -+#define IEP_DST_ADDR_Y1 0x0bc /* Start addr. of dst image 1 (Y) */ -+#define IEP_DST_ADDR_CBCR1 0x0c0 /* Start addr. of dst image 1 (Cb/Cr) */ -+#define IEP_DST_ADDR_CR1 0x0c4 /* Start addr. of dst image 1 (Cr) */ -+#define IEP_DST_ADDR_Y_ITEMP 0x0c8 /* Start addr. of dst image(Y int part) */ -+#define IEP_DST_ADDR_CBCR_ITEMP 0x0cc /* Start addr. of dst image(CBCR int part)*/ -+#define IEP_DST_ADDR_CR_ITEMP 0x0d0 /* Start addr. of dst image(CR int part) */ -+#define IEP_DST_ADDR_Y_FTEMP 0x0d4 /* Start addr. of dst image(Y frac part) */ -+#define IEP_DST_ADDR_CBCR_FTEMP 0x0d8 /* Start addr. of dst image(CBCR frac part) */ -+#define IEP_DST_ADDR_CR_FTEMP 0x0dc /* Start addr. of dst image(CR frac part)*/ -+ -+#define IEP_DEIN_MTN_TAB0 0x0e0 /* Deinterlace motion table0 */ -+#define IEP_DEIN_MTN_TAB1 0x0e4 /* Deinterlace motion table1 */ -+#define IEP_DEIN_MTN_TAB2 0x0e8 /* Deinterlace motion table2 */ -+#define IEP_DEIN_MTN_TAB3 0x0ec /* Deinterlace motion table3 */ -+#define IEP_DEIN_MTN_TAB4 0x0f0 /* Deinterlace motion table4 */ -+#define IEP_DEIN_MTN_TAB5 0x0f4 /* Deinterlace motion table5 */ -+#define IEP_DEIN_MTN_TAB6 0x0f8 /* Deinterlace motion table6 */ -+#define IEP_DEIN_MTN_TAB7 0x0fc /* Deinterlace motion table7 */ -+ -+#define IEP_ENH_CG_TAB 0x100 /* Contrast and gamma enhancement table */ -+#define IEP_ENH_DDE_COE0 0x400 /* Denoise,detail and edge enhancement coefficient */ -+#define IEP_ENH_DDE_COE1 0x500 /* Denoise,detail and edge enhancement coefficient1 */ -+ -+#define IEP_INT_MASK (IEP_INT_FRAME_DONE) -+ -+/* IEP colorformats */ -+#define IEP_COLOR_FMT_XRGB 0U -+#define IEP_COLOR_FMT_RGB565 1U -+#define IEP_COLOR_FMT_YUV422 2U -+#define IEP_COLOR_FMT_YUV420 3U -+ -+/* IEP YUV color swaps */ -+#define IEP_YUV_SWP_SP_UV 0U -+#define IEP_YUV_SWP_SP_VU 1U -+#define IEP_YUV_SWP_P 2U -+ -+/* IEP XRGB color swaps */ -+#define XRGB_SWP_XRGB 0U -+#define XRGB_SWP_XBGR 1U -+#define XRGB_SWP_BGRX 2U -+ -+/* IEP RGB565 color swaps */ -+#define RGB565_SWP_RGB 0U -+#define RGB565_SWP_BGR 1U -+ -+#define FMT_IS_YUV(fmt) (fmt == IEP_COLOR_FMT_XRGB || fmt == IEP_COLOR_FMT_RGB565 ? 0 : 1) -+ -+#define IEP_IMG_SIZE(w, h) (((w - 1) & 0x1fff) << 0 | \ -+ ((h - 1) & 0x1fff) << 16) -+ -+#define IEP_VIR_WIDTH(src_w, dst_w) (((src_w / 4) & 0x1fff) << 0 | \ -+ ((dst_w / 4) & 0x1fff) << 16) -+ -+#define IEP_Y_STRIDE(w, h) (w * h) -+#define IEP_UV_STRIDE(w, h, fac) (w * h + w * h / fac) -+ -+#define IEP_SRC_FMT_SWP_MASK(f) (FMT_IS_YUV(f) ? IEP_SRC_YUV_SWP_MASK : IEP_SRC_RGB_SWP_MASK) -+#define IEP_DST_FMT_SWP_MASK(f) (FMT_IS_YUV(f) ? IEP_DST_YUV_SWP_MASK : IEP_DST_RGB_SWP_MASK) -+ -+#define IEP_SRC_FMT(f, swp) (f << IEP_SRC_FMT_SHFT | \ -+ (swp << (FMT_IS_YUV(f) ? IEP_SRC_YUV_SWP_SHFT : IEP_SRC_RGB_SWP_SHFT))) -+#define IEP_DST_FMT(f, swp) (f << IEP_DST_FMT_SHFT | \ -+ (swp << (FMT_IS_YUV(f) ? IEP_DST_YUV_SWP_SHFT : IEP_DST_RGB_SWP_SHFT))) -+ -+/* IEP DEINTERLACE MODES */ -+#define IEP_DEIN_MODE_YUV 0U -+#define IEP_DEIN_MODE_I4O2 1U -+#define IEP_DEIN_MODE_I4O1B 2U -+#define IEP_DEIN_MODE_I4O1T 3U -+#define IEP_DEIN_MODE_I2O1B 4U -+#define IEP_DEIN_MODE_I2O1T 5U -+#define IEP_DEIN_MODE_BYPASS 6U -+ -+#define IEP_DEIN_IN_FIELDS_2 2U -+#define IEP_DEIN_IN_FIELDS_4 4U -+ -+#define IEP_DEIN_OUT_FRAMES_1 1U -+#define IEP_DEIN_OUT_FRAMES_2 2U -+ -+/* values taken from BSP driver */ -+static const u32 default_dein_motion_tbl[][2] = { -+ { IEP_DEIN_MTN_TAB0, 0x40404040 }, -+ { IEP_DEIN_MTN_TAB1, 0x3c3e3f3f }, -+ { IEP_DEIN_MTN_TAB2, 0x3336393b }, -+ { IEP_DEIN_MTN_TAB3, 0x272a2d31 }, -+ { IEP_DEIN_MTN_TAB4, 0x181c2023 }, -+ { IEP_DEIN_MTN_TAB5, 0x0c0e1215 }, -+ { IEP_DEIN_MTN_TAB6, 0x03040609 }, -+ { IEP_DEIN_MTN_TAB7, 0x00000001 }, -+ -+}; -+ -+#define IEP_DEIN_IN_IMG0_Y(bff) (bff ? IEP_SRC_ADDR_Y_RGB : IEP_SRC_ADDR_Y1) -+#define IEP_DEIN_IN_IMG0_CBCR(bff) (bff ? IEP_SRC_ADDR_CBCR : IEP_SRC_ADDR_CBCR1) -+#define IEP_DEIN_IN_IMG0_CR(bff) (bff ? IEP_SRC_ADDR_CR : IEP_SRC_ADDR_CR1) -+#define IEP_DEIN_IN_IMG1_Y(bff) (IEP_DEIN_IN_IMG0_Y(!bff)) -+#define IEP_DEIN_IN_IMG1_CBCR(bff) (IEP_DEIN_IN_IMG0_CBCR(!bff)) -+#define IEP_DEIN_IN_IMG1_CR(bff) (IEP_DEIN_IN_IMG0_CR(!bff)) -+ -+#define IEP_DEIN_OUT_IMG0_Y(bff) (bff ? IEP_DST_ADDR_Y1 : IEP_DST_ADDR_Y_RGB) -+#define IEP_DEIN_OUT_IMG0_CBCR(bff) (bff ? IEP_DST_ADDR_CBCR1 : IEP_DST_ADDR_CBCR) -+#define IEP_DEIN_OUT_IMG0_CR(bff) (bff ? IEP_DST_ADDR_CR1 : IEP_DST_ADDR_CR) -+#define IEP_DEIN_OUT_IMG1_Y(bff) (IEP_DEIN_OUT_IMG0_Y(!bff)) -+#define IEP_DEIN_OUT_IMG1_CBCR(bff) (IEP_DEIN_OUT_IMG0_CBCR(!bff)) -+#define IEP_DEIN_OUT_IMG1_CR(bff) (IEP_DEIN_OUT_IMG0_CR(!bff)) -+ -+#define IEP_DEIN_MODE(m) (m << IEP_DEIN_MODE_SHFT) -+ -+#define IEP_DEIN_IN_MODE_FIELDS(m) ((m == IEP_DEIN_MODE_I4O1T || m == IEP_DEIN_MODE_I4O1B \ -+ || m == IEP_DEIN_MODE_I4O2) \ -+ ? IEP_DEIN_IN_FIELDS_4 : IEP_DEIN_IN_FIELDS_2) -+ -+#define IEP_DEIN_OUT_MODE_FRAMES(m) (m == IEP_DEIN_MODE_I4O2 \ -+ ? IEP_DEIN_OUT_FRAMES_2 : IEP_DEIN_OUT_FRAMES_1) -+ -+#define IEP_DEIN_OUT_MODE_1FRM_TOP_FIELD(m) (m == IEP_DEIN_MODE_I4O1T || IEP_DEIN_MODE_I2O1T \ -+ ? 1 : 0) -+ -+#define IEP_DEIN_EDGE_INTPOL_RADIUS(r) (r << IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT) -+ -+#define IEP_DEIN_HIGH_FREQ(f) (f << IEP_DEIN_HIGH_FREQ_SHFT) -+ -+/* YUV Enhance video modes */ -+#define VIDEO_MODE_BLACK_SCREEN 0U -+#define VIDEO_MODE_BLUE_SCREEN 1U -+#define VIDEO_MODE_COLOR_BARS 2U -+#define VIDEO_MODE_NORMAL_VIDEO 3U -+ -+#define YUV_VIDEO_MODE(m) ((m << IEP_YUV_VIDEO_MODE_SHFT) & IEP_YUV_VIDEO_MODE_MASK) -+#define YUV_BRIGHTNESS(v) ((v << IEP_YUV_BRIGHTNESS_SHFT) & IEP_YUV_BRIGHTNESS_MASK) -+#define YUV_CONTRAST(v) ((v << IEP_YUV_CONTRAST_SHFT) & IEP_YUV_CONTRAST_MASK) -+#define YUV_SATURATION(v) ((v << IEP_YUV_SATURATION_SHFT) & IEP_YUV_SATURATION_MASK) -+#define YUV_COS_HUE(v) ((v << IEP_YUV_COS_HUE_SHFT) & IEP_YUV_COS_HUE_MASK) -+#define YUV_SIN_HUE(v) ((v << IEP_YUV_SIN_HUE_SHFT) & IEP_YUV_SIN_HUE_MASK) -+ -+#endif -diff -rupN linux.orig/drivers/media/platform/rockchip/iep/iep.c linux/drivers/media/platform/rockchip/iep/iep.c ---- linux.orig/drivers/media/platform/rockchip/iep/iep.c 1970-01-01 00:00:00.000000000 +0000 -+++ linux/drivers/media/platform/rockchip/iep/iep.c 2024-01-03 21:28:43.674043912 +0000 -@@ -0,0 +1,1089 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Rockchip Image Enhancement Processor (IEP) driver -+ * -+ * Copyright (C) 2020 Alex Bee -+ * -+ * Based on Allwinner sun8i deinterlacer with scaler driver -+ * Copyright (C) 2019 Jernej Skrabec -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "iep-regs.h" -+#include "iep.h" -+ -+static struct iep_fmt formats[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_NV12, -+ .color_swap = IEP_YUV_SWP_SP_UV, -+ .hw_format = IEP_COLOR_FMT_YUV420, -+ .depth = 12, -+ .uv_factor = 4, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_NV21, -+ .color_swap = IEP_YUV_SWP_SP_VU, -+ .hw_format = IEP_COLOR_FMT_YUV420, -+ .depth = 12, -+ .uv_factor = 4, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_NV16, -+ .color_swap = IEP_YUV_SWP_SP_UV, -+ .hw_format = IEP_COLOR_FMT_YUV422, -+ .depth = 16, -+ .uv_factor = 2, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_NV61, -+ .color_swap = IEP_YUV_SWP_SP_VU, -+ .hw_format = IEP_COLOR_FMT_YUV422, -+ .depth = 16, -+ .uv_factor = 2, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_YUV420, -+ .color_swap = IEP_YUV_SWP_P, -+ .hw_format = IEP_COLOR_FMT_YUV420, -+ .depth = 12, -+ .uv_factor = 4, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_YUV422P, -+ .color_swap = IEP_YUV_SWP_P, -+ .hw_format = IEP_COLOR_FMT_YUV422, -+ .depth = 16, -+ .uv_factor = 2, -+ }, -+}; -+ -+static struct iep_fmt *iep_fmt_find(struct v4l2_pix_format *pix_fmt) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < ARRAY_SIZE(formats); i++) { -+ if (formats[i].fourcc == pix_fmt->pixelformat) -+ return &formats[i]; -+ } -+ -+ return NULL; -+} -+ -+static bool iep_check_pix_format(u32 pixelformat) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < ARRAY_SIZE(formats); i++) -+ if (formats[i].fourcc == pixelformat) -+ return true; -+ -+ return false; -+} -+ -+static struct vb2_v4l2_buffer *iep_m2m_next_dst_buf(struct iep_ctx *ctx) -+{ -+ struct vb2_v4l2_buffer *dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); -+ -+ /* application has set a dst sequence: take it as start point */ -+ if (ctx->dst_sequence == 0 && dst_buf->sequence > 0) -+ ctx->dst_sequence = dst_buf->sequence; -+ -+ dst_buf->sequence = ctx->dst_sequence++; -+ -+ return dst_buf; -+} -+ -+static void iep_m2m_dst_bufs_done(struct iep_ctx *ctx, enum vb2_buffer_state state) -+{ -+ if (ctx->dst0_buf) { -+ v4l2_m2m_buf_done(ctx->dst0_buf, state); -+ ctx->dst_buffs_done++; -+ ctx->dst0_buf = NULL; -+ } -+ -+ if (ctx->dst1_buf) { -+ v4l2_m2m_buf_done(ctx->dst1_buf, state); -+ ctx->dst_buffs_done++; -+ ctx->dst1_buf = NULL; -+ } -+} -+ -+static void iep_setup_formats(struct iep_ctx *ctx) -+{ -+ /* setup src dimensions */ -+ iep_write(ctx->iep, IEP_SRC_IMG_SIZE, -+ IEP_IMG_SIZE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height)); -+ -+ /* setup dst dimensions */ -+ iep_write(ctx->iep, IEP_DST_IMG_SIZE, -+ IEP_IMG_SIZE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height)); -+ -+ /* setup virtual width */ -+ iep_write(ctx->iep, IEP_VIR_IMG_WIDTH, -+ IEP_VIR_WIDTH(ctx->src_fmt.pix.width, ctx->dst_fmt.pix.width)); -+ -+ /* setup src format */ -+ iep_shadow_mod(ctx->iep, IEP_CONFIG1, IEP_RAW_CONFIG1, -+ IEP_SRC_FMT_MASK | IEP_SRC_FMT_SWP_MASK(ctx->src_fmt.hw_fmt->hw_format), -+ IEP_SRC_FMT(ctx->src_fmt.hw_fmt->hw_format, -+ ctx->src_fmt.hw_fmt->color_swap)); -+ /* setup dst format */ -+ iep_shadow_mod(ctx->iep, IEP_CONFIG1, IEP_RAW_CONFIG1, -+ IEP_DST_FMT_MASK | IEP_DST_FMT_SWP_MASK(ctx->dst_fmt.hw_fmt->hw_format), -+ IEP_DST_FMT(ctx->dst_fmt.hw_fmt->hw_format, -+ ctx->dst_fmt.hw_fmt->color_swap)); -+ -+ ctx->fmt_changed = false; -+} -+ -+static void iep_dein_init(struct rockchip_iep *iep) -+{ -+ unsigned int i; -+ -+ /* values taken from BSP driver */ -+ iep_shadow_mod(iep, IEP_CONFIG0, IEP_RAW_CONFIG0, -+ (IEP_DEIN_EDGE_INTPOL_SMTH_EN | -+ IEP_DEIN_EDGE_INTPOL_RADIUS_MASK | -+ IEP_DEIN_HIGH_FREQ_EN | -+ IEP_DEIN_HIGH_FREQ_MASK), -+ (IEP_DEIN_EDGE_INTPOL_SMTH_EN | -+ IEP_DEIN_EDGE_INTPOL_RADIUS(3) | -+ IEP_DEIN_HIGH_FREQ_EN | -+ IEP_DEIN_HIGH_FREQ(64))); -+ -+ for (i = 0; i < ARRAY_SIZE(default_dein_motion_tbl); i++) -+ iep_write(iep, default_dein_motion_tbl[i][0], -+ default_dein_motion_tbl[i][1]); -+} -+ -+static void iep_init(struct rockchip_iep *iep) -+{ -+ iep_write(iep, IEP_CONFIG0, -+ IEP_DEIN_MODE(IEP_DEIN_MODE_BYPASS) // | -+ //IEP_YUV_ENHNC_EN -+ ); -+ -+ /* TODO: B/S/C/H works -+ * only in 1-frame-out modes -+ iep_write(iep, IEP_ENH_YUV_CNFG_0, -+ YUV_BRIGHTNESS(0) | -+ YUV_CONTRAST(128) | -+ YUV_SATURATION(128)); -+ -+ iep_write(iep, IEP_ENH_YUV_CNFG_1, -+ YUV_COS_HUE(255) | -+ YUV_SIN_HUE(255)); -+ -+ iep_write(iep, IEP_ENH_YUV_CNFG_2, -+ YUV_VIDEO_MODE(VIDEO_MODE_NORMAL_VIDEO)); -+ -+ */ -+ -+ /* reset frame counter */ -+ iep_write(iep, IEP_FRM_CNT, 0); -+} -+ -+static void iep_device_run(void *priv) -+{ -+ struct iep_ctx *ctx = priv; -+ struct rockchip_iep *iep = ctx->iep; -+ struct vb2_v4l2_buffer *src, *dst; -+ unsigned int dein_mode; -+ dma_addr_t addr; -+ -+ if (ctx->fmt_changed) -+ iep_setup_formats(ctx); -+ -+ if (ctx->prev_src_buf) -+ dein_mode = IEP_DEIN_MODE_I4O2; -+ else -+ dein_mode = ctx->field_bff ? IEP_DEIN_MODE_I2O1B : IEP_DEIN_MODE_I2O1T; -+ -+ iep_shadow_mod(iep, IEP_CONFIG0, IEP_RAW_CONFIG0, -+ IEP_DEIN_MODE_MASK, IEP_DEIN_MODE(dein_mode)); -+ -+ /* sync RAW_xxx registers with actual used */ -+ iep_write(iep, IEP_CONFIG_DONE, 1); -+ -+ /* setup src buff(s)/addresses */ -+ src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); -+ addr = vb2_dma_contig_plane_dma_addr(&src->vb2_buf, 0); -+ -+ iep_write(iep, IEP_DEIN_IN_IMG0_Y(ctx->field_bff), addr); -+ -+ iep_write(iep, IEP_DEIN_IN_IMG0_CBCR(ctx->field_bff), -+ addr + ctx->src_fmt.y_stride); -+ -+ iep_write(iep, IEP_DEIN_IN_IMG0_CR(ctx->field_bff), -+ addr + ctx->src_fmt.uv_stride); -+ -+ if (IEP_DEIN_IN_MODE_FIELDS(dein_mode) == IEP_DEIN_IN_FIELDS_4) -+ addr = vb2_dma_contig_plane_dma_addr(&ctx->prev_src_buf->vb2_buf, 0); -+ -+ iep_write(iep, IEP_DEIN_IN_IMG1_Y(ctx->field_bff), addr); -+ -+ iep_write(iep, IEP_DEIN_IN_IMG1_CBCR(ctx->field_bff), -+ addr + ctx->src_fmt.y_stride); -+ -+ iep_write(iep, IEP_DEIN_IN_IMG1_CR(ctx->field_bff), -+ addr + ctx->src_fmt.uv_stride); -+ -+ /* setup dst buff(s)/addresses */ -+ dst = iep_m2m_next_dst_buf(ctx); -+ addr = vb2_dma_contig_plane_dma_addr(&dst->vb2_buf, 0); -+ -+ if (IEP_DEIN_OUT_MODE_FRAMES(dein_mode) == IEP_DEIN_OUT_FRAMES_2) { -+ v4l2_m2m_buf_copy_metadata(ctx->prev_src_buf, dst, true); -+ -+ iep_write(iep, IEP_DEIN_OUT_IMG0_Y(ctx->field_bff), addr); -+ -+ iep_write(iep, IEP_DEIN_OUT_IMG0_CBCR(ctx->field_bff), -+ addr + ctx->dst_fmt.y_stride); -+ -+ iep_write(iep, IEP_DEIN_OUT_IMG0_CR(ctx->field_bff), -+ addr + ctx->dst_fmt.uv_stride); -+ -+ ctx->dst0_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); -+ -+ dst = iep_m2m_next_dst_buf(ctx); -+ addr = vb2_dma_contig_plane_dma_addr(&dst->vb2_buf, 0); -+ } -+ -+ v4l2_m2m_buf_copy_metadata(src, dst, true); -+ -+ iep_write(iep, IEP_DEIN_OUT_IMG1_Y(ctx->field_bff), addr); -+ -+ iep_write(iep, IEP_DEIN_OUT_IMG1_CBCR(ctx->field_bff), -+ addr + ctx->dst_fmt.y_stride); -+ -+ iep_write(iep, IEP_DEIN_OUT_IMG1_CR(ctx->field_bff), -+ addr + ctx->dst_fmt.uv_stride); -+ -+ ctx->dst1_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); -+ -+ iep_mod(ctx->iep, IEP_INT, IEP_INT_FRAME_DONE_EN, -+ IEP_INT_FRAME_DONE_EN); -+ -+ /* start HW */ -+ iep_write(iep, IEP_FRM_START, 1); -+} -+ -+static int iep_job_ready(void *priv) -+{ -+ struct iep_ctx *ctx = priv; -+ -+ return v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) >= 2 && -+ v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) >= 1; -+} -+ -+static void iep_job_abort(void *priv) -+{ -+ struct iep_ctx *ctx = priv; -+ -+ /* Will cancel the transaction in the next interrupt handler */ -+ ctx->job_abort = true; -+} -+ -+static const struct v4l2_m2m_ops iep_m2m_ops = { -+ .device_run = iep_device_run, -+ .job_ready = iep_job_ready, -+ .job_abort = iep_job_abort, -+}; -+ -+static int iep_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers, -+ unsigned int *nplanes, unsigned int sizes[], -+ struct device *alloc_devs[]) -+{ -+ struct iep_ctx *ctx = vb2_get_drv_priv(vq); -+ struct v4l2_pix_format *pix_fmt; -+ -+ if (V4L2_TYPE_IS_OUTPUT(vq->type)) -+ pix_fmt = &ctx->src_fmt.pix; -+ else -+ pix_fmt = &ctx->dst_fmt.pix; -+ -+ if (*nplanes) { -+ if (sizes[0] < pix_fmt->sizeimage) -+ return -EINVAL; -+ } else { -+ sizes[0] = pix_fmt->sizeimage; -+ *nplanes = 1; -+ } -+ -+ return 0; -+} -+ -+static int iep_buf_prepare(struct vb2_buffer *vb) -+{ -+ struct vb2_queue *vq = vb->vb2_queue; -+ struct iep_ctx *ctx = vb2_get_drv_priv(vq); -+ struct v4l2_pix_format *pix_fmt; -+ -+ if (V4L2_TYPE_IS_OUTPUT(vq->type)) -+ pix_fmt = &ctx->src_fmt.pix; -+ else -+ pix_fmt = &ctx->dst_fmt.pix; -+ -+ if (vb2_plane_size(vb, 0) < pix_fmt->sizeimage) -+ return -EINVAL; -+ -+ /* set bytesused for capture buffers */ -+ if (!V4L2_TYPE_IS_OUTPUT(vq->type)) -+ vb2_set_plane_payload(vb, 0, pix_fmt->sizeimage); -+ -+ return 0; -+} -+ -+static void iep_buf_queue(struct vb2_buffer *vb) -+{ -+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); -+ struct iep_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); -+ -+ v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf); -+} -+ -+static void iep_queue_cleanup(struct vb2_queue *vq, u32 state) -+{ -+ struct iep_ctx *ctx = vb2_get_drv_priv(vq); -+ struct vb2_v4l2_buffer *vbuf; -+ -+ do { -+ if (V4L2_TYPE_IS_OUTPUT(vq->type)) -+ vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); -+ else -+ vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); -+ -+ if (vbuf) -+ v4l2_m2m_buf_done(vbuf, state); -+ } while (vbuf); -+ -+ if (V4L2_TYPE_IS_OUTPUT(vq->type) && ctx->prev_src_buf) -+ v4l2_m2m_buf_done(ctx->prev_src_buf, state); -+ else -+ iep_m2m_dst_bufs_done(ctx, state); -+} -+ -+static int iep_start_streaming(struct vb2_queue *vq, unsigned int count) -+{ -+ struct iep_ctx *ctx = vb2_get_drv_priv(vq); -+ struct device *dev = ctx->iep->dev; -+ int ret; -+ -+ if (V4L2_TYPE_IS_OUTPUT(vq->type)) { -+ ret = pm_runtime_get_sync(dev); -+ if (ret < 0) { -+ dev_err(dev, "Failed to enable module\n"); -+ goto err_runtime_get; -+ } -+ -+ ctx->field_order_bff = -+ ctx->src_fmt.pix.field == V4L2_FIELD_INTERLACED_BT; -+ ctx->field_bff = ctx->field_order_bff; -+ -+ ctx->src_sequence = 0; -+ ctx->dst_sequence = 0; -+ -+ ctx->prev_src_buf = NULL; -+ -+ ctx->dst0_buf = NULL; -+ ctx->dst1_buf = NULL; -+ ctx->dst_buffs_done = 0; -+ -+ ctx->job_abort = false; -+ -+ iep_init(ctx->iep); -+ //if (ctx->src_fmt.pix.field != ctx->dst_fmt.pix.field) -+ iep_dein_init(ctx->iep); -+ } -+ -+ return 0; -+ -+err_runtime_get: -+ iep_queue_cleanup(vq, VB2_BUF_STATE_QUEUED); -+ -+ return ret; -+} -+ -+static void iep_stop_streaming(struct vb2_queue *vq) -+{ -+ struct iep_ctx *ctx = vb2_get_drv_priv(vq); -+ -+ if (V4L2_TYPE_IS_OUTPUT(vq->type)) { -+ pm_runtime_mark_last_busy(ctx->iep->dev); -+ pm_runtime_put_autosuspend(ctx->iep->dev); -+ } -+ -+ iep_queue_cleanup(vq, VB2_BUF_STATE_ERROR); -+} -+ -+static const struct vb2_ops iep_qops = { -+ .queue_setup = iep_queue_setup, -+ .buf_prepare = iep_buf_prepare, -+ .buf_queue = iep_buf_queue, -+ .start_streaming = iep_start_streaming, -+ .stop_streaming = iep_stop_streaming, -+ .wait_prepare = vb2_ops_wait_prepare, -+ .wait_finish = vb2_ops_wait_finish, -+}; -+ -+static int iep_queue_init(void *priv, struct vb2_queue *src_vq, -+ struct vb2_queue *dst_vq) -+{ -+ struct iep_ctx *ctx = priv; -+ int ret; -+ -+ src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT; -+ src_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES | -+ DMA_ATTR_NO_KERNEL_MAPPING; -+ src_vq->io_modes = VB2_MMAP | VB2_DMABUF; -+ src_vq->drv_priv = ctx; -+ src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); -+ src_vq->min_buffers_needed = 1; -+ src_vq->ops = &iep_qops; -+ src_vq->mem_ops = &vb2_dma_contig_memops; -+ src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; -+ src_vq->lock = &ctx->iep->mutex; -+ src_vq->dev = ctx->iep->v4l2_dev.dev; -+ -+ ret = vb2_queue_init(src_vq); -+ if (ret) -+ return ret; -+ -+ dst_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES | -+ DMA_ATTR_NO_KERNEL_MAPPING; -+ dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; -+ dst_vq->drv_priv = ctx; -+ dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); -+ dst_vq->min_buffers_needed = 2; -+ dst_vq->ops = &iep_qops; -+ dst_vq->mem_ops = &vb2_dma_contig_memops; -+ dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; -+ dst_vq->lock = &ctx->iep->mutex; -+ dst_vq->dev = ctx->iep->v4l2_dev.dev; -+ -+ ret = vb2_queue_init(dst_vq); -+ if (ret) -+ return ret; -+ -+ return 0; -+} -+ -+static void iep_prepare_format(struct v4l2_pix_format *pix_fmt) -+{ -+ unsigned int height = pix_fmt->height; -+ unsigned int width = pix_fmt->width; -+ unsigned int sizeimage, bytesperline; -+ -+ struct iep_fmt *hw_fmt = iep_fmt_find(pix_fmt); -+ -+ if (!hw_fmt) { -+ hw_fmt = &formats[0]; -+ pix_fmt->pixelformat = hw_fmt->fourcc; -+ } -+ -+ width = ALIGN(clamp(width, IEP_MIN_WIDTH, -+ IEP_MAX_WIDTH), 16); -+ height = ALIGN(clamp(height, IEP_MIN_HEIGHT, -+ IEP_MAX_HEIGHT), 16); -+ -+ bytesperline = FMT_IS_YUV(hw_fmt->hw_format) -+ ? width : (width * hw_fmt->depth) >> 3; -+ -+ sizeimage = height * (width * hw_fmt->depth) >> 3; -+ -+ pix_fmt->width = width; -+ pix_fmt->height = height; -+ pix_fmt->bytesperline = bytesperline; -+ pix_fmt->sizeimage = sizeimage; -+} -+ -+static int iep_open(struct file *file) -+{ -+ struct rockchip_iep *iep = video_drvdata(file); -+ struct iep_ctx *ctx = NULL; -+ -+ int ret; -+ -+ if (mutex_lock_interruptible(&iep->mutex)) -+ return -ERESTARTSYS; -+ -+ ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); -+ if (!ctx) { -+ mutex_unlock(&iep->mutex); -+ return -ENOMEM; -+ } -+ -+ /* default output format */ -+ ctx->src_fmt.pix.pixelformat = formats[0].fourcc; -+ ctx->src_fmt.pix.field = V4L2_FIELD_INTERLACED; -+ ctx->src_fmt.pix.width = IEP_DEFAULT_WIDTH; -+ ctx->src_fmt.pix.height = IEP_DEFAULT_HEIGHT; -+ iep_prepare_format(&ctx->src_fmt.pix); -+ ctx->src_fmt.hw_fmt = &formats[0]; -+ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height); -+ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height, -+ ctx->src_fmt.hw_fmt->uv_factor); -+ -+ /* default capture format */ -+ ctx->dst_fmt.pix.pixelformat = formats[0].fourcc; -+ ctx->dst_fmt.pix.field = V4L2_FIELD_NONE; -+ ctx->dst_fmt.pix.width = IEP_DEFAULT_WIDTH; -+ ctx->dst_fmt.pix.height = IEP_DEFAULT_HEIGHT; -+ iep_prepare_format(&ctx->dst_fmt.pix); -+ ctx->dst_fmt.hw_fmt = &formats[0]; -+ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height); -+ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height, -+ ctx->dst_fmt.hw_fmt->uv_factor); -+ /* ensure fmts are written to HW */ -+ ctx->fmt_changed = true; -+ -+ v4l2_fh_init(&ctx->fh, video_devdata(file)); -+ file->private_data = &ctx->fh; -+ ctx->iep = iep; -+ -+ ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(iep->m2m_dev, ctx, -+ &iep_queue_init); -+ -+ if (IS_ERR(ctx->fh.m2m_ctx)) { -+ ret = PTR_ERR(ctx->fh.m2m_ctx); -+ goto err_free; -+ } -+ -+ v4l2_fh_add(&ctx->fh); -+ -+ mutex_unlock(&iep->mutex); -+ -+ return 0; -+ -+err_free: -+ kfree(ctx); -+ mutex_unlock(&iep->mutex); -+ -+ return ret; -+} -+ -+static int iep_release(struct file *file) -+{ -+ struct rockchip_iep *iep = video_drvdata(file); -+ struct iep_ctx *ctx = container_of(file->private_data, -+ struct iep_ctx, fh); -+ -+ mutex_lock(&iep->mutex); -+ -+ v4l2_fh_del(&ctx->fh); -+ v4l2_fh_exit(&ctx->fh); -+ v4l2_m2m_ctx_release(ctx->fh.m2m_ctx); -+ kfree(ctx); -+ -+ mutex_unlock(&iep->mutex); -+ return 0; -+} -+ -+static const struct v4l2_file_operations iep_fops = { -+ .owner = THIS_MODULE, -+ .open = iep_open, -+ .release = iep_release, -+ .poll = v4l2_m2m_fop_poll, -+ .unlocked_ioctl = video_ioctl2, -+ .mmap = v4l2_m2m_fop_mmap, -+}; -+ -+static int iep_querycap(struct file *file, void *priv, -+ struct v4l2_capability *cap) -+{ -+ strscpy(cap->driver, IEP_NAME, sizeof(cap->driver)); -+ strscpy(cap->card, IEP_NAME, sizeof(cap->card)); -+ snprintf(cap->bus_info, sizeof(cap->bus_info), -+ "platform:%s", IEP_NAME); -+ -+ return 0; -+} -+ -+static int iep_enum_fmt(struct file *file, void *priv, -+ struct v4l2_fmtdesc *f) -+{ -+ struct iep_fmt *fmt; -+ -+ if (f->index < ARRAY_SIZE(formats)) { -+ fmt = &formats[f->index]; -+ f->pixelformat = fmt->fourcc; -+ -+ return 0; -+ } -+ -+ return -EINVAL; -+} -+ -+static int iep_enum_framesizes(struct file *file, void *priv, -+ struct v4l2_frmsizeenum *fsize) -+{ -+ if (fsize->index != 0) -+ return -EINVAL; -+ -+ if (!iep_check_pix_format(fsize->pixel_format)) -+ return -EINVAL; -+ -+ fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; -+ -+ fsize->stepwise.min_width = IEP_MIN_WIDTH; -+ fsize->stepwise.max_width = IEP_MAX_WIDTH; -+ fsize->stepwise.step_width = 16; -+ -+ fsize->stepwise.min_height = IEP_MIN_HEIGHT; -+ fsize->stepwise.max_height = IEP_MAX_HEIGHT; -+ fsize->stepwise.step_height = 16; -+ -+ return 0; -+} -+ -+static inline struct iep_ctx *iep_file2ctx(struct file *file) -+{ -+ return container_of(file->private_data, struct iep_ctx, fh); -+} -+ -+static int iep_g_fmt_vid_cap(struct file *file, void *priv, -+ struct v4l2_format *f) -+{ -+ struct iep_ctx *ctx = iep_file2ctx(file); -+ -+ f->fmt.pix = ctx->dst_fmt.pix; -+ -+ return 0; -+} -+ -+static int iep_g_fmt_vid_out(struct file *file, void *priv, -+ struct v4l2_format *f) -+{ -+ struct iep_ctx *ctx = iep_file2ctx(file); -+ -+ f->fmt.pix = ctx->src_fmt.pix; -+ -+ return 0; -+} -+ -+static int iep_try_fmt_vid_cap(struct file *file, void *priv, -+ struct v4l2_format *f) -+{ -+ f->fmt.pix.field = V4L2_FIELD_NONE; -+ iep_prepare_format(&f->fmt.pix); -+ -+ return 0; -+} -+ -+static int iep_try_fmt_vid_out(struct file *file, void *priv, -+ struct v4l2_format *f) -+{ -+ if (f->fmt.pix.field != V4L2_FIELD_INTERLACED_TB && -+ f->fmt.pix.field != V4L2_FIELD_INTERLACED_BT && -+ f->fmt.pix.field != V4L2_FIELD_INTERLACED) -+ f->fmt.pix.field = V4L2_FIELD_INTERLACED; -+ -+ iep_prepare_format(&f->fmt.pix); -+ -+ return 0; -+} -+ -+static int iep_s_fmt_vid_out(struct file *file, void *priv, -+ struct v4l2_format *f) -+{ -+ struct iep_ctx *ctx = iep_file2ctx(file); -+ struct vb2_queue *vq; -+ -+ int ret; -+ -+ ret = iep_try_fmt_vid_out(file, priv, f); -+ if (ret) -+ return ret; -+ -+ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); -+ if (vb2_is_busy(vq)) -+ return -EBUSY; -+ -+ ctx->src_fmt.pix = f->fmt.pix; -+ ctx->src_fmt.hw_fmt = iep_fmt_find(&f->fmt.pix); -+ ctx->src_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height); -+ ctx->src_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height, -+ ctx->src_fmt.hw_fmt->uv_factor); -+ -+ /* Propagate colorspace information to capture. */ -+ ctx->dst_fmt.pix.colorspace = f->fmt.pix.colorspace; -+ ctx->dst_fmt.pix.xfer_func = f->fmt.pix.xfer_func; -+ ctx->dst_fmt.pix.ycbcr_enc = f->fmt.pix.ycbcr_enc; -+ ctx->dst_fmt.pix.quantization = f->fmt.pix.quantization; -+ -+ /* scaling is not supported */ -+ ctx->dst_fmt.pix.width = f->fmt.pix.width; -+ ctx->dst_fmt.pix.height = f->fmt.pix.height; -+ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height); -+ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height, -+ ctx->dst_fmt.hw_fmt->uv_factor); -+ -+ ctx->fmt_changed = true; -+ -+ return 0; -+} -+ -+static int iep_s_fmt_vid_cap(struct file *file, void *priv, -+ struct v4l2_format *f) -+{ -+ struct iep_ctx *ctx = iep_file2ctx(file); -+ struct vb2_queue *vq; -+ int ret; -+ -+ ret = iep_try_fmt_vid_cap(file, priv, f); -+ if (ret) -+ return ret; -+ -+ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); -+ if (vb2_is_busy(vq)) -+ return -EBUSY; -+ -+ /* scaling is not supported */ -+ f->fmt.pix.width = ctx->src_fmt.pix.width; -+ f->fmt.pix.height = ctx->src_fmt.pix.height; -+ -+ ctx->dst_fmt.pix = f->fmt.pix; -+ ctx->dst_fmt.hw_fmt = iep_fmt_find(&f->fmt.pix); -+ -+ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height); -+ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height, -+ ctx->dst_fmt.hw_fmt->uv_factor); -+ -+ ctx->fmt_changed = true; -+ -+ return 0; -+} -+ -+static const struct v4l2_ioctl_ops iep_ioctl_ops = { -+ .vidioc_querycap = iep_querycap, -+ -+ .vidioc_enum_framesizes = iep_enum_framesizes, -+ -+ .vidioc_enum_fmt_vid_cap = iep_enum_fmt, -+ .vidioc_g_fmt_vid_cap = iep_g_fmt_vid_cap, -+ .vidioc_try_fmt_vid_cap = iep_try_fmt_vid_cap, -+ .vidioc_s_fmt_vid_cap = iep_s_fmt_vid_cap, -+ -+ .vidioc_enum_fmt_vid_out = iep_enum_fmt, -+ .vidioc_g_fmt_vid_out = iep_g_fmt_vid_out, -+ .vidioc_try_fmt_vid_out = iep_try_fmt_vid_out, -+ .vidioc_s_fmt_vid_out = iep_s_fmt_vid_out, -+ -+ .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, -+ .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, -+ .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, -+ .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, -+ .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, -+ .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, -+ .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, -+ -+ .vidioc_streamon = v4l2_m2m_ioctl_streamon, -+ .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, -+}; -+ -+static const struct video_device iep_video_device = { -+ .name = IEP_NAME, -+ .vfl_dir = VFL_DIR_M2M, -+ .fops = &iep_fops, -+ .ioctl_ops = &iep_ioctl_ops, -+ .minor = -1, -+ .release = video_device_release_empty, -+ .device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING, -+}; -+ -+static int iep_parse_dt(struct rockchip_iep *iep) -+{ -+ int ret = 0; -+ -+ iep->axi_clk = devm_clk_get(iep->dev, "axi"); -+ if (IS_ERR(iep->axi_clk)) { -+ dev_err(iep->dev, "failed to get aclk clock\n"); -+ return PTR_ERR(iep->axi_clk); -+ } -+ -+ iep->ahb_clk = devm_clk_get(iep->dev, "ahb"); -+ if (IS_ERR(iep->ahb_clk)) { -+ dev_err(iep->dev, "failed to get hclk clock\n"); -+ return PTR_ERR(iep->ahb_clk); -+ } -+ -+ ret = clk_set_rate(iep->axi_clk, 300000000); -+ -+ if (ret) -+ dev_err(iep->dev, "failed to set axi clock rate to 300 MHz\n"); -+ -+ return ret; -+} -+ -+static irqreturn_t iep_isr(int irq, void *prv) -+{ -+ struct rockchip_iep *iep = prv; -+ struct iep_ctx *ctx; -+ u32 val; -+ enum vb2_buffer_state state = VB2_BUF_STATE_DONE; -+ -+ ctx = v4l2_m2m_get_curr_priv(iep->m2m_dev); -+ if (!ctx) { -+ v4l2_err(&iep->v4l2_dev, -+ "Instance released before the end of transaction\n"); -+ return IRQ_NONE; -+ } -+ -+ /* -+ * The irq is shared with the iommu. If the runtime-pm state of the -+ * iep-device is disabled or the interrupt status doesn't match the -+ * expeceted mask the irq has been targeted to the iommu. -+ */ -+ -+ if (!pm_runtime_active(iep->dev) || -+ !(iep_read(iep, IEP_INT) & IEP_INT_MASK)) -+ return IRQ_NONE; -+ -+ /* disable interrupt - will be re-enabled at next iep_device_run */ -+ iep_mod(ctx->iep, IEP_INT, -+ IEP_INT_FRAME_DONE_EN, 0); -+ -+ iep_mod(iep, IEP_INT, IEP_INT_FRAME_DONE_CLR, -+ IEP_INT_FRAME_DONE_CLR); -+ -+ /* wait for all status regs to show "idle" */ -+ val = readl_poll_timeout(iep->regs + IEP_STATUS, val, -+ (val == 0), 100, IEP_TIMEOUT); -+ -+ if (val) { -+ dev_err(iep->dev, -+ "Failed to wait for job to finish: status: %u\n", val); -+ state = VB2_BUF_STATE_ERROR; -+ ctx->job_abort = true; -+ } -+ -+ iep_m2m_dst_bufs_done(ctx, state); -+ -+ ctx->field_bff = (ctx->dst_buffs_done % 2 == 0) -+ ? ctx->field_order_bff : !ctx->field_order_bff; -+ -+ if (ctx->dst_buffs_done == 2 || ctx->job_abort) { -+ if (ctx->prev_src_buf) -+ v4l2_m2m_buf_done(ctx->prev_src_buf, state); -+ -+ /* current src buff will be next prev */ -+ ctx->prev_src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); -+ -+ v4l2_m2m_job_finish(ctx->iep->m2m_dev, ctx->fh.m2m_ctx); -+ ctx->dst_buffs_done = 0; -+ -+ } else { -+ iep_device_run(ctx); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+static int iep_probe(struct platform_device *pdev) -+{ -+ struct rockchip_iep *iep; -+ struct video_device *vfd; -+ struct resource *res; -+ int ret = 0; -+ int irq; -+ -+ if (!pdev->dev.of_node) -+ return -ENODEV; -+ -+ iep = devm_kzalloc(&pdev->dev, sizeof(*iep), GFP_KERNEL); -+ if (!iep) -+ return -ENOMEM; -+ -+ platform_set_drvdata(pdev, iep); -+ iep->dev = &pdev->dev; -+ iep->vfd = iep_video_device; -+ -+ ret = iep_parse_dt(iep); -+ if (ret) -+ dev_err(&pdev->dev, "Unable to parse OF data\n"); -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ -+ iep->regs = devm_ioremap_resource(iep->dev, res); -+ if (IS_ERR(iep->regs)) { -+ ret = PTR_ERR(iep->regs); -+ goto err_put_clk; -+ } -+ -+ ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); -+ if (ret) { -+ dev_err(&pdev->dev, "Could not set DMA coherent mask.\n"); -+ goto err_put_clk; -+ } -+ -+ vb2_dma_contig_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32)); -+ -+ irq = platform_get_irq(pdev, 0); -+ if (irq < 0) { -+ ret = irq; -+ goto err_put_clk; -+ } -+ -+ /* IRQ is shared with IOMMU */ -+ ret = devm_request_irq(iep->dev, irq, iep_isr, IRQF_SHARED, -+ dev_name(iep->dev), iep); -+ if (ret < 0) { -+ dev_err(iep->dev, "failed to request irq\n"); -+ goto err_put_clk; -+ } -+ -+ mutex_init(&iep->mutex); -+ -+ ret = v4l2_device_register(&pdev->dev, &iep->v4l2_dev); -+ if (ret) { -+ dev_err(iep->dev, "Failed to register V4L2 device\n"); -+ -+ return ret; -+ } -+ -+ vfd = &iep->vfd; -+ vfd->lock = &iep->mutex; -+ vfd->v4l2_dev = &iep->v4l2_dev; -+ -+ snprintf(vfd->name, sizeof(vfd->name), "%s", -+ iep_video_device.name); -+ -+ video_set_drvdata(vfd, iep); -+ -+ ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0); -+ if (ret) { -+ v4l2_err(&iep->v4l2_dev, "Failed to register video device\n"); -+ -+ goto err_v4l2; -+ } -+ -+ v4l2_info(&iep->v4l2_dev, -+ "Device %s registered as /dev/video%d\n", vfd->name, vfd->num); -+ -+ iep->m2m_dev = v4l2_m2m_init(&iep_m2m_ops); -+ if (IS_ERR(iep->m2m_dev)) { -+ v4l2_err(&iep->v4l2_dev, -+ "Failed to initialize V4L2 M2M device\n"); -+ ret = PTR_ERR(iep->m2m_dev); -+ -+ goto err_video; -+ } -+ -+ pm_runtime_set_autosuspend_delay(iep->dev, 100); -+ pm_runtime_use_autosuspend(iep->dev); -+ pm_runtime_enable(iep->dev); -+ -+ return ret; -+ -+err_video: -+ video_unregister_device(&iep->vfd); -+err_v4l2: -+ v4l2_device_unregister(&iep->v4l2_dev); -+err_put_clk: -+ pm_runtime_dont_use_autosuspend(iep->dev); -+ pm_runtime_disable(iep->dev); -+ -+return ret; -+} -+ -+static int iep_remove(struct platform_device *pdev) -+{ -+ struct rockchip_iep *iep = platform_get_drvdata(pdev); -+ -+ pm_runtime_dont_use_autosuspend(iep->dev); -+ pm_runtime_disable(iep->dev); -+ -+ v4l2_m2m_release(iep->m2m_dev); -+ video_unregister_device(&iep->vfd); -+ v4l2_device_unregister(&iep->v4l2_dev); -+ -+ return 0; -+} -+ -+static int __maybe_unused iep_runtime_suspend(struct device *dev) -+{ -+ struct rockchip_iep *iep = dev_get_drvdata(dev); -+ -+ clk_disable_unprepare(iep->ahb_clk); -+ clk_disable_unprepare(iep->axi_clk); -+ -+ return 0; -+} -+ -+static int __maybe_unused iep_runtime_resume(struct device *dev) -+{ -+ struct rockchip_iep *iep; -+ int ret = 0; -+ -+ iep = dev_get_drvdata(dev); -+ -+ ret = clk_prepare_enable(iep->axi_clk); -+ if (ret) { -+ dev_err(iep->dev, "Cannot enable axi clock: %d\n", ret); -+ return ret; -+ } -+ -+ ret = clk_prepare_enable(iep->ahb_clk); -+ if (ret) { -+ dev_err(iep->dev, "Cannot enable ahb clock: %d\n", ret); -+ goto err_disable_axi_clk; -+ } -+ -+ return ret; -+ -+err_disable_axi_clk: -+ clk_disable_unprepare(iep->axi_clk); -+ return ret; -+} -+ -+static const struct dev_pm_ops iep_pm_ops = { -+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, -+ pm_runtime_force_resume) -+ SET_RUNTIME_PM_OPS(iep_runtime_suspend, -+ iep_runtime_resume, NULL) -+}; -+ -+static const struct of_device_id rockchip_iep_match[] = { -+ { -+ .compatible = "rockchip,rk3228-iep", -+ }, -+ {}, -+}; -+ -+MODULE_DEVICE_TABLE(of, rockchip_iep_match); -+ -+static struct platform_driver iep_pdrv = { -+ .probe = iep_probe, -+ .remove = iep_remove, -+ .driver = { -+ .name = IEP_NAME, -+ .pm = &iep_pm_ops, -+ .of_match_table = rockchip_iep_match, -+ }, -+}; -+ -+module_platform_driver(iep_pdrv); -+ -+MODULE_AUTHOR("Alex Bee "); -+MODULE_DESCRIPTION("Rockchip Image Enhancement Processor"); -+MODULE_LICENSE("GPL v2"); -diff -rupN linux.orig/drivers/media/platform/rockchip/iep/iep.h linux/drivers/media/platform/rockchip/iep/iep.h ---- linux.orig/drivers/media/platform/rockchip/iep/iep.h 1970-01-01 00:00:00.000000000 +0000 -+++ linux/drivers/media/platform/rockchip/iep/iep.h 2024-01-03 21:28:43.674043912 +0000 -@@ -0,0 +1,112 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Rockchip Image Enhancement Processor (IEP) driver -+ * -+ * Copyright (C) 2020 Alex Bee -+ * -+ */ -+#ifndef __IEP_H__ -+#define __IEP_H__ -+ -+#include -+#include -+#include -+#include -+ -+#define IEP_NAME "rockchip-iep" -+ -+/* Hardware limits */ -+#define IEP_MIN_WIDTH 320U -+#define IEP_MAX_WIDTH 1920U -+ -+#define IEP_MIN_HEIGHT 240U -+#define IEP_MAX_HEIGHT 1088U -+ -+/* Hardware defaults */ -+#define IEP_DEFAULT_WIDTH 320U -+#define IEP_DEFAULT_HEIGHT 240U -+ -+//ns -+#define IEP_TIMEOUT 250000 -+ -+struct iep_fmt { -+ u32 fourcc; -+ u8 depth; -+ u8 uv_factor; -+ u8 color_swap; -+ u8 hw_format; -+}; -+ -+struct iep_frm_fmt { -+ struct iep_fmt *hw_fmt; -+ struct v4l2_pix_format pix; -+ -+ unsigned int y_stride; -+ unsigned int uv_stride; -+}; -+ -+struct iep_ctx { -+ struct v4l2_fh fh; -+ struct rockchip_iep *iep; -+ -+ struct iep_frm_fmt src_fmt; -+ struct iep_frm_fmt dst_fmt; -+ -+ struct vb2_v4l2_buffer *prev_src_buf; -+ struct vb2_v4l2_buffer *dst0_buf; -+ struct vb2_v4l2_buffer *dst1_buf; -+ -+ u32 dst_sequence; -+ u32 src_sequence; -+ -+ /* bff = bottom field first */ -+ bool field_order_bff; -+ bool field_bff; -+ -+ unsigned int dst_buffs_done; -+ -+ bool fmt_changed; -+ bool job_abort; -+}; -+ -+struct rockchip_iep { -+ struct v4l2_device v4l2_dev; -+ struct v4l2_m2m_dev *m2m_dev; -+ struct video_device vfd; -+ -+ struct device *dev; -+ -+ void __iomem *regs; -+ -+ struct clk *axi_clk; -+ struct clk *ahb_clk; -+ -+ /* vfd lock */ -+ struct mutex mutex; -+}; -+ -+static inline void iep_write(struct rockchip_iep *iep, u32 reg, u32 value) -+{ -+ writel(value, iep->regs + reg); -+}; -+ -+static inline u32 iep_read(struct rockchip_iep *iep, u32 reg) -+{ -+ return readl(iep->regs + reg); -+}; -+ -+static inline void iep_shadow_mod(struct rockchip_iep *iep, u32 reg, -+ u32 shadow_reg, u32 mask, u32 val) -+{ -+ u32 temp = iep_read(iep, shadow_reg) & ~(mask); -+ -+ temp |= val & mask; -+ iep_write(iep, reg, temp); -+}; -+ -+static inline void iep_mod(struct rockchip_iep *iep, u32 reg, u32 mask, u32 val) -+{ -+ iep_shadow_mod(iep, reg, reg, mask, val); -+}; -+ -+#endif -diff -rupN linux.orig/drivers/media/platform/verisilicon/rockchip_vpu_hw.c linux/drivers/media/platform/verisilicon/rockchip_vpu_hw.c ---- linux.orig/drivers/media/platform/verisilicon/rockchip_vpu_hw.c 2024-01-03 20:53:30.815326981 +0000 -+++ linux/drivers/media/platform/verisilicon/rockchip_vpu_hw.c 2024-01-03 21:26:02.711011382 +0000 -@@ -15,7 +15,8 @@ - #include "rockchip_vpu2_regs.h" - - #define RK3066_ACLK_MAX_FREQ (300 * 1000 * 1000) --#define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000) -+#define RK3288_ACLK_MAX_FREQ (600 * 1000 * 1000) -+#define RK3399_ACLK_MAX_FREQ (400 * 1000 * 1000) - - /* - * Supported formats. -@@ -346,13 +347,20 @@ static int rk3066_vpu_hw_init(struct han - return 0; - } - --static int rockchip_vpu_hw_init(struct hantro_dev *vpu) -+static int rk3288_vpu_hw_init(struct hantro_dev *vpu) - { - /* Bump ACLK to max. possible freq. to improve performance. */ - clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ); - return 0; - } - -+static int rockchip_vpu_hw_init(struct hantro_dev *vpu) -+{ -+ /* Bump ACLK to max. possible freq. to improve performance. */ -+ clk_set_rate(vpu->clocks[0].clk, RK3399_ACLK_MAX_FREQ); -+ return 0; -+} -+ - static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx) - { - struct hantro_dev *vpu = ctx->dev; -@@ -592,7 +600,7 @@ const struct hantro_variant rk3288_vpu_v - .codec_ops = rk3288_vpu_codec_ops, - .irqs = rockchip_vpu1_irqs, - .num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs), -- .init = rockchip_vpu_hw_init, -+ .init = rk3288_vpu_hw_init, - .clk_names = rockchip_vpu_clk_names, - .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) - }; -diff -rupN linux.orig/drivers/media/v4l2-core/v4l2-common.c linux/drivers/media/v4l2-core/v4l2-common.c ---- linux.orig/drivers/media/v4l2-core/v4l2-common.c 2024-01-03 20:53:30.851327467 +0000 -+++ linux/drivers/media/v4l2-core/v4l2-common.c 2024-01-03 21:03:38.389716887 +0000 -@@ -268,6 +268,9 @@ const struct v4l2_format_info *v4l2_form - { .format = V4L2_PIX_FMT_NV42, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 1, .vdiv = 1 }, - { .format = V4L2_PIX_FMT_P010, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 2, 2, 0, 0 }, .hdiv = 2, .vdiv = 1 }, - -+ { .format = V4L2_PIX_FMT_NV15, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .hdiv = 2, .vdiv = 2, .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } }, -+ { .format = V4L2_PIX_FMT_NV20, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .hdiv = 2, .vdiv = 1, .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } }, -+ - { .format = V4L2_PIX_FMT_YUV410, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 4 }, - { .format = V4L2_PIX_FMT_YVU410, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 4 }, - { .format = V4L2_PIX_FMT_YUV411P, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 1 }, -@@ -338,6 +341,33 @@ static inline unsigned int v4l2_format_b - return info->block_h[plane]; - } - -+static inline unsigned int v4l2_format_plane_width(const struct v4l2_format_info *info, int plane, -+ unsigned int width) -+{ -+ unsigned int hdiv = plane ? info->hdiv : 1; -+ unsigned int bytes = DIV_ROUND_UP(width * info->bpp[plane], -+ v4l2_format_block_width(info, plane) * -+ v4l2_format_block_height(info, plane)); -+ -+ return DIV_ROUND_UP(bytes, hdiv); -+} -+ -+static inline unsigned int v4l2_format_plane_height(const struct v4l2_format_info *info, int plane, -+ unsigned int height) -+{ -+ unsigned int vdiv = plane ? info->vdiv : 1; -+ unsigned int lines = ALIGN(height, v4l2_format_block_height(info, plane)); -+ -+ return DIV_ROUND_UP(lines, vdiv); -+} -+ -+static inline unsigned int v4l2_format_plane_size(const struct v4l2_format_info *info, int plane, -+ unsigned int width, unsigned int height) -+{ -+ return v4l2_format_plane_width(info, plane, width) * -+ v4l2_format_plane_height(info, plane, height); -+} -+ - void v4l2_apply_frmsize_constraints(u32 *width, u32 *height, - const struct v4l2_frmsize_stepwise *frmsize) - { -@@ -373,37 +403,19 @@ int v4l2_fill_pixfmt_mp(struct v4l2_pix_ - - if (info->mem_planes == 1) { - plane = &pixfmt->plane_fmt[0]; -- plane->bytesperline = ALIGN(width, v4l2_format_block_width(info, 0)) * info->bpp[0]; -+ plane->bytesperline = v4l2_format_plane_width(info, 0, width); - plane->sizeimage = 0; - -- for (i = 0; i < info->comp_planes; i++) { -- unsigned int hdiv = (i == 0) ? 1 : info->hdiv; -- unsigned int vdiv = (i == 0) ? 1 : info->vdiv; -- unsigned int aligned_width; -- unsigned int aligned_height; -- -- aligned_width = ALIGN(width, v4l2_format_block_width(info, i)); -- aligned_height = ALIGN(height, v4l2_format_block_height(info, i)); -- -- plane->sizeimage += info->bpp[i] * -- DIV_ROUND_UP(aligned_width, hdiv) * -- DIV_ROUND_UP(aligned_height, vdiv); -- } -+ for (i = 0; i < info->comp_planes; i++) -+ plane->sizeimage += -+ v4l2_format_plane_size(info, i, width, height); - } else { - for (i = 0; i < info->comp_planes; i++) { -- unsigned int hdiv = (i == 0) ? 1 : info->hdiv; -- unsigned int vdiv = (i == 0) ? 1 : info->vdiv; -- unsigned int aligned_width; -- unsigned int aligned_height; -- -- aligned_width = ALIGN(width, v4l2_format_block_width(info, i)); -- aligned_height = ALIGN(height, v4l2_format_block_height(info, i)); -- - plane = &pixfmt->plane_fmt[i]; - plane->bytesperline = -- info->bpp[i] * DIV_ROUND_UP(aligned_width, hdiv); -- plane->sizeimage = -- plane->bytesperline * DIV_ROUND_UP(aligned_height, vdiv); -+ v4l2_format_plane_width(info, i, width); -+ plane->sizeimage = plane->bytesperline * -+ v4l2_format_plane_height(info, i, height); - } - } - return 0; -@@ -427,22 +439,12 @@ int v4l2_fill_pixfmt(struct v4l2_pix_for - pixfmt->width = width; - pixfmt->height = height; - pixfmt->pixelformat = pixelformat; -- pixfmt->bytesperline = ALIGN(width, v4l2_format_block_width(info, 0)) * info->bpp[0]; -+ pixfmt->bytesperline = v4l2_format_plane_width(info, 0, width); - pixfmt->sizeimage = 0; - -- for (i = 0; i < info->comp_planes; i++) { -- unsigned int hdiv = (i == 0) ? 1 : info->hdiv; -- unsigned int vdiv = (i == 0) ? 1 : info->vdiv; -- unsigned int aligned_width; -- unsigned int aligned_height; -- -- aligned_width = ALIGN(width, v4l2_format_block_width(info, i)); -- aligned_height = ALIGN(height, v4l2_format_block_height(info, i)); -- -- pixfmt->sizeimage += info->bpp[i] * -- DIV_ROUND_UP(aligned_width, hdiv) * -- DIV_ROUND_UP(aligned_height, vdiv); -- } -+ for (i = 0; i < info->comp_planes; i++) -+ pixfmt->sizeimage += -+ v4l2_format_plane_size(info, i, width, height); - return 0; - } - EXPORT_SYMBOL_GPL(v4l2_fill_pixfmt); -diff -rupN linux.orig/drivers/media/v4l2-core/v4l2-ioctl.c linux/drivers/media/v4l2-core/v4l2-ioctl.c ---- linux.orig/drivers/media/v4l2-core/v4l2-ioctl.c 2024-01-03 20:53:30.851327467 +0000 -+++ linux/drivers/media/v4l2-core/v4l2-ioctl.c 2024-01-03 21:03:38.389716887 +0000 -@@ -1354,6 +1354,8 @@ static void v4l_fill_fmtdesc(struct v4l2 - case V4L2_PIX_FMT_NV24: descr = "Y/UV 4:4:4"; break; - case V4L2_PIX_FMT_NV42: descr = "Y/VU 4:4:4"; break; - case V4L2_PIX_FMT_P010: descr = "10-bit Y/UV 4:2:0"; break; -+ case V4L2_PIX_FMT_NV15: descr = "10-bit Y/UV 4:2:0 (Packed)"; break; -+ case V4L2_PIX_FMT_NV20: descr = "10-bit Y/UV 4:2:2 (Packed)"; break; - case V4L2_PIX_FMT_NV12_4L4: descr = "Y/UV 4:2:0 (4x4 Linear)"; break; - case V4L2_PIX_FMT_NV12_16L16: descr = "Y/UV 4:2:0 (16x16 Linear)"; break; - case V4L2_PIX_FMT_NV12_32L32: descr = "Y/UV 4:2:0 (32x32 Linear)"; break; -diff -rupN linux.orig/drivers/mmc/core/core.c linux/drivers/mmc/core/core.c ---- linux.orig/drivers/mmc/core/core.c 2024-01-03 20:53:30.907328224 +0000 -+++ linux/drivers/mmc/core/core.c 2024-01-03 21:32:47.747235430 +0000 -@@ -1369,6 +1369,14 @@ void mmc_power_off(struct mmc_host *host - if (host->ios.power_mode == MMC_POWER_OFF) - return; - -+ mmc_set_initial_signal_voltage(host); -+ -+ /* -+ * This delay should be sufficient to allow the power supply -+ * to reach the minimum voltage. -+ */ -+ mmc_delay(host->ios.power_delay_ms); -+ - mmc_pwrseq_power_off(host); - - host->ios.clock = 0; -diff -rupN linux.orig/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c linux/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c ---- linux.orig/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c 2024-01-03 20:53:31.235332660 +0000 -+++ linux/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c 2024-01-03 21:32:47.747235430 +0000 -@@ -245,6 +245,7 @@ struct inno_hdmi_phy { - struct clk_hw hw; - struct clk *phyclk; - unsigned long pixclock; -+ unsigned long tmdsclock; - }; - - struct pre_pll_config { -@@ -291,31 +292,179 @@ struct inno_hdmi_phy_drv_data { - }; - - static const struct pre_pll_config pre_pll_cfg_table[] = { -- { 27000000, 27000000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0}, -- { 27000000, 33750000, 1, 90, 1, 3, 3, 10, 3, 3, 4, 0, 0}, -- { 40000000, 40000000, 1, 80, 2, 2, 2, 12, 2, 2, 2, 0, 0}, -- { 59341000, 59341000, 1, 98, 3, 1, 2, 1, 3, 3, 4, 0, 0xE6AE6B}, -- { 59400000, 59400000, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0}, -- { 59341000, 74176250, 1, 98, 0, 3, 3, 1, 3, 3, 4, 0, 0xE6AE6B}, -- { 59400000, 74250000, 1, 99, 1, 2, 2, 1, 3, 3, 4, 0, 0}, -- { 74176000, 74176000, 1, 98, 1, 2, 2, 1, 2, 3, 4, 0, 0xE6AE6B}, -- { 74250000, 74250000, 1, 99, 1, 2, 2, 1, 2, 3, 4, 0, 0}, -- { 74176000, 92720000, 4, 494, 1, 2, 2, 1, 3, 3, 4, 0, 0x816817}, -- { 74250000, 92812500, 4, 495, 1, 2, 2, 1, 3, 3, 4, 0, 0}, -- {148352000, 148352000, 1, 98, 1, 1, 1, 1, 2, 2, 2, 0, 0xE6AE6B}, -- {148500000, 148500000, 1, 99, 1, 1, 1, 1, 2, 2, 2, 0, 0}, -- {148352000, 185440000, 4, 494, 0, 2, 2, 1, 3, 2, 2, 0, 0x816817}, -- {148500000, 185625000, 4, 495, 0, 2, 2, 1, 3, 2, 2, 0, 0}, -- {296703000, 296703000, 1, 98, 0, 1, 1, 1, 0, 2, 2, 0, 0xE6AE6B}, -- {297000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0}, -- {296703000, 370878750, 4, 494, 1, 2, 0, 1, 3, 1, 1, 0, 0x816817}, -- {297000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 0, 0}, -- {593407000, 296703500, 1, 98, 0, 1, 1, 1, 0, 2, 1, 0, 0xE6AE6B}, -- {594000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 1, 0, 0}, -- {593407000, 370879375, 4, 494, 1, 2, 0, 1, 3, 1, 1, 1, 0x816817}, -- {594000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 1, 0}, -- {593407000, 593407000, 1, 98, 0, 2, 0, 1, 0, 1, 1, 0, 0xE6AE6B}, -- {594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0}, -+ { 25175000, 25175000, 3, 125, 3, 1, 1, 1, 3, 3, 4, 0, 0xe00000}, -+ { 25175000, 31468750, 1, 41, 0, 3, 3, 1, 3, 3, 4, 0, 0xf5554f}, -+ { 27000000, 27000000, 1, 36, 0, 3, 3, 1, 2, 3, 4, 0, 0x0}, -+ { 27000000, 33750000, 1, 45, 0, 3, 3, 1, 3, 3, 4, 0, 0x0}, -+ { 31500000, 31500000, 1, 42, 0, 3, 3, 1, 2, 3, 4, 0, 0x0}, -+ { 31500000, 39375000, 1, 105, 1, 3, 3, 10, 0, 3, 4, 0, 0x0}, -+ { 33750000, 33750000, 1, 45, 0, 3, 3, 1, 2, 3, 4, 0, 0x0}, -+ { 33750000, 42187500, 1, 169, 2, 3, 3, 15, 0, 3, 4, 0, 0x0}, -+ { 35500000, 35500000, 1, 71, 2, 2, 2, 6, 0, 3, 4, 0, 0x0}, -+ { 35500000, 44375000, 1, 74, 3, 1, 1, 25, 0, 1, 1, 0, 0x0}, -+ { 36000000, 36000000, 1, 36, 2, 1, 1, 1, 1, 3, 4, 0, 0x0}, -+ { 36000000, 45000000, 1, 45, 2, 1, 1, 15, 0, 1, 1, 0, 0x0}, -+ { 40000000, 40000000, 1, 40, 2, 1, 1, 1, 1, 3, 4, 0, 0x0}, -+ { 40000000, 50000000, 1, 50, 2, 1, 1, 15, 0, 1, 1, 0, 0x0}, -+ { 49500000, 49500000, 1, 66, 0, 3, 3, 1, 2, 3, 4, 0, 0x0}, -+ { 49500000, 61875000, 1, 165, 1, 3, 3, 10, 0, 3, 4, 0, 0x0}, -+ { 50000000, 50000000, 1, 50, 2, 1, 1, 1, 1, 3, 4, 0, 0x0}, -+ { 50000000, 62500000, 1, 125, 2, 2, 2, 15, 0, 2, 2, 0, 0x0}, -+ { 54000000, 54000000, 1, 36, 0, 2, 2, 1, 0, 3, 4, 0, 0x0}, -+ { 54000000, 67500000, 1, 45, 0, 2, 2, 1, 3, 2, 2, 0, 0x0}, -+ { 56250000, 56250000, 1, 75, 0, 3, 3, 1, 2, 3, 4, 0, 0x0}, -+ { 56250000, 70312500, 1, 117, 3, 1, 1, 25, 0, 1, 1, 0, 0x0}, -+ { 59341000, 59341000, 1, 118, 2, 2, 2, 6, 0, 3, 4, 0, 0xae978d}, -+ { 59341000, 74176250, 2, 148, 2, 1, 1, 15, 0, 1, 1, 0, 0x5a3d70}, -+ { 59400000, 59400000, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0x0}, -+ { 59400000, 74250000, 1, 99, 0, 3, 3, 1, 3, 3, 4, 0, 0x0}, -+ { 65000000, 65000000, 1, 65, 2, 1, 1, 1, 1, 3, 4, 0, 0x0}, -+ { 65000000, 81250000, 3, 325, 0, 3, 3, 1, 3, 3, 4, 0, 0x0}, -+ { 68250000, 68250000, 1, 91, 0, 3, 3, 1, 2, 3, 4, 0, 0x0}, -+ { 68250000, 85312500, 1, 142, 3, 1, 1, 25, 0, 1, 1, 0, 0x0}, -+ { 71000000, 71000000, 1, 71, 2, 1, 1, 1, 1, 3, 4, 0, 0x0}, -+ { 71000000, 88750000, 3, 355, 0, 3, 3, 1, 3, 3, 4, 0, 0x0}, -+ { 72000000, 72000000, 1, 36, 2, 0, 0, 1, 1, 2, 2, 0, 0x0}, -+ { 72000000, 90000000, 1, 60, 0, 2, 2, 1, 3, 2, 2, 0, 0x0}, -+ { 73250000, 73250000, 3, 293, 0, 3, 3, 1, 2, 3, 4, 0, 0x0}, -+ { 73250000, 91562500, 1, 61, 0, 2, 2, 1, 3, 2, 2, 0, 0x0}, -+ { 74176000, 74176000, 1, 37, 2, 0, 0, 1, 1, 2, 2, 0, 0x16872b}, -+ { 74176000, 92720000, 2, 185, 2, 1, 1, 15, 0, 1, 1, 0, 0x70a3d7}, -+ { 74250000, 74250000, 1, 99, 0, 3, 3, 1, 2, 3, 4, 0, 0x0}, -+ { 74250000, 92812500, 4, 495, 0, 3, 3, 1, 3, 3, 4, 0, 0x0}, -+ { 75000000, 75000000, 1, 50, 0, 2, 2, 1, 0, 3, 4, 0, 0x0}, -+ { 75000000, 93750000, 1, 125, 0, 3, 3, 1, 3, 3, 4, 0, 0x0}, -+ { 78750000, 78750000, 1, 105, 0, 3, 3, 1, 2, 3, 4, 0, 0x0}, -+ { 78750000, 98437500, 1, 164, 3, 1, 1, 25, 0, 1, 1, 0, 0x0}, -+ { 79500000, 79500000, 1, 53, 0, 2, 2, 1, 0, 3, 4, 0, 0x0}, -+ { 79500000, 99375000, 1, 199, 2, 2, 2, 15, 0, 2, 2, 0, 0x0}, -+ { 83500000, 83500000, 2, 167, 2, 1, 1, 1, 1, 3, 4, 0, 0x0}, -+ { 83500000, 104375000, 1, 104, 2, 1, 1, 15, 0, 1, 1, 0, 0x600000}, -+ { 85500000, 85500000, 1, 57, 0, 2, 2, 1, 0, 3, 4, 0, 0x0}, -+ { 85500000, 106875000, 1, 178, 3, 1, 1, 25, 0, 1, 1, 0, 0x0}, -+ { 85750000, 85750000, 3, 343, 0, 3, 3, 1, 2, 3, 4, 0, 0x0}, -+ { 85750000, 107187500, 1, 143, 0, 3, 3, 1, 3, 3, 4, 0, 0x0}, -+ { 88750000, 88750000, 3, 355, 0, 3, 3, 1, 2, 3, 4, 0, 0x0}, -+ { 88750000, 110937500, 1, 110, 2, 1, 1, 15, 0, 1, 1, 0, 0xf00000}, -+ { 94500000, 94500000, 1, 63, 0, 2, 2, 1, 0, 3, 4, 0, 0x0}, -+ { 94500000, 118125000, 1, 197, 3, 1, 1, 25, 0, 1, 1, 0, 0x0}, -+ {101000000, 101000000, 1, 101, 2, 1, 1, 1, 1, 3, 4, 0, 0x0}, -+ {101000000, 126250000, 1, 42, 0, 1, 1, 1, 3, 1, 1, 0, 0x0}, -+ {102250000, 102250000, 4, 409, 2, 1, 1, 1, 1, 3, 4, 0, 0x0}, -+ {102250000, 127812500, 1, 128, 2, 1, 1, 15, 0, 1, 1, 0, 0x0}, -+ {106500000, 106500000, 1, 71, 0, 2, 2, 1, 0, 3, 4, 0, 0x0}, -+ {106500000, 133125000, 1, 133, 2, 1, 1, 15, 0, 1, 1, 0, 0x0}, -+ {108000000, 108000000, 1, 36, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, -+ {108000000, 135000000, 1, 45, 0, 1, 1, 1, 3, 1, 1, 0, 0x0}, -+ {115500000, 115500000, 1, 77, 0, 2, 2, 1, 0, 3, 4, 0, 0x0}, -+ {115500000, 144375000, 1, 48, 0, 1, 1, 1, 3, 1, 1, 0, 0x0}, -+ {117500000, 117500000, 2, 235, 2, 1, 1, 1, 1, 3, 4, 0, 0x0}, -+ {117500000, 146875000, 1, 49, 0, 1, 1, 1, 3, 1, 1, 0, 0x0}, -+ {119000000, 119000000, 1, 119, 2, 1, 1, 1, 1, 3, 4, 0, 0x0}, -+ {119000000, 148750000, 3, 148, 0, 1, 1, 1, 3, 1, 1, 0, 0xc00000}, -+ {121750000, 121750000, 4, 487, 2, 1, 1, 1, 1, 3, 4, 0, 0x0}, -+ {121750000, 152187500, 1, 203, 0, 3, 3, 1, 3, 3, 4, 0, 0x0}, -+ {122500000, 122500000, 2, 245, 2, 1, 1, 1, 1, 3, 4, 0, 0x0}, -+ {122500000, 153125000, 1, 51, 0, 1, 1, 1, 3, 1, 1, 0, 0x0}, -+ {135000000, 135000000, 1, 45, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, -+ {135000000, 168750000, 1, 169, 2, 1, 1, 15, 0, 1, 1, 0, 0x0}, -+ {136750000, 136750000, 1, 68, 2, 0, 0, 1, 1, 2, 2, 0, 0x600000}, -+ {136750000, 170937500, 1, 113, 0, 2, 2, 1, 3, 2, 2, 0, 0xf5554f}, -+ {140250000, 140250000, 2, 187, 0, 2, 2, 1, 0, 3, 4, 0, 0x0}, -+ {140250000, 175312500, 1, 117, 0, 2, 2, 1, 3, 2, 2, 0, 0x0}, -+ {146250000, 146250000, 2, 195, 0, 2, 2, 1, 0, 3, 4, 0, 0x0}, -+ {146250000, 182812500, 1, 61, 0, 1, 1, 1, 3, 1, 1, 0, 0x0}, -+ {148250000, 148250000, 3, 222, 2, 0, 0, 1, 1, 2, 2, 0, 0x600000}, -+ {148250000, 185312500, 1, 123, 0, 2, 2, 1, 3, 2, 2, 0, 0x8aaab0}, -+ {148352000, 148352000, 2, 148, 2, 0, 0, 1, 1, 2, 2, 0, 0x5a1cac}, -+ {148352000, 185440000, 3, 185, 0, 1, 1, 1, 3, 1, 1, 0, 0x70a3d7}, -+ {148500000, 148500000, 1, 99, 0, 2, 2, 1, 0, 3, 4, 0, 0x0}, -+ {148500000, 185625000, 4, 495, 0, 2, 2, 1, 3, 2, 2, 0, 0x0}, -+ {154000000, 154000000, 1, 77, 2, 0, 0, 1, 1, 2, 2, 0, 0x0}, -+ {154000000, 192500000, 1, 64, 0, 1, 1, 1, 3, 1, 1, 0, 0x0}, -+ {156000000, 156000000, 1, 52, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, -+ {156000000, 195000000, 1, 65, 0, 1, 1, 1, 3, 1, 1, 0, 0x0}, -+ {156750000, 156750000, 2, 209, 0, 2, 2, 1, 0, 3, 4, 0, 0x0}, -+ {156750000, 195937500, 1, 196, 2, 1, 1, 15, 0, 1, 1, 0, 0x0}, -+ {157000000, 157000000, 2, 157, 2, 0, 0, 1, 1, 2, 2, 0, 0x0}, -+ {157000000, 196250000, 1, 131, 0, 2, 2, 1, 3, 2, 2, 0, 0x0}, -+ {157500000, 157500000, 1, 105, 0, 2, 2, 1, 0, 3, 4, 0, 0x0}, -+ {157500000, 196875000, 1, 197, 2, 1, 1, 15, 0, 1, 1, 0, 0x0}, -+ {162000000, 162000000, 1, 54, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, -+ {162000000, 202500000, 2, 135, 0, 1, 1, 1, 3, 1, 1, 0, 0x0}, -+ {175500000, 175500000, 1, 117, 0, 2, 2, 1, 0, 3, 4, 0, 0x0}, -+ {175500000, 219375000, 1, 73, 0, 1, 1, 1, 3, 1, 1, 0, 0x0}, -+ {179500000, 179500000, 3, 359, 0, 2, 2, 1, 0, 3, 4, 0, 0x0}, -+ {179500000, 224375000, 1, 75, 0, 1, 1, 1, 3, 1, 1, 0, 0x0}, -+ {182750000, 182750000, 1, 91, 2, 0, 0, 1, 1, 2, 2, 0, 0x600000}, -+ {182750000, 228437500, 1, 152, 0, 2, 2, 1, 3, 2, 2, 0, 0x4aaab0}, -+ {182750000, 228437500, 1, 152, 0, 2, 2, 1, 3, 2, 2, 0, 0x4aaab0}, -+ {187000000, 187000000, 2, 187, 2, 0, 0, 1, 1, 2, 2, 0, 0x0}, -+ {187000000, 233750000, 1, 39, 0, 0, 0, 1, 3, 0, 0, 1, 0x0}, -+ {187250000, 187250000, 3, 280, 2, 0, 0, 1, 1, 2, 2, 0, 0xe00000}, -+ {187250000, 234062500, 1, 156, 0, 2, 2, 1, 3, 2, 2, 0, 0xaaab0}, -+ {189000000, 189000000, 1, 63, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, -+ {189000000, 236250000, 1, 79, 0, 1, 1, 1, 3, 1, 1, 0, 0x0}, -+ {193250000, 193250000, 3, 289, 2, 0, 0, 1, 1, 2, 2, 0, 0xe00000}, -+ {193250000, 241562500, 1, 161, 0, 2, 2, 1, 3, 2, 2, 0, 0xaaab0}, -+ {202500000, 202500000, 2, 135, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, -+ {202500000, 253125000, 1, 169, 0, 2, 2, 1, 3, 2, 2, 0, 0x0}, -+ {204750000, 204750000, 4, 273, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, -+ {204750000, 255937500, 1, 171, 0, 2, 2, 1, 3, 2, 2, 0, 0x0}, -+ {208000000, 208000000, 1, 104, 2, 0, 0, 1, 1, 2, 2, 0, 0x0}, -+ {208000000, 260000000, 1, 173, 0, 2, 2, 1, 3, 2, 2, 0, 0x0}, -+ {214750000, 214750000, 1, 107, 2, 0, 0, 1, 1, 2, 2, 0, 0x600000}, -+ {214750000, 268437500, 1, 178, 0, 2, 2, 1, 3, 2, 2, 0, 0xf5554f}, -+ {218250000, 218250000, 4, 291, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, -+ {218250000, 272812500, 1, 91, 0, 1, 1, 1, 3, 1, 1, 0, 0x0}, -+ {229500000, 229500000, 2, 153, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, -+ {229500000, 286875000, 1, 191, 0, 2, 2, 1, 3, 2, 2, 0, 0x0}, -+ {234000000, 234000000, 1, 39, 0, 0, 0, 1, 0, 1, 1, 0, 0x0}, -+ {234000000, 292500000, 1, 195, 0, 2, 2, 1, 3, 2, 2, 0, 0x0}, -+ {241500000, 241500000, 2, 161, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, -+ {241500000, 301875000, 1, 201, 0, 2, 2, 1, 3, 2, 2, 0, 0x0}, -+ {245250000, 245250000, 4, 327, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, -+ {245250000, 306562500, 1, 51, 0, 0, 0, 1, 3, 0, 0, 1, 0x0}, -+ {245500000, 245500000, 4, 491, 2, 0, 0, 1, 1, 2, 2, 0, 0x0}, -+ {245500000, 306875000, 1, 51, 0, 0, 0, 1, 3, 0, 0, 1, 0x0}, -+ {261000000, 261000000, 1, 87, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, -+ {261000000, 326250000, 1, 109, 0, 1, 1, 1, 3, 1, 1, 0, 0x0}, -+ {268250000, 268250000, 9, 402, 0, 0, 0, 1, 0, 1, 1, 0, 0x600000}, -+ {268250000, 335312500, 1, 111, 0, 1, 1, 1, 3, 1, 1, 0, 0xc5554f}, -+ {268500000, 268500000, 2, 179, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, -+ {268500000, 335625000, 1, 56, 0, 0, 0, 1, 3, 0, 0, 1, 0x0}, -+ {281250000, 281250000, 4, 375, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, -+ {281250000, 351562500, 1, 117, 0, 3, 1, 1, 3, 1, 1, 0, 0x0}, -+ {288000000, 288000000, 1, 48, 0, 0, 0, 1, 0, 1, 1, 0, 0x0}, -+ {288000000, 360000000, 1, 60, 0, 2, 0, 1, 3, 0, 0, 1, 0x0}, -+ {296703000, 296703000, 1, 49, 0, 0, 0, 1, 0, 1, 1, 0, 0x7353f7}, -+ {296703000, 370878750, 1, 123, 0, 3, 1, 1, 3, 1, 1, 0, 0xa051eb}, -+ {297000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, -+ {297000000, 371250000, 4, 495, 0, 3, 1, 1, 3, 1, 1, 0, 0x0}, -+ {312250000, 312250000, 9, 468, 0, 0, 0, 1, 0, 1, 1, 0, 0x600000}, -+ {312250000, 390312500, 1, 130, 0, 3, 1, 1, 3, 1, 1, 0, 0x1aaab0}, -+ {317000000, 317000000, 3, 317, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, -+ {317000000, 396250000, 1, 66, 0, 2, 0, 1, 3, 0, 0, 1, 0x0}, -+ {319750000, 319750000, 3, 159, 0, 0, 0, 1, 0, 1, 1, 0, 0xe00000}, -+ {319750000, 399687500, 3, 199, 0, 2, 0, 1, 3, 0, 0, 1, 0xd80000}, -+ {333250000, 333250000, 9, 499, 0, 0, 0, 1, 0, 1, 1, 0, 0xe00000}, -+ {333250000, 416562500, 1, 138, 0, 3, 1, 1, 3, 1, 1, 0, 0xdaaab0}, -+ {348500000, 348500000, 9, 522, 0, 2, 0, 1, 0, 1, 1, 0, 0xc00000}, -+ {348500000, 435625000, 1, 145, 0, 3, 1, 1, 3, 1, 1, 0, 0x35554f}, -+ {356500000, 356500000, 9, 534, 0, 2, 0, 1, 0, 1, 1, 0, 0xc00000}, -+ {356500000, 445625000, 1, 148, 0, 3, 1, 1, 3, 1, 1, 0, 0x8aaab0}, -+ {380500000, 380500000, 9, 570, 0, 2, 0, 1, 0, 1, 1, 0, 0xc00000}, -+ {380500000, 475625000, 1, 158, 0, 3, 1, 1, 3, 1, 1, 0, 0x8aaab0}, -+ {443250000, 443250000, 1, 73, 0, 2, 0, 1, 0, 1, 1, 0, 0xe00000}, -+ {443250000, 554062500, 1, 92, 0, 2, 0, 1, 3, 0, 0, 1, 0x580000}, -+ {505250000, 505250000, 9, 757, 0, 2, 0, 1, 0, 1, 1, 0, 0xe00000}, -+ {552750000, 552750000, 3, 276, 0, 2, 0, 1, 0, 1, 1, 0, 0x600000}, -+ {593407000, 296703500, 3, 296, 0, 1, 1, 1, 0, 1, 1, 0, 0xb41893}, -+ {593407000, 370879375, 4, 494, 0, 3, 1, 1, 3, 0, 0, 1, 0x817e4a}, -+ {593407000, 593407000, 3, 296, 0, 2, 0, 1, 0, 1, 1, 0, 0xb41893}, -+ {594000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 1, 1, 0, 0x0}, -+ {594000000, 371250000, 4, 495, 0, 3, 1, 1, 3, 0, 0, 1, 0x0}, -+ {594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0x0}, - { /* sentinel */ } - }; - -@@ -485,6 +634,8 @@ static int inno_hdmi_phy_power_on(struct - - dev_dbg(inno->dev, "Inno HDMI PHY Power On\n"); - -+ inno->plat_data->clk_ops->set_rate(&inno->hw, inno->pixclock, 24000000); -+ - ret = clk_prepare_enable(inno->phyclk); - if (ret) - return ret; -@@ -509,6 +660,8 @@ static int inno_hdmi_phy_power_off(struc - - clk_disable_unprepare(inno->phyclk); - -+ inno->tmdsclock = 0; -+ - dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n"); - - return 0; -@@ -628,6 +781,9 @@ static int inno_hdmi_phy_rk3228_clk_set_ - dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", - __func__, rate, tmdsclock); - -+ if (inno->pixclock == rate && inno->tmdsclock == tmdsclock) -+ return 0; -+ - cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate); - if (IS_ERR(cfg)) - return PTR_ERR(cfg); -@@ -670,6 +826,7 @@ static int inno_hdmi_phy_rk3228_clk_set_ - } - - inno->pixclock = rate; -+ inno->tmdsclock = tmdsclock; - - return 0; - } -@@ -714,7 +871,7 @@ unsigned long inno_hdmi_phy_rk3328_clk_r - { - struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw); - unsigned long frac; -- u8 nd, no_a, no_b, no_c, no_d; -+ u8 nd, no_a, no_b, no_d; - u64 vco; - u16 nf; - -@@ -737,9 +894,6 @@ unsigned long inno_hdmi_phy_rk3328_clk_r - no_b = inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_B_MASK; - no_b >>= RK3328_PRE_PLL_PCLK_DIV_B_SHIFT; - no_b += 2; -- no_c = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_C_MASK; -- no_c >>= RK3328_PRE_PLL_PCLK_DIV_C_SHIFT; -- no_c = 1 << no_c; - no_d = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_D_MASK; - - do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2)); -@@ -784,6 +938,9 @@ static int inno_hdmi_phy_rk3328_clk_set_ - dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", - __func__, rate, tmdsclock); - -+ if (inno->pixclock == rate && inno->tmdsclock == tmdsclock) -+ return 0; -+ - cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate); - if (IS_ERR(cfg)) - return PTR_ERR(cfg); -@@ -823,6 +980,7 @@ static int inno_hdmi_phy_rk3328_clk_set_ - } - - inno->pixclock = rate; -+ inno->tmdsclock = tmdsclock; - - return 0; - } -diff -rupN linux.orig/drivers/soc/rockchip/pm_domains.c linux/drivers/soc/rockchip/pm_domains.c ---- linux.orig/drivers/soc/rockchip/pm_domains.c 2024-01-03 20:53:31.383334661 +0000 -+++ linux/drivers/soc/rockchip/pm_domains.c 2024-01-03 21:26:02.707011192 +0000 -@@ -338,6 +338,29 @@ static int rockchip_pmu_set_idle_request - return 0; - } - -+int rockchip_pmu_idle_request(struct device *dev, bool idle) -+{ -+ struct generic_pm_domain *genpd; -+ struct rockchip_pm_domain *pd; -+ int ret; -+ -+ if (IS_ERR_OR_NULL(dev)) -+ return -EINVAL; -+ -+ if (IS_ERR_OR_NULL(dev->pm_domain)) -+ return -EINVAL; -+ -+ genpd = pd_to_genpd(dev->pm_domain); -+ pd = to_rockchip_pd(genpd); -+ -+ mutex_lock(&pd->pmu->mutex); -+ ret = rockchip_pmu_set_idle_request(pd, idle); -+ mutex_unlock(&pd->pmu->mutex); -+ -+ return ret; -+} -+EXPORT_SYMBOL(rockchip_pmu_idle_request); -+ - static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd) - { - int i; -diff -rupN linux.orig/drivers/staging/media/rkvdec/Kconfig linux/drivers/staging/media/rkvdec/Kconfig ---- linux.orig/drivers/staging/media/rkvdec/Kconfig 2024-01-03 20:53:31.439335419 +0000 -+++ linux/drivers/staging/media/rkvdec/Kconfig 2024-01-03 21:33:30.116696710 +0000 -@@ -1,7 +1,7 @@ - # SPDX-License-Identifier: GPL-2.0 - config VIDEO_ROCKCHIP_VDEC - tristate "Rockchip Video Decoder driver" -- depends on ARCH_ROCKCHIP || COMPILE_TEST -+ depends on ARCH_ROCKCHIP - depends on VIDEO_DEV - select MEDIA_CONTROLLER - select MEDIA_CONTROLLER_REQUEST_API -diff -rupN linux.orig/drivers/staging/media/rkvdec/Makefile linux/drivers/staging/media/rkvdec/Makefile ---- linux.orig/drivers/staging/media/rkvdec/Makefile 2024-01-03 20:53:31.439335419 +0000 -+++ linux/drivers/staging/media/rkvdec/Makefile 2024-01-03 21:27:48.647744137 +0000 -@@ -1,3 +1,3 @@ - obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rockchip-vdec.o - --rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-vp9.o -+rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-hevc.o rkvdec-vp9.o -diff -rupN linux.orig/drivers/staging/media/rkvdec/rkvdec-h264.c linux/drivers/staging/media/rkvdec/rkvdec-h264.c ---- linux.orig/drivers/staging/media/rkvdec/rkvdec-h264.c 2024-01-03 20:53:31.439335419 +0000 -+++ linux/drivers/staging/media/rkvdec/rkvdec-h264.c 2024-01-03 21:03:38.389716887 +0000 -@@ -655,13 +655,14 @@ static void assemble_hw_pps(struct rkvde - - #define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value) - /* write sps */ -- WRITE_PPS(0xf, SEQ_PARAMETER_SET_ID); -- WRITE_PPS(0xff, PROFILE_IDC); -- WRITE_PPS(1, CONSTRAINT_SET3_FLAG); -+ WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID); -+ WRITE_PPS(sps->profile_idc, PROFILE_IDC); -+ WRITE_PPS((sps->constraint_set_flags & 1 << 3) ? 1 : 0, CONSTRAINT_SET3_FLAG); - WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC); - WRITE_PPS(sps->bit_depth_luma_minus8, BIT_DEPTH_LUMA); - WRITE_PPS(sps->bit_depth_chroma_minus8, BIT_DEPTH_CHROMA); -- WRITE_PPS(0, QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG); -+ WRITE_PPS(!!(sps->flags & V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS), -+ QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG); - WRITE_PPS(sps->log2_max_frame_num_minus4, LOG2_MAX_FRAME_NUM_MINUS4); - WRITE_PPS(sps->max_num_ref_frames, MAX_NUM_REF_FRAMES); - WRITE_PPS(sps->pic_order_cnt_type, PIC_ORDER_CNT_TYPE); -@@ -688,8 +689,8 @@ static void assemble_hw_pps(struct rkvde - DIRECT_8X8_INFERENCE_FLAG); - - /* write pps */ -- WRITE_PPS(0xff, PIC_PARAMETER_SET_ID); -- WRITE_PPS(0x1f, PPS_SEQ_PARAMETER_SET_ID); -+ WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID); -+ WRITE_PPS(pps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID); - WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE), - ENTROPY_CODING_MODE_FLAG); - WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT), -@@ -896,9 +897,9 @@ static void config_registers(struct rkvd - dma_addr_t rlc_addr; - dma_addr_t refer_addr; - u32 rlc_len; -- u32 hor_virstride = 0; -- u32 ver_virstride = 0; -- u32 y_virstride = 0; -+ u32 hor_virstride; -+ u32 ver_virstride; -+ u32 y_virstride; - u32 yuv_virstride = 0; - u32 offset; - dma_addr_t dst_addr; -@@ -909,8 +910,8 @@ static void config_registers(struct rkvd - - f = &ctx->decoded_fmt; - dst_fmt = &f->fmt.pix_mp; -- hor_virstride = (sps->bit_depth_luma_minus8 + 8) * dst_fmt->width / 8; -- ver_virstride = round_up(dst_fmt->height, 16); -+ hor_virstride = dst_fmt->plane_fmt[0].bytesperline; -+ ver_virstride = dst_fmt->height; - y_virstride = hor_virstride * ver_virstride; - - if (sps->chroma_format_idc == 0) -@@ -1031,19 +1032,14 @@ static int rkvdec_h264_validate_sps(stru - { - unsigned int width, height; - -- /* -- * TODO: The hardware supports 10-bit and 4:2:2 profiles, -- * but it's currently broken in the driver. -- * Reject them for now, until it's fixed. -- */ -- if (sps->chroma_format_idc > 1) -- /* Only 4:0:0 and 4:2:0 are supported */ -+ if (sps->chroma_format_idc > 2) -+ /* Only 4:0:0, 4:2:0 and 4:2:2 are supported */ - return -EINVAL; - if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) - /* Luma and chroma bit depth mismatch */ - return -EINVAL; -- if (sps->bit_depth_luma_minus8 != 0) -- /* Only 8-bit is supported */ -+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) -+ /* Only 8-bit and 10-bit is supported */ - return -EINVAL; - - width = (sps->pic_width_in_mbs_minus1 + 1) * 16; -@@ -1064,6 +1060,25 @@ static int rkvdec_h264_validate_sps(stru - return 0; - } - -+static u32 rkvdec_h264_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) -+{ -+ const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps; -+ -+ if (sps->bit_depth_luma_minus8 == 0) { -+ if (sps->chroma_format_idc == 2) -+ return V4L2_PIX_FMT_NV16; -+ else -+ return V4L2_PIX_FMT_NV12; -+ } else if (sps->bit_depth_luma_minus8 == 2) { -+ if (sps->chroma_format_idc == 2) -+ return V4L2_PIX_FMT_NV20; -+ else -+ return V4L2_PIX_FMT_NV15; -+ } -+ -+ return 0; -+} -+ - static int rkvdec_h264_start(struct rkvdec_ctx *ctx) - { - struct rkvdec_dev *rkvdec = ctx->dev; -@@ -1185,6 +1200,7 @@ static int rkvdec_h264_try_ctrl(struct r - - const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops = { - .adjust_fmt = rkvdec_h264_adjust_fmt, -+ .valid_fmt = rkvdec_h264_valid_fmt, - .start = rkvdec_h264_start, - .stop = rkvdec_h264_stop, - .run = rkvdec_h264_run, -diff -rupN linux.orig/drivers/staging/media/rkvdec/rkvdec-hevc.c linux/drivers/staging/media/rkvdec/rkvdec-hevc.c ---- linux.orig/drivers/staging/media/rkvdec/rkvdec-hevc.c 1970-01-01 00:00:00.000000000 +0000 -+++ linux/drivers/staging/media/rkvdec/rkvdec-hevc.c 2024-01-03 21:27:48.651744306 +0000 -@@ -0,0 +1,2594 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Rockchip Video Decoder HEVC backend -+ * -+ * Copyright (C) 2019 Collabora, Ltd. -+ * Boris Brezillon -+ * -+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd. -+ * Jeffy Chen -+ */ -+ -+#include -+#include -+ -+#include "rkvdec.h" -+#include "rkvdec-regs.h" -+ -+/* Size in u8/u32 units. */ -+#define RKV_CABAC_TABLE_SIZE 27456 -+#define RKV_SCALING_LIST_SIZE 1360 -+#define RKV_PPS_SIZE (80 / 4) -+#define RKV_PPS_LEN 64 -+#define RKV_RPS_SIZE (32 / 4) -+#define RKV_RPS_LEN 600 -+ -+struct rkvdec_sps_pps_packet { -+ u32 info[RKV_PPS_SIZE]; -+}; -+ -+struct rkvdec_rps_packet { -+ u32 info[RKV_RPS_SIZE]; -+}; -+ -+struct rkvdec_ps_field { -+ u16 offset; -+ u8 len; -+}; -+ -+#define PS_FIELD(_offset, _len) \ -+ ((struct rkvdec_ps_field){ _offset, _len }) -+ -+/* SPS */ -+#define VIDEO_PARAMETER_SET_ID PS_FIELD(0, 4) -+#define SEQ_PARAMETER_SET_ID PS_FIELD(4, 4) -+#define CHROMA_FORMAT_IDC PS_FIELD(8, 2) -+#define PIC_WIDTH_IN_LUMA_SAMPLES PS_FIELD(10, 13) -+#define PIC_HEIGHT_IN_LUMA_SAMPLES PS_FIELD(23, 13) -+#define BIT_DEPTH_LUMA PS_FIELD(36, 4) -+#define BIT_DEPTH_CHROMA PS_FIELD(40, 4) -+#define LOG2_MAX_PIC_ORDER_CNT_LSB PS_FIELD(44, 5) -+#define LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(49, 2) -+#define LOG2_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(51, 3) -+#define LOG2_MIN_TRANSFORM_BLOCK_SIZE PS_FIELD(54, 3) -+#define LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE PS_FIELD(57, 2) -+#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTER PS_FIELD(59, 3) -+#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA PS_FIELD(62, 3) -+#define SCALING_LIST_ENABLED_FLAG PS_FIELD(65, 1) -+#define AMP_ENABLED_FLAG PS_FIELD(66, 1) -+#define SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG PS_FIELD(67, 1) -+#define PCM_ENABLED_FLAG PS_FIELD(68, 1) -+#define PCM_SAMPLE_BIT_DEPTH_LUMA PS_FIELD(69, 4) -+#define PCM_SAMPLE_BIT_DEPTH_CHROMA PS_FIELD(73, 4) -+#define PCM_LOOP_FILTER_DISABLED_FLAG PS_FIELD(77, 1) -+#define LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(78, 3) -+#define LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(81, 3) -+#define NUM_SHORT_TERM_REF_PIC_SETS PS_FIELD(84, 7) -+#define LONG_TERM_REF_PICS_PRESENT_FLAG PS_FIELD(91, 1) -+#define NUM_LONG_TERM_REF_PICS_SPS PS_FIELD(92, 6) -+#define SPS_TEMPORAL_MVP_ENABLED_FLAG PS_FIELD(98, 1) -+#define STRONG_INTRA_SMOOTHING_ENABLED_FLAG PS_FIELD(99, 1) -+/* PPS */ -+#define PIC_PARAMETER_SET_ID PS_FIELD(128, 6) -+#define PPS_SEQ_PARAMETER_SET_ID PS_FIELD(134, 4) -+#define DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG PS_FIELD(138, 1) -+#define OUTPUT_FLAG_PRESENT_FLAG PS_FIELD(139, 1) -+#define NUM_EXTRA_SLICE_HEADER_BITS PS_FIELD(140, 13) -+#define SIGN_DATA_HIDING_ENABLED_FLAG PS_FIELD(153, 1) -+#define CABAC_INIT_PRESENT_FLAG PS_FIELD(154, 1) -+#define NUM_REF_IDX_L0_DEFAULT_ACTIVE PS_FIELD(155, 4) -+#define NUM_REF_IDX_L1_DEFAULT_ACTIVE PS_FIELD(159, 4) -+#define INIT_QP_MINUS26 PS_FIELD(163, 7) -+#define CONSTRAINED_INTRA_PRED_FLAG PS_FIELD(170, 1) -+#define TRANSFORM_SKIP_ENABLED_FLAG PS_FIELD(171, 1) -+#define CU_QP_DELTA_ENABLED_FLAG PS_FIELD(172, 1) -+#define LOG2_MIN_CU_QP_DELTA_SIZE PS_FIELD(173, 3) -+#define PPS_CB_QP_OFFSET PS_FIELD(176, 5) -+#define PPS_CR_QP_OFFSET PS_FIELD(181, 5) -+#define PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG PS_FIELD(186, 1) -+#define WEIGHTED_PRED_FLAG PS_FIELD(187, 1) -+#define WEIGHTED_BIPRED_FLAG PS_FIELD(188, 1) -+#define TRANSQUANT_BYPASS_ENABLED_FLAG PS_FIELD(189, 1) -+#define TILES_ENABLED_FLAG PS_FIELD(190, 1) -+#define ENTROPY_CODING_SYNC_ENABLED_FLAG PS_FIELD(191, 1) -+#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG PS_FIELD(192, 1) -+#define LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG PS_FIELD(193, 1) -+#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG PS_FIELD(194, 1) -+#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG PS_FIELD(195, 1) -+#define PPS_BETA_OFFSET_DIV2 PS_FIELD(196, 4) -+#define PPS_TC_OFFSET_DIV2 PS_FIELD(200, 4) -+#define LISTS_MODIFICATION_PRESENT_FLAG PS_FIELD(204, 1) -+#define LOG2_PARALLEL_MERGE_LEVEL PS_FIELD(205, 3) -+#define SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG PS_FIELD(208, 1) -+#define NUM_TILE_COLUMNS PS_FIELD(212, 5) -+#define NUM_TILE_ROWS PS_FIELD(217, 5) -+#define COLUMN_WIDTH(i) PS_FIELD(256 + (i * 8), 8) -+#define ROW_HEIGHT(i) PS_FIELD(416 + (i * 8), 8) -+#define SCALING_LIST_ADDRESS PS_FIELD(592, 32) -+ -+/* Data structure describing auxiliary buffer format. */ -+struct rkvdec_hevc_priv_tbl { -+ u8 cabac_table[RKV_CABAC_TABLE_SIZE]; -+ u8 scaling_list[RKV_SCALING_LIST_SIZE]; -+ struct rkvdec_sps_pps_packet param_set[RKV_PPS_LEN]; -+ struct rkvdec_rps_packet rps[RKV_RPS_LEN]; -+}; -+ -+struct rkvdec_hevc_run { -+ struct rkvdec_run base; -+ const struct v4l2_ctrl_hevc_slice_params *slices_params; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params; -+ const struct v4l2_ctrl_hevc_sps *sps; -+ const struct v4l2_ctrl_hevc_pps *pps; -+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; -+ int num_slices; -+}; -+ -+struct rkvdec_hevc_ctx { -+ struct rkvdec_aux_buf priv_tbl; -+ struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache; -+}; -+ -+// TODO: refactor scaling list code, was copied 1:1 from mpp -+ -+typedef struct ScalingList { -+ /* This is a little wasteful, since sizeID 0 only needs 8 coeffs, -+ * and size ID 3 only has 2 arrays, not 6. */ -+ u8 sl[4][6][64]; -+ u8 sl_dc[2][6]; -+} scalingList_t; -+ -+typedef struct ScalingFactor_Model { -+ u8 scalingfactor0[1248]; -+ u8 scalingfactor1[96]; /*4X4 TU Rotate, total 16X4*/ -+ u8 scalingdc[12]; /*N1005 Vienna Meeting*/ -+ u8 reserverd[4]; /*16Bytes align*/ -+} scalingFactor_t; -+ -+#define SCALING_LIST_SIZE_NUM 4 -+ -+static void -+hal_record_scaling_list(scalingFactor_t *pScalingFactor_out, -+ scalingList_t *pScalingList) -+{ -+ int i; -+ u32 g_scalingListNum_model[SCALING_LIST_SIZE_NUM] = {6, 6, 6, 2}; // from C Model -+ u32 nIndex = 0; -+ u32 sizeId, matrixId, listId; -+ u8 *p = pScalingFactor_out->scalingfactor0; -+ u8 tmpBuf[8 * 8]; -+ -+ //output non-default scalingFactor Table (1248 BYTES) -+ for (sizeId = 0; sizeId < SCALING_LIST_SIZE_NUM; sizeId++) { -+ for (listId = 0; listId < g_scalingListNum_model[sizeId]; listId++) { -+ if (sizeId < 3) { -+ for (i = 0; i < (sizeId == 0 ? 16 : 64); i++) { -+ pScalingFactor_out->scalingfactor0[nIndex++] = (u8)pScalingList->sl[sizeId][listId][i]; -+ } -+ } else { -+ for (i = 0; i < 64; i ++) { -+ pScalingFactor_out->scalingfactor0[nIndex++] = (u8)pScalingList->sl[sizeId][listId][i]; -+ } -+ for (i = 0; i < 128; i ++) { -+ pScalingFactor_out->scalingfactor0[nIndex++] = 0; -+ } -+ } -+ } -+ } -+ //output non-default scalingFactor Table Rotation(96 Bytes) -+ nIndex = 0; -+ for (listId = 0; listId < g_scalingListNum_model[0]; listId++) { -+ u8 temp16[16] = {0}; -+ for (i = 0; i < 16; i ++) { -+ temp16[i] = (u8)pScalingList->sl[0][listId][i]; -+ } -+ for (i = 0; i < 4; i ++) { -+ pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i]; -+ pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 4]; -+ pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 8]; -+ pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 12]; -+ } -+ } -+ //output non-default ScalingList_DC_Coeff (12 BYTES) -+ nIndex = 0; -+ for (listId = 0; listId < g_scalingListNum_model[2]; listId++) { //sizeId = 2 -+ pScalingFactor_out->scalingdc[nIndex++] = (u8)pScalingList->sl_dc[0][listId];// zrh warning: sl_dc differed from scalingList->getScalingListDC -+ } -+ for (listId = 0; listId < g_scalingListNum_model[3]; listId++) { //sizeId = 3 -+ pScalingFactor_out->scalingdc[nIndex++] = (u8)pScalingList->sl_dc[1][listId];// zrh warning: sl_dc differed from scalingList->getScalingListDC -+ pScalingFactor_out->scalingdc[nIndex++] = 0; -+ pScalingFactor_out->scalingdc[nIndex++] = 0; -+ } -+ -+ //align 16X address -+ nIndex = 0; -+ for (i = 0; i < 4; i ++) { -+ pScalingFactor_out->reserverd[nIndex++] = 0; -+ } -+ -+ //----------------------All above code show the normal store way in HM-------------------------- -+ //--------from now on, the scalingfactor0 is rotated 90', the scalingfactor1 is also rotated 90' -+ -+ //sizeId == 0 -+ for (matrixId = 0; matrixId < 6; matrixId++) { -+ p = pScalingFactor_out->scalingfactor0 + matrixId * 16; -+ -+ for (i = 0; i < 4; i++) { -+ tmpBuf[4 * 0 + i] = p[i * 4 + 0]; -+ tmpBuf[4 * 1 + i] = p[i * 4 + 1]; -+ tmpBuf[4 * 2 + i] = p[i * 4 + 2]; -+ tmpBuf[4 * 3 + i] = p[i * 4 + 3]; -+ } -+ memcpy(p, tmpBuf, 4 * 4 * sizeof(u8)); -+ } -+ //sizeId == 1 -+ for (matrixId = 0; matrixId < 6; matrixId++) { -+ p = pScalingFactor_out->scalingfactor0 + 6 * 16 + matrixId * 64; -+ -+ for (i = 0; i < 8; i++) { -+ tmpBuf[8 * 0 + i] = p[i * 8 + 0]; -+ tmpBuf[8 * 1 + i] = p[i * 8 + 1]; -+ tmpBuf[8 * 2 + i] = p[i * 8 + 2]; -+ tmpBuf[8 * 3 + i] = p[i * 8 + 3]; -+ tmpBuf[8 * 4 + i] = p[i * 8 + 4]; -+ tmpBuf[8 * 5 + i] = p[i * 8 + 5]; -+ tmpBuf[8 * 6 + i] = p[i * 8 + 6]; -+ tmpBuf[8 * 7 + i] = p[i * 8 + 7]; -+ } -+ memcpy(p, tmpBuf, 8 * 8 * sizeof(u8)); -+ } -+ //sizeId == 2 -+ for (matrixId = 0; matrixId < 6; matrixId++) { -+ p = pScalingFactor_out->scalingfactor0 + 6 * 16 + 6 * 64 + matrixId * 64; -+ -+ for (i = 0; i < 8; i++) { -+ tmpBuf[8 * 0 + i] = p[i * 8 + 0]; -+ tmpBuf[8 * 1 + i] = p[i * 8 + 1]; -+ tmpBuf[8 * 2 + i] = p[i * 8 + 2]; -+ tmpBuf[8 * 3 + i] = p[i * 8 + 3]; -+ tmpBuf[8 * 4 + i] = p[i * 8 + 4]; -+ tmpBuf[8 * 5 + i] = p[i * 8 + 5]; -+ tmpBuf[8 * 6 + i] = p[i * 8 + 6]; -+ tmpBuf[8 * 7 + i] = p[i * 8 + 7]; -+ } -+ memcpy(p, tmpBuf, 8 * 8 * sizeof(u8)); -+ } -+ //sizeId == 3 -+ for (matrixId = 0; matrixId < 6; matrixId++) { -+ p = pScalingFactor_out->scalingfactor0 + 6 * 16 + 6 * 64 + 6 * 64 + matrixId * 64; -+ -+ for (i = 0; i < 8; i++) { -+ tmpBuf[8 * 0 + i] = p[i * 8 + 0]; -+ tmpBuf[8 * 1 + i] = p[i * 8 + 1]; -+ tmpBuf[8 * 2 + i] = p[i * 8 + 2]; -+ tmpBuf[8 * 3 + i] = p[i * 8 + 3]; -+ tmpBuf[8 * 4 + i] = p[i * 8 + 4]; -+ tmpBuf[8 * 5 + i] = p[i * 8 + 5]; -+ tmpBuf[8 * 6 + i] = p[i * 8 + 6]; -+ tmpBuf[8 * 7 + i] = p[i * 8 + 7]; -+ } -+ memcpy(p, tmpBuf, 8 * 8 * sizeof(u8)); -+ } -+ -+ //sizeId == 0 -+ for (matrixId = 0; matrixId < 6; matrixId++) { -+ p = pScalingFactor_out->scalingfactor1 + matrixId * 16; -+ -+ for (i = 0; i < 4; i++) { -+ tmpBuf[4 * 0 + i] = p[i * 4 + 0]; -+ tmpBuf[4 * 1 + i] = p[i * 4 + 1]; -+ tmpBuf[4 * 2 + i] = p[i * 4 + 2]; -+ tmpBuf[4 * 3 + i] = p[i * 4 + 3]; -+ } -+ memcpy(p, tmpBuf, 4 * 4 * sizeof(u8)); -+ } -+} -+ -+static const u8 rkvdec_hevc_cabac_table[RKV_CABAC_TABLE_SIZE] = { -+ 0x07, 0x0f, 0x48, 0x58, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, 0x68, -+ 0x48, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40, 0x40, 0x68, -+ 0x58, 0x60, 0x40, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x60, 0x60, 0x50, 0x58, -+ 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50, 0x48, 0x68, 0x60, 0x60, -+ 0x50, 0x58, 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50, 0x48, 0x68, -+ 0x48, 0x48, 0x1f, 0x58, 0x68, 0x68, 0x58, 0x60, 0x60, 0x60, 0x50, 0x50, 0x50, 0x48, 0x58, 0x58, -+ 0x37, 0x07, 0x58, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x50, -+ 0x48, 0x1f, 0x1f, 0x0f, 0x0f, 0x0f, 0x0f, 0x07, 0x0f, 0x48, 0x68, 0x0f, 0x48, 0x68, 0x40, 0x40, -+ 0x50, 0x50, 0x07, 0x40, 0x50, 0x0f, 0x40, 0x48, 0x07, 0x40, 0x27, 0x50, 0x48, 0x48, 0x40, 0x0f, -+ 0x50, 0x37, 0x1f, 0x1f, 0x50, 0x37, 0x40, 0x27, 0x40, 0x07, 0x0f, 0x17, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x0f, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, 0x66, -+ 0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x67, -+ 0x57, 0x5e, 0x00, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5f, 0x5f, 0x4f, 0x57, -+ 0x4f, 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x66, 0x5f, 0x5f, -+ 0x4f, 0x57, 0x4f, 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, 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rkvdec_ps_field field, u32 value) -+{ -+ u8 bit = field.offset % 32, word = field.offset / 32; -+ u64 mask = GENMASK_ULL(bit + field.len - 1, bit); -+ u64 val = ((u64)value << bit) & mask; -+ -+ buf[word] &= ~mask; -+ buf[word] |= val; -+ if (bit + field.len > 32) { -+ buf[word + 1] &= ~(mask >> 32); -+ buf[word + 1] |= val >> 32; -+ } -+} -+ -+static void assemble_hw_pps(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ const struct v4l2_ctrl_hevc_sps *sps = run->sps; -+ const struct v4l2_ctrl_hevc_pps *pps = run->pps; -+ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; -+ struct rkvdec_sps_pps_packet *hw_ps; -+ u32 min_cb_log2_size_y, ctb_log2_size_y, ctb_size_y; -+ u32 log2_min_cu_qp_delta_size; -+ dma_addr_t scaling_list_address; -+ u32 scaling_distance; -+ int i; -+ -+ /* -+ * HW read the SPS/PPS information from PPS packet index by PPS id. -+ * offset from the base can be calculated by PPS_id * 80 (size per PPS -+ * packet unit). so the driver copy SPS/PPS information to the exact PPS -+ * packet unit for HW accessing. -+ */ -+ hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id]; -+ memset(hw_ps, 0, sizeof(*hw_ps)); -+ -+ min_cb_log2_size_y = sps->log2_min_luma_coding_block_size_minus3 + 3; -+ ctb_log2_size_y = min_cb_log2_size_y + -+ sps->log2_diff_max_min_luma_coding_block_size; -+ ctb_size_y = 1 << ctb_log2_size_y; -+ -+#define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value) -+ /* write sps */ -+ WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID); -+ WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID); -+ WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC); -+ WRITE_PPS(sps->pic_width_in_luma_samples, PIC_WIDTH_IN_LUMA_SAMPLES); -+ WRITE_PPS(sps->pic_height_in_luma_samples, PIC_HEIGHT_IN_LUMA_SAMPLES); -+ WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA); -+ WRITE_PPS(sps->bit_depth_chroma_minus8 + 8, BIT_DEPTH_CHROMA); -+ WRITE_PPS(sps->log2_max_pic_order_cnt_lsb_minus4 + 4, -+ LOG2_MAX_PIC_ORDER_CNT_LSB); -+ WRITE_PPS(sps->log2_diff_max_min_luma_coding_block_size, -+ LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE); -+ WRITE_PPS(sps->log2_min_luma_coding_block_size_minus3 + 3, -+ LOG2_MIN_LUMA_CODING_BLOCK_SIZE); -+ WRITE_PPS(sps->log2_min_luma_transform_block_size_minus2 + 2, -+ LOG2_MIN_TRANSFORM_BLOCK_SIZE); -+ WRITE_PPS(sps->log2_diff_max_min_luma_transform_block_size, -+ LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE); -+ WRITE_PPS(sps->max_transform_hierarchy_depth_inter, -+ MAX_TRANSFORM_HIERARCHY_DEPTH_INTER); -+ WRITE_PPS(sps->max_transform_hierarchy_depth_intra, -+ MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED), -+ SCALING_LIST_ENABLED_FLAG); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED), -+ AMP_ENABLED_FLAG); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET), -+ SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG); -+ if (sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED) { -+ WRITE_PPS(1, PCM_ENABLED_FLAG); -+ WRITE_PPS(sps->pcm_sample_bit_depth_luma_minus1 + 1, -+ PCM_SAMPLE_BIT_DEPTH_LUMA); -+ WRITE_PPS(sps->pcm_sample_bit_depth_chroma_minus1 + 1, -+ PCM_SAMPLE_BIT_DEPTH_CHROMA); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED), -+ PCM_LOOP_FILTER_DISABLED_FLAG); -+ WRITE_PPS(sps->log2_diff_max_min_pcm_luma_coding_block_size, -+ LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE); -+ WRITE_PPS(sps->log2_min_pcm_luma_coding_block_size_minus3 + 3, -+ LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE); -+ } -+ WRITE_PPS(sps->num_short_term_ref_pic_sets, NUM_SHORT_TERM_REF_PIC_SETS); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT), -+ LONG_TERM_REF_PICS_PRESENT_FLAG); -+ WRITE_PPS(sps->num_long_term_ref_pics_sps, NUM_LONG_TERM_REF_PICS_SPS); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED), -+ SPS_TEMPORAL_MVP_ENABLED_FLAG); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED), -+ STRONG_INTRA_SMOOTHING_ENABLED_FLAG); -+ -+ /* write pps */ -+ WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID); -+ WRITE_PPS(sps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED), -+ DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT), -+ OUTPUT_FLAG_PRESENT_FLAG); -+ WRITE_PPS(pps->num_extra_slice_header_bits, NUM_EXTRA_SLICE_HEADER_BITS); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED), -+ SIGN_DATA_HIDING_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT), -+ CABAC_INIT_PRESENT_FLAG); -+ WRITE_PPS(pps->num_ref_idx_l0_default_active_minus1 + 1, -+ NUM_REF_IDX_L0_DEFAULT_ACTIVE); -+ WRITE_PPS(pps->num_ref_idx_l1_default_active_minus1 + 1, -+ NUM_REF_IDX_L1_DEFAULT_ACTIVE); -+ WRITE_PPS(pps->init_qp_minus26, INIT_QP_MINUS26); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED), -+ CONSTRAINED_INTRA_PRED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED), -+ TRANSFORM_SKIP_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED), -+ CU_QP_DELTA_ENABLED_FLAG); -+ -+ log2_min_cu_qp_delta_size = ctb_log2_size_y - pps->diff_cu_qp_delta_depth; -+ WRITE_PPS(log2_min_cu_qp_delta_size, LOG2_MIN_CU_QP_DELTA_SIZE); -+ -+ WRITE_PPS(pps->pps_cb_qp_offset, PPS_CB_QP_OFFSET); -+ WRITE_PPS(pps->pps_cr_qp_offset, PPS_CR_QP_OFFSET); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT), -+ PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED), -+ WEIGHTED_PRED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED), -+ WEIGHTED_BIPRED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED), -+ TRANSQUANT_BYPASS_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED), -+ TILES_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED), -+ ENTROPY_CODING_SYNC_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED), -+ PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED), -+ LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED), -+ DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER), -+ PPS_DEBLOCKING_FILTER_DISABLED_FLAG); -+ WRITE_PPS(pps->pps_beta_offset_div2, PPS_BETA_OFFSET_DIV2); -+ WRITE_PPS(pps->pps_tc_offset_div2, PPS_TC_OFFSET_DIV2); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT), -+ LISTS_MODIFICATION_PRESENT_FLAG); -+ WRITE_PPS(pps->log2_parallel_merge_level_minus2 + 2, LOG2_PARALLEL_MERGE_LEVEL); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT), -+ SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG); -+ WRITE_PPS(pps->num_tile_columns_minus1 + 1, NUM_TILE_COLUMNS); -+ WRITE_PPS(pps->num_tile_rows_minus1 + 1, NUM_TILE_ROWS); -+ -+ if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) { -+ for (i = 0; i <= pps->num_tile_columns_minus1; i++) -+ WRITE_PPS(pps->column_width_minus1[i], COLUMN_WIDTH(i)); -+ for (i = 0; i <= pps->num_tile_rows_minus1; i++) -+ WRITE_PPS(pps->row_height_minus1[i], ROW_HEIGHT(i)); -+ } else { -+ WRITE_PPS(((sps->pic_width_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1, -+ COLUMN_WIDTH(0)); -+ WRITE_PPS(((sps->pic_height_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1, -+ ROW_HEIGHT(0)); -+ } -+ -+ scaling_distance = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list); -+ scaling_list_address = hevc_ctx->priv_tbl.dma + scaling_distance; -+ WRITE_PPS(scaling_list_address, SCALING_LIST_ADDRESS); -+} -+ -+static void assemble_hw_rps(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -+ const struct v4l2_ctrl_hevc_sps *sps = run->sps; -+ const struct v4l2_ctrl_hevc_slice_params *sl_params; -+ const struct v4l2_hevc_dpb_entry *dpb; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; -+ struct rkvdec_rps_packet *hw_ps; -+ int i, j; -+ unsigned int lowdelay; -+ -+#define WRITE_RPS(value, field) set_ps_field(hw_ps->info, field, value) -+ -+#define REF_PIC_LONG_TERM_L0(i) PS_FIELD(i * 5, 1) -+#define REF_PIC_IDX_L0(i) PS_FIELD(1 + (i * 5), 4) -+#define REF_PIC_LONG_TERM_L1(i) PS_FIELD((i < 5 ? 75 : 132) + (i * 5), 1) -+#define REF_PIC_IDX_L1(i) PS_FIELD((i < 4 ? 76 : 128) + (i * 5), 4) -+ -+#define LOWDELAY PS_FIELD(182, 1) -+#define LONG_TERM_RPS_BIT_OFFSET PS_FIELD(183, 10) -+#define SHORT_TERM_RPS_BIT_OFFSET PS_FIELD(193, 9) -+#define NUM_RPS_POC PS_FIELD(202, 4) -+ -+ for (j = 0; j < run->num_slices; j++) { -+ uint st_bit_offset = 0; -+ uint num_l0_refs = 0; -+ uint num_l1_refs = 0; -+ -+ sl_params = &run->slices_params[j]; -+ dpb = decode_params->dpb; -+ -+ if (sl_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) { -+ num_l0_refs = sl_params->num_ref_idx_l0_active_minus1 + 1; -+ -+ if (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_B) -+ num_l1_refs = sl_params->num_ref_idx_l1_active_minus1 + 1; -+ -+ lowdelay = 1; -+ } else { -+ lowdelay = 0; -+ } -+ -+ hw_ps = &priv_tbl->rps[j]; -+ memset(hw_ps, 0, sizeof(*hw_ps)); -+ -+ for (i = 0; i < num_l0_refs; i++) { -+ WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), -+ REF_PIC_LONG_TERM_L0(i)); -+ WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i)); -+ -+ if (dpb[sl_params->ref_idx_l0[i]].pic_order_cnt_val > sl_params->slice_pic_order_cnt) -+ lowdelay = 0; -+ -+ } -+ -+ for (i = 0; i < num_l1_refs; i++) { -+ WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), -+ REF_PIC_LONG_TERM_L1(i)); -+ WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i)); -+ -+ if (dpb[sl_params->ref_idx_l1[i]].pic_order_cnt_val > sl_params->slice_pic_order_cnt) -+ lowdelay = 0; -+ } -+ -+ WRITE_RPS(lowdelay, LOWDELAY); -+ -+ if (!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC)) { -+ if (sl_params->short_term_ref_pic_set_size) -+ st_bit_offset = sl_params->short_term_ref_pic_set_size; -+ else if (sps->num_short_term_ref_pic_sets > 1) -+ st_bit_offset = fls(sps->num_short_term_ref_pic_sets - 1); -+ } -+ -+ WRITE_RPS(st_bit_offset + sl_params->long_term_ref_pic_set_size, -+ LONG_TERM_RPS_BIT_OFFSET); -+ WRITE_RPS(sl_params->short_term_ref_pic_set_size, -+ SHORT_TERM_RPS_BIT_OFFSET); -+ -+ WRITE_RPS(decode_params->num_poc_st_curr_before + -+ decode_params->num_poc_st_curr_after + -+ decode_params->num_poc_lt_curr, -+ NUM_RPS_POC); -+ } -+} -+ -+static void assemble_hw_scaling_list(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling = run->scaling_matrix; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu; -+ u8 *dst; -+ scalingList_t sl; -+ int i, j; -+ -+ if (!memcmp((void*)&hevc_ctx->scaling_matrix_cache, scaling, -+ sizeof(struct v4l2_ctrl_hevc_scaling_matrix))) -+ return; -+ -+ memset(&sl, 0, sizeof(scalingList_t)); -+ -+ for (i = 0; i < 6; i++) { -+ for (j = 0; j < 16; j++) -+ sl.sl[0][i][j] = scaling->scaling_list_4x4[i][j]; -+ for (j = 0; j < 64; j++) { -+ sl.sl[1][i][j] = scaling->scaling_list_8x8[i][j]; -+ sl.sl[2][i][j] = scaling->scaling_list_16x16[i][j]; -+ if (i < 2) -+ sl.sl[3][i][j] = scaling->scaling_list_32x32[i][j]; -+ } -+ sl.sl_dc[0][i] = scaling->scaling_list_dc_coef_16x16[i]; -+ if (i < 2) -+ sl.sl_dc[1][i] = scaling->scaling_list_dc_coef_32x32[i]; -+ } -+ -+ dst = tbl->scaling_list; -+ hal_record_scaling_list((scalingFactor_t *)dst, &sl); -+ -+ memcpy((void*)&hevc_ctx->scaling_matrix_cache, scaling, -+ sizeof(struct v4l2_ctrl_hevc_scaling_matrix)); -+} -+ -+static struct vb2_buffer * -+get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run, -+ unsigned int dpb_idx) -+{ -+ struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; -+ struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; -+ struct vb2_buffer *vb2_buf = NULL; -+ -+ if (dpb_idx < decode_params->num_active_dpb_entries) -+ vb2_buf = vb2_find_buffer(cap_q, dpb[dpb_idx].timestamp); -+ -+ /* -+ * If a DPB entry is unused or invalid, address of current destination -+ * buffer is returned. -+ */ -+ if (!vb2_buf) -+ return &run->base.bufs.dst->vb2_buf; -+ -+ return vb2_buf; -+} -+ -+static void config_registers(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -+ const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0]; -+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma; -+ const struct v4l2_pix_format_mplane *dst_fmt; -+ struct vb2_v4l2_buffer *src_buf = run->base.bufs.src; -+ struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst; -+ const struct v4l2_format *f; -+ dma_addr_t rlc_addr; -+ dma_addr_t refer_addr; -+ u32 rlc_len; -+ u32 hor_virstride; -+ u32 ver_virstride; -+ u32 y_virstride; -+ u32 uv_virstride; -+ u32 yuv_virstride; -+ u32 offset; -+ dma_addr_t dst_addr; -+ u32 reg, i; -+ -+ reg = RKVDEC_MODE(RKVDEC_MODE_HEVC); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_SYSCTRL); -+ -+ f = &ctx->decoded_fmt; -+ dst_fmt = &f->fmt.pix_mp; -+ hor_virstride = dst_fmt->plane_fmt[0].bytesperline; -+ ver_virstride = dst_fmt->height; -+ y_virstride = hor_virstride * ver_virstride; -+ uv_virstride = y_virstride / 2; -+ yuv_virstride = y_virstride + uv_virstride; -+ -+ reg = RKVDEC_Y_HOR_VIRSTRIDE(hor_virstride / 16) | -+ RKVDEC_UV_HOR_VIRSTRIDE(hor_virstride / 16) | -+ RKVDEC_SLICE_NUM_LOWBITS(run->num_slices); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_PICPAR); -+ -+ /* config rlc base address */ -+ rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); -+ writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE); -+ -+ rlc_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0); -+ reg = RKVDEC_STRM_LEN(round_up(rlc_len, 16) + 64); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_STRM_LEN); -+ -+ /* config cabac table */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table); -+ writel_relaxed(priv_start_addr + offset, -+ rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE); -+ -+ /* config output base address */ -+ dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); -+ writel_relaxed(dst_addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE); -+ -+ reg = RKVDEC_Y_VIRSTRIDE(y_virstride / 16); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE); -+ -+ reg = RKVDEC_YUV_VIRSTRIDE(yuv_virstride / 16); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE); -+ -+ /* config ref pic address */ -+ for (i = 0; i < 15; i++) { -+ struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i); -+ -+ if (i < 4 && decode_params->num_active_dpb_entries) { -+ reg = GENMASK(decode_params->num_active_dpb_entries - 1, 0); -+ reg = (reg >> (i * 4)) & 0xf; -+ } else -+ reg = 0; -+ -+ refer_addr = vb2_dma_contig_plane_dma_addr(vb_buf, 0); -+ writel_relaxed(refer_addr | reg, -+ rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i)); -+ -+ reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ? dpb[i].pic_order_cnt_val : 0); -+ writel_relaxed(reg, -+ rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i)); -+ } -+ -+ reg = RKVDEC_CUR_POC(sl_params->slice_pic_order_cnt); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0); -+ -+ /* config hw pps address */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set); -+ writel_relaxed(priv_start_addr + offset, -+ rkvdec->regs + RKVDEC_REG_PPS_BASE); -+ -+ /* config hw rps address */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, rps); -+ writel_relaxed(priv_start_addr + offset, -+ rkvdec->regs + RKVDEC_REG_RPS_BASE); -+ -+ reg = RKVDEC_AXI_DDR_RDATA(0); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_RDATA); -+ -+ reg = RKVDEC_AXI_DDR_WDATA(0); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_WDATA); -+} -+ -+#define RKVDEC_HEVC_MAX_DEPTH_IN_BYTES 2 -+ -+static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, -+ struct v4l2_format *f) -+{ -+ struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp; -+ -+ fmt->num_planes = 1; -+ if (!fmt->plane_fmt[0].sizeimage) -+ fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height * -+ RKVDEC_HEVC_MAX_DEPTH_IN_BYTES; -+ return 0; -+} -+ -+static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, -+ const struct v4l2_ctrl_hevc_sps *sps) -+{ -+ if (sps->chroma_format_idc > 1) -+ /* Only 4:0:0 and 4:2:0 are supported */ -+ return -EINVAL; -+ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) -+ /* Luma and chroma bit depth mismatch */ -+ return -EINVAL; -+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) -+ /* Only 8-bit and 10-bit is supported */ -+ return -EINVAL; -+ -+ if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width || -+ sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static u32 rkvdec_hevc_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) -+{ -+ const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; -+ -+ if (sps->bit_depth_luma_minus8 == 2) -+ return V4L2_PIX_FMT_NV15; -+ else -+ return V4L2_PIX_FMT_NV12; -+} -+ -+static int rkvdec_hevc_start(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_hevc_priv_tbl *priv_tbl; -+ struct rkvdec_hevc_ctx *hevc_ctx; -+ struct v4l2_ctrl *ctrl; -+ int ret; -+ -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SPS); -+ if (!ctrl) -+ return -EINVAL; -+ -+ ret = rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); -+ if (ret) -+ return ret; -+ -+ hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL); -+ if (!hevc_ctx) -+ return -ENOMEM; -+ -+ -+ priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl), -+ &hevc_ctx->priv_tbl.dma, GFP_KERNEL); -+ if (!priv_tbl) { -+ ret = -ENOMEM; -+ goto err_free_ctx; -+ } -+ -+ hevc_ctx->priv_tbl.size = sizeof(*priv_tbl); -+ hevc_ctx->priv_tbl.cpu = priv_tbl; -+ memset(priv_tbl, 0, sizeof(*priv_tbl)); -+ memcpy(priv_tbl->cabac_table, rkvdec_hevc_cabac_table, -+ sizeof(rkvdec_hevc_cabac_table)); -+ -+ ctx->priv = hevc_ctx; -+ return 0; -+ -+err_free_ctx: -+ kfree(hevc_ctx); -+ return ret; -+} -+ -+static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ -+ dma_free_coherent(rkvdec->dev, hevc_ctx->priv_tbl.size, -+ hevc_ctx->priv_tbl.cpu, hevc_ctx->priv_tbl.dma); -+ kfree(hevc_ctx); -+} -+ -+static void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ struct v4l2_ctrl *ctrl; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_DECODE_PARAMS); -+ run->decode_params = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SLICE_PARAMS); -+ run->slices_params = ctrl ? ctrl->p_cur.p : NULL; -+ run->num_slices = ctrl->new_elems; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SPS); -+ run->sps = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_PPS); -+ run->pps = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SCALING_MATRIX); -+ run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL; -+ -+ rkvdec_run_preamble(ctx, &run->base); -+} -+ -+static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_hevc_run run; -+ -+ rkvdec_hevc_run_preamble(ctx, &run); -+ -+ assemble_hw_scaling_list(ctx, &run); -+ assemble_hw_pps(ctx, &run); -+ assemble_hw_rps(ctx, &run); -+ config_registers(ctx, &run); -+ -+ rkvdec_run_postamble(ctx, &run.base); -+ -+ // sw_cabac_error_e - cabac error enable -+ writel_relaxed(0xfdfffffd, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN); -+ // slice end error enable = BIT(28) -+ // frame end error enable = BIT(29) -+ writel_relaxed(0x30000000, rkvdec->regs + RKVDEC_REG_H264_ERR_E); -+ -+ schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000)); -+ -+ writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND); -+ writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); -+ -+ /* Start decoding! */ -+ writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E | -+ RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E, -+ rkvdec->regs + RKVDEC_REG_INTERRUPT); -+ -+ return 0; -+} -+ -+static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) -+{ -+ if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS) -+ return rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); -+ -+ return 0; -+} -+ -+const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = { -+ .adjust_fmt = rkvdec_hevc_adjust_fmt, -+ .start = rkvdec_hevc_start, -+ .stop = rkvdec_hevc_stop, -+ .run = rkvdec_hevc_run, -+ .try_ctrl = rkvdec_hevc_try_ctrl, -+ .valid_fmt = rkvdec_hevc_valid_fmt, -+}; -diff -rupN linux.orig/drivers/staging/media/rkvdec/rkvdec-regs.h linux/drivers/staging/media/rkvdec/rkvdec-regs.h ---- linux.orig/drivers/staging/media/rkvdec/rkvdec-regs.h 2024-01-03 20:53:31.439335419 +0000 -+++ linux/drivers/staging/media/rkvdec/rkvdec-regs.h 2024-01-03 21:27:48.651744306 +0000 -@@ -28,6 +28,11 @@ - #define RKVDEC_SOFTRST_EN_P BIT(20) - #define RKVDEC_FORCE_SOFTRESET_VALID BIT(21) - #define RKVDEC_SOFTRESET_RDY BIT(22) -+#define RKVDEC_ERR_MASK (RKVDEC_BUS_STA \ -+ | RKVDEC_ERR_STA \ -+ | RKVDEC_TIMEOUT_STA \ -+ | RKVDEC_BUF_EMPTY_STA \ -+ | RKVDEC_COLMV_REF_ERR_STA ) - - #define RKVDEC_REG_SYSCTRL 0x008 - #define RKVDEC_IN_ENDIAN BIT(0) -@@ -43,6 +48,7 @@ - #define RKVDEC_RLC_MODE BIT(11) - #define RKVDEC_STRM_START_BIT(x) (((x) & 0x7f) << 12) - #define RKVDEC_MODE(x) (((x) & 0x03) << 20) -+#define RKVDEC_MODE_HEVC 0 - #define RKVDEC_MODE_H264 1 - #define RKVDEC_MODE_VP9 2 - #define RKVDEC_RPS_MODE BIT(24) -@@ -217,6 +223,8 @@ - #define RKVDEC_REG_H264_ERR_E 0x134 - #define RKVDEC_H264_ERR_EN_HIGHBITS(x) ((x) & 0x3fffffff) - -+#define RKVDEC_QOS_CTRL 0x18C -+ - #define RKVDEC_REG_PREF_LUMA_CACHE_COMMAND 0x410 - #define RKVDEC_REG_PREF_CHR_CACHE_COMMAND 0x450 - -diff -rupN linux.orig/drivers/staging/media/rkvdec/rkvdec-vp9.c linux/drivers/staging/media/rkvdec/rkvdec-vp9.c ---- linux.orig/drivers/staging/media/rkvdec/rkvdec-vp9.c 2024-01-03 20:53:31.439335419 +0000 -+++ linux/drivers/staging/media/rkvdec/rkvdec-vp9.c 2024-01-03 21:26:02.711011382 +0000 -@@ -804,6 +804,7 @@ static int rkvdec_vp9_run(struct rkvdec_ - struct rkvdec_dev *rkvdec = ctx->dev; - struct rkvdec_vp9_run run = { }; - int ret; -+ u32 reg; - - ret = rkvdec_vp9_run_preamble(ctx, &run); - if (ret) { -@@ -825,6 +826,13 @@ static int rkvdec_vp9_run(struct rkvdec_ - writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); - - writel(0xe, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN); -+ -+ /* disable QOS for RK3328 - no effect on other SoCs */ -+ reg = readl(rkvdec->regs + RKVDEC_QOS_CTRL); -+ reg |= 0xFFFF; -+ reg &= (~BIT(12)); -+ writel(reg, rkvdec->regs + RKVDEC_QOS_CTRL); -+ - /* Start decoding! */ - writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E | - RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E, -diff -rupN linux.orig/drivers/staging/media/rkvdec/rkvdec.c linux/drivers/staging/media/rkvdec/rkvdec.c ---- linux.orig/drivers/staging/media/rkvdec/rkvdec.c 2024-01-03 20:53:31.439335419 +0000 -+++ linux/drivers/staging/media/rkvdec/rkvdec.c 2024-01-03 21:31:44.568991334 +0000 -@@ -10,12 +10,16 @@ - */ - - #include -+#include - #include - #include - #include -+#include - #include - #include - #include -+#include -+#include - #include - #include - #include -@@ -27,19 +31,67 @@ - #include "rkvdec.h" - #include "rkvdec-regs.h" - -+static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, -+ struct v4l2_pix_format_mplane *pix_mp) -+{ -+ v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, -+ ALIGN(pix_mp->width, 64), pix_mp->height); -+ pix_mp->plane_fmt[0].sizeimage += 128 * -+ DIV_ROUND_UP(pix_mp->width, 16) * -+ DIV_ROUND_UP(pix_mp->height, 16); -+ pix_mp->field = V4L2_FIELD_NONE; -+} -+ -+static u32 rkvdec_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) -+{ -+ const struct rkvdec_coded_fmt_desc *coded_desc = ctx->coded_fmt_desc; -+ -+ if (coded_desc->ops->valid_fmt) -+ return coded_desc->ops->valid_fmt(ctx, ctrl); -+ -+ return ctx->valid_fmt; -+} -+ - static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) - { - struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); - const struct rkvdec_coded_fmt_desc *desc = ctx->coded_fmt_desc; - -- if (desc->ops->try_ctrl) -- return desc->ops->try_ctrl(ctx, ctrl); -+ if (desc->ops->try_ctrl) { -+ int ret; -+ ret = desc->ops->try_ctrl(ctx, ctrl); -+ if (ret) -+ return ret; -+ } -+ -+ if (ctx->valid_fmt && ctx->valid_fmt != rkvdec_valid_fmt(ctx, ctrl)) -+ /* Only current valid format */ -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl) -+{ -+ struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); -+ -+ if (!ctx->valid_fmt) { -+ ctx->valid_fmt = rkvdec_valid_fmt(ctx, ctrl); -+ if (ctx->valid_fmt) { -+ struct v4l2_pix_format_mplane *pix_mp; -+ -+ pix_mp = &ctx->decoded_fmt.fmt.pix_mp; -+ pix_mp->pixelformat = ctx->valid_fmt; -+ rkvdec_fill_decoded_pixfmt(ctx, pix_mp); -+ } -+ } - - return 0; - } - - static const struct v4l2_ctrl_ops rkvdec_ctrl_ops = { - .try_ctrl = rkvdec_try_ctrl, -+ .s_ctrl = rkvdec_s_ctrl, - }; - - static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { -@@ -83,13 +135,72 @@ static const struct rkvdec_ctrl_desc rkv - }, - }; - -+static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_SLICE_PARAMS, -+ .cfg.flags = V4L2_CTRL_FLAG_DYNAMIC_ARRAY, -+ .cfg.type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS, -+ .cfg.dims = { 600 }, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_SPS, -+ .cfg.ops = &rkvdec_ctrl_ops, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_PPS, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE, -+ .cfg.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, -+ .cfg.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, -+ .cfg.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_START_CODE, -+ .cfg.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, -+ .cfg.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, -+ .cfg.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, -+ }, -+ { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, -+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, -+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, -+ .cfg.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, -+ }, -+ { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, -+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1, -+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, -+ }, -+}; -+ -+static const struct rkvdec_ctrls rkvdec_hevc_ctrls = { -+ .ctrls = rkvdec_hevc_ctrl_descs, -+ .num_ctrls = ARRAY_SIZE(rkvdec_hevc_ctrl_descs), -+}; -+ -+static const u32 rkvdec_hevc_decoded_fmts[] = { -+ V4L2_PIX_FMT_NV12, -+ V4L2_PIX_FMT_NV15, -+}; -+ -+ - static const struct rkvdec_ctrls rkvdec_h264_ctrls = { - .ctrls = rkvdec_h264_ctrl_descs, - .num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs), - }; - --static const u32 rkvdec_h264_vp9_decoded_fmts[] = { -+static const u32 rkvdec_h264_decoded_fmts[] = { - V4L2_PIX_FMT_NV12, -+ V4L2_PIX_FMT_NV15, -+ V4L2_PIX_FMT_NV16, -+ V4L2_PIX_FMT_NV20, - }; - - static const struct rkvdec_ctrl_desc rkvdec_vp9_ctrl_descs[] = { -@@ -112,8 +223,28 @@ static const struct rkvdec_ctrls rkvdec_ - .num_ctrls = ARRAY_SIZE(rkvdec_vp9_ctrl_descs), - }; - -+static const u32 rkvdec_vp9_decoded_fmts[] = { -+ V4L2_PIX_FMT_NV12, -+}; -+ - static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - { -+ .fourcc = V4L2_PIX_FMT_HEVC_SLICE, -+ .frmsize = { -+ .min_width = 64, -+ .max_width = 4096, -+ .step_width = 64, -+ .min_height = 64, -+ .max_height = 2304, -+ .step_height = 16, -+ }, -+ .ctrls = &rkvdec_hevc_ctrls, -+ .ops = &rkvdec_hevc_fmt_ops, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), -+ .decoded_fmts = rkvdec_hevc_decoded_fmts, -+ .capability = RKVDEC_CAPABILITY_HEVC, -+ }, -+ { - .fourcc = V4L2_PIX_FMT_H264_SLICE, - .frmsize = { - .min_width = 48, -@@ -125,9 +256,10 @@ static const struct rkvdec_coded_fmt_des - }, - .ctrls = &rkvdec_h264_ctrls, - .ops = &rkvdec_h264_fmt_ops, -- .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_vp9_decoded_fmts), -- .decoded_fmts = rkvdec_h264_vp9_decoded_fmts, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), -+ .decoded_fmts = rkvdec_h264_decoded_fmts, - .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, -+ .capability = RKVDEC_CAPABILITY_H264, - }, - { - .fourcc = V4L2_PIX_FMT_VP9_FRAME, -@@ -141,18 +273,33 @@ static const struct rkvdec_coded_fmt_des - }, - .ctrls = &rkvdec_vp9_ctrls, - .ops = &rkvdec_vp9_fmt_ops, -- .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_vp9_decoded_fmts), -- .decoded_fmts = rkvdec_h264_vp9_decoded_fmts, -- } -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts), -+ .decoded_fmts = rkvdec_vp9_decoded_fmts, -+ .capability = RKVDEC_CAPABILITY_VP9, -+ }, - }; - - static const struct rkvdec_coded_fmt_desc * --rkvdec_find_coded_fmt_desc(u32 fourcc) -+rkvdec_default_coded_fmt_desc(unsigned int capabilities) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { -+ if (rkvdec_coded_fmts[i].capability & capabilities) -+ return &rkvdec_coded_fmts[i]; -+ } -+ -+ return NULL; -+} -+ -+static const struct rkvdec_coded_fmt_desc * -+rkvdec_find_coded_fmt_desc(u32 fourcc, unsigned int capabilities) - { - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { -- if (rkvdec_coded_fmts[i].fourcc == fourcc) -+ if (rkvdec_coded_fmts[i].fourcc == fourcc && -+ (rkvdec_coded_fmts[i].capability & capabilities)) - return &rkvdec_coded_fmts[i]; - } - -@@ -175,7 +322,7 @@ static void rkvdec_reset_coded_fmt(struc - { - struct v4l2_format *f = &ctx->coded_fmt; - -- ctx->coded_fmt_desc = &rkvdec_coded_fmts[0]; -+ ctx->coded_fmt_desc = rkvdec_default_coded_fmt_desc(ctx->dev->capabilities); - rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->fourcc); - - f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; -@@ -190,26 +337,25 @@ static void rkvdec_reset_decoded_fmt(str - { - struct v4l2_format *f = &ctx->decoded_fmt; - -+ ctx->valid_fmt = 0; - rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]); - f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; -- v4l2_fill_pixfmt_mp(&f->fmt.pix_mp, -- ctx->coded_fmt_desc->decoded_fmts[0], -- ctx->coded_fmt.fmt.pix_mp.width, -- ctx->coded_fmt.fmt.pix_mp.height); -- f->fmt.pix_mp.plane_fmt[0].sizeimage += 128 * -- DIV_ROUND_UP(f->fmt.pix_mp.width, 16) * -- DIV_ROUND_UP(f->fmt.pix_mp.height, 16); -+ f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width; -+ f->fmt.pix_mp.height = ctx->coded_fmt.fmt.pix_mp.height; -+ rkvdec_fill_decoded_pixfmt(ctx, &f->fmt.pix_mp); - } - - static int rkvdec_enum_framesizes(struct file *file, void *priv, - struct v4l2_frmsizeenum *fsize) - { - const struct rkvdec_coded_fmt_desc *fmt; -+ struct rkvdec_dev *rkvdec = video_drvdata(file); - - if (fsize->index != 0) - return -EINVAL; - -- fmt = rkvdec_find_coded_fmt_desc(fsize->pixel_format); -+ fmt = rkvdec_find_coded_fmt_desc(fsize->pixel_format, -+ rkvdec->capabilities); - if (!fmt) - return -EINVAL; - -@@ -249,13 +395,17 @@ static int rkvdec_try_capture_fmt(struct - if (WARN_ON(!coded_desc)) - return -EINVAL; - -- for (i = 0; i < coded_desc->num_decoded_fmts; i++) { -- if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat) -- break; -- } -+ if (ctx->valid_fmt) { -+ pix_mp->pixelformat = ctx->valid_fmt; -+ } else { -+ for (i = 0; i < coded_desc->num_decoded_fmts; i++) { -+ if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat) -+ break; -+ } - -- if (i == coded_desc->num_decoded_fmts) -- pix_mp->pixelformat = coded_desc->decoded_fmts[0]; -+ if (i == coded_desc->num_decoded_fmts) -+ pix_mp->pixelformat = coded_desc->decoded_fmts[0]; -+ } - - /* Always apply the frmsize constraint of the coded end. */ - pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width); -@@ -264,13 +414,7 @@ static int rkvdec_try_capture_fmt(struct - &pix_mp->height, - &coded_desc->frmsize); - -- v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, -- pix_mp->width, pix_mp->height); -- pix_mp->plane_fmt[0].sizeimage += -- 128 * -- DIV_ROUND_UP(pix_mp->width, 16) * -- DIV_ROUND_UP(pix_mp->height, 16); -- pix_mp->field = V4L2_FIELD_NONE; -+ rkvdec_fill_decoded_pixfmt(ctx, pix_mp); - - return 0; - } -@@ -282,10 +426,11 @@ static int rkvdec_try_output_fmt(struct - struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv); - const struct rkvdec_coded_fmt_desc *desc; - -- desc = rkvdec_find_coded_fmt_desc(pix_mp->pixelformat); -+ desc = rkvdec_find_coded_fmt_desc(pix_mp->pixelformat, -+ ctx->dev->capabilities); - if (!desc) { -- pix_mp->pixelformat = rkvdec_coded_fmts[0].fourcc; -- desc = &rkvdec_coded_fmts[0]; -+ desc = rkvdec_default_coded_fmt_desc(ctx->dev->capabilities); -+ pix_mp->pixelformat = desc->fourcc; - } - - v4l2_apply_frmsize_constraints(&pix_mp->width, -@@ -325,6 +470,7 @@ static int rkvdec_s_capture_fmt(struct f - return ret; - - ctx->decoded_fmt = *f; -+ ctx->valid_fmt = f->fmt.pix_mp.pixelformat; - return 0; - } - -@@ -362,7 +508,8 @@ static int rkvdec_s_output_fmt(struct fi - if (ret) - return ret; - -- desc = rkvdec_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat); -+ desc = rkvdec_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat, -+ ctx->dev->capabilities); - if (!desc) - return -EINVAL; - ctx->coded_fmt_desc = desc; -@@ -413,7 +560,10 @@ static int rkvdec_g_capture_fmt(struct f - static int rkvdec_enum_output_fmt(struct file *file, void *priv, - struct v4l2_fmtdesc *f) - { -- if (f->index >= ARRAY_SIZE(rkvdec_coded_fmts)) -+ struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv); -+ -+ if (f->index >= ARRAY_SIZE(rkvdec_coded_fmts) || -+ !(ctx->dev->capabilities & rkvdec_coded_fmts[f->index].capability)) - return -EINVAL; - - f->pixelformat = rkvdec_coded_fmts[f->index].fourcc; -@@ -428,6 +578,14 @@ static int rkvdec_enum_capture_fmt(struc - if (WARN_ON(!ctx->coded_fmt_desc)) - return -EINVAL; - -+ if (ctx->valid_fmt) { -+ if (f->index) -+ return -EINVAL; -+ -+ f->pixelformat = ctx->valid_fmt; -+ return 0; -+ } -+ - if (f->index >= ctx->coded_fmt_desc->num_decoded_fmts) - return -EINVAL; - -@@ -658,6 +816,11 @@ static void rkvdec_job_finish(struct rkv - - pm_runtime_mark_last_busy(rkvdec->dev); - pm_runtime_put_autosuspend(rkvdec->dev); -+ -+ if (result == VB2_BUF_STATE_ERROR && -+ rkvdec->reset_mask == RESET_NONE) -+ rkvdec->reset_mask |= RESET_SOFT; -+ - rkvdec_job_finish_no_pm(ctx, result); - } - -@@ -695,6 +858,33 @@ static void rkvdec_device_run(void *priv - - if (WARN_ON(!desc)) - return; -+ if (rkvdec->reset_mask != RESET_NONE) { -+ -+ if (rkvdec->reset_mask & RESET_SOFT) { -+ writel(RKVDEC_SOFTRST_EN_P, -+ rkvdec->regs + RKVDEC_REG_INTERRUPT); -+ udelay(RKVDEC_RESET_DELAY); -+ if (readl(rkvdec->regs + RKVDEC_REG_INTERRUPT) -+ & RKVDEC_SOFTRESET_RDY) -+ dev_info_ratelimited(rkvdec->dev, -+ "softreset failed\n"); -+ } -+ -+ if (rkvdec->reset_mask & RESET_HARD) { -+ rockchip_pmu_idle_request(rkvdec->dev, true); -+ ret = reset_control_assert(rkvdec->rstc); -+ if (!ret) { -+ udelay(RKVDEC_RESET_DELAY); -+ ret = reset_control_deassert(rkvdec->rstc); -+ } -+ rockchip_pmu_idle_request(rkvdec->dev, false); -+ if (ret) -+ dev_notice_ratelimited(rkvdec->dev, -+ "hardreset failed\n"); -+ } -+ rkvdec->reset_mask = RESET_NONE; -+ pm_runtime_suspend(rkvdec->dev); -+ } - - ret = pm_runtime_resume_and_get(rkvdec->dev); - if (ret < 0) { -@@ -781,14 +971,17 @@ static int rkvdec_init_ctrls(struct rkvd - int ret; - - for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) -- nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls; -+ if (rkvdec_coded_fmts[i].capability & ctx->dev->capabilities) -+ nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls; - - v4l2_ctrl_handler_init(&ctx->ctrl_hdl, nctrls); - - for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { -- ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls); -- if (ret) -- goto err_free_handler; -+ if (rkvdec_coded_fmts[i].capability & ctx->dev->capabilities) { -+ ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls); -+ if (ret) -+ goto err_free_handler; -+ } - } - - ret = v4l2_ctrl_handler_setup(&ctx->ctrl_hdl); -@@ -961,6 +1154,11 @@ static irqreturn_t rkvdec_irq_handler(in - if (cancel_delayed_work(&rkvdec->watchdog_work)) { - struct rkvdec_ctx *ctx; - -+ if (state == VB2_BUF_STATE_ERROR) { -+ rkvdec->reset_mask |= (status & RKVDEC_ERR_MASK) ? -+ RESET_HARD : RESET_SOFT; -+ } -+ - ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); - rkvdec_job_finish(ctx, state); - } -@@ -978,14 +1176,32 @@ static void rkvdec_watchdog_func(struct - ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); - if (ctx) { - dev_err(rkvdec->dev, "Frame processing timed out!\n"); -+ rkvdec->reset_mask |= RESET_HARD; - writel(RKVDEC_IRQ_DIS, rkvdec->regs + RKVDEC_REG_INTERRUPT); - writel(0, rkvdec->regs + RKVDEC_REG_SYSCTRL); - rkvdec_job_finish(ctx, VB2_BUF_STATE_ERROR); - } - } - -+static const struct rkvdec_variant rk3399_rkvdec_variant = { -+ .capabilities = RKVDEC_CAPABILITY_H264 | -+ RKVDEC_CAPABILITY_HEVC | -+ RKVDEC_CAPABILITY_VP9 -+}; -+ -+static const struct rkvdec_variant rk3288_hevc_variant = { -+ .capabilities = RKVDEC_CAPABILITY_HEVC -+}; -+ - static const struct of_device_id of_rkvdec_match[] = { -- { .compatible = "rockchip,rk3399-vdec" }, -+ { -+ .compatible = "rockchip,rk3399-vdec", -+ .data = &rk3399_rkvdec_variant, -+ }, -+ { -+ .compatible = "rockchip,rk3288-hevc", -+ .data = &rk3288_hevc_variant, -+ }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, of_rkvdec_match); -@@ -997,6 +1213,7 @@ static const char * const rkvdec_clk_nam - static int rkvdec_probe(struct platform_device *pdev) - { - struct rkvdec_dev *rkvdec; -+ const struct rkvdec_variant *variant; - unsigned int i; - int ret, irq; - -@@ -1022,6 +1239,13 @@ static int rkvdec_probe(struct platform_ - if (ret) - return ret; - -+ variant = of_device_get_match_data(rkvdec->dev); -+ if (!variant) -+ return -EINVAL; -+ -+ rkvdec->capabilities = variant->capabilities; -+ -+ - rkvdec->regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(rkvdec->regs)) - return PTR_ERR(rkvdec->regs); -@@ -1046,6 +1270,18 @@ static int rkvdec_probe(struct platform_ - return ret; - } - -+ -+ rkvdec->rstc = devm_reset_control_array_get(&pdev->dev, false, true); -+ if (IS_ERR(rkvdec->rstc)) { -+ dev_err(&pdev->dev, -+ "get resets failed %ld\n", PTR_ERR(rkvdec->rstc)); -+ return PTR_ERR(rkvdec->rstc); -+ } else { -+ dev_dbg(&pdev->dev, -+ "requested %d resets\n", -+ reset_control_get_count(&pdev->dev)); -+ } -+ - pm_runtime_set_autosuspend_delay(&pdev->dev, 100); - pm_runtime_use_autosuspend(&pdev->dev); - pm_runtime_enable(&pdev->dev); -@@ -1068,9 +1304,9 @@ static int rkvdec_remove(struct platform - - cancel_delayed_work_sync(&rkvdec->watchdog_work); - -- rkvdec_v4l2_cleanup(rkvdec); -- pm_runtime_disable(&pdev->dev); - pm_runtime_dont_use_autosuspend(&pdev->dev); -+ pm_runtime_disable(&pdev->dev); -+ rkvdec_v4l2_cleanup(rkvdec); - return 0; - } - -diff -rupN linux.orig/drivers/staging/media/rkvdec/rkvdec.h linux/drivers/staging/media/rkvdec/rkvdec.h ---- linux.orig/drivers/staging/media/rkvdec/rkvdec.h 2024-01-03 20:53:31.439335419 +0000 -+++ linux/drivers/staging/media/rkvdec/rkvdec.h 2024-01-03 21:27:48.651744306 +0000 -@@ -11,10 +11,11 @@ - #ifndef RKVDEC_H_ - #define RKVDEC_H_ - -+#include - #include -+#include - #include - #include --#include - - #include - #include -@@ -22,6 +23,16 @@ - #include - #include - -+#define RESET_NONE 0 -+#define RESET_SOFT BIT(0) -+#define RESET_HARD BIT(1) -+ -+#define RKVDEC_RESET_DELAY 5 -+ -+#define RKVDEC_CAPABILITY_H264 BIT(0) -+#define RKVDEC_CAPABILITY_HEVC BIT(1) -+#define RKVDEC_CAPABILITY_VP9 BIT(2) -+ - struct rkvdec_ctx; - - struct rkvdec_ctrl_desc { -@@ -63,9 +74,14 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buf - base.vb.vb2_buf); - } - -+struct rkvdec_variant { -+ unsigned int capabilities; -+}; -+ - struct rkvdec_coded_fmt_ops { - int (*adjust_fmt)(struct rkvdec_ctx *ctx, - struct v4l2_format *f); -+ u32 (*valid_fmt)(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl); - int (*start)(struct rkvdec_ctx *ctx); - void (*stop)(struct rkvdec_ctx *ctx); - int (*run)(struct rkvdec_ctx *ctx); -@@ -83,6 +99,7 @@ struct rkvdec_coded_fmt_desc { - unsigned int num_decoded_fmts; - const u32 *decoded_fmts; - u32 subsystem_flags; -+ unsigned int capability; - }; - - struct rkvdec_dev { -@@ -95,12 +112,16 @@ struct rkvdec_dev { - void __iomem *regs; - struct mutex vdev_lock; /* serializes ioctls */ - struct delayed_work watchdog_work; -+ struct reset_control *rstc; -+ u8 reset_mask; -+ unsigned int capabilities; - }; - - struct rkvdec_ctx { - struct v4l2_fh fh; - struct v4l2_format coded_fmt; - struct v4l2_format decoded_fmt; -+ u32 valid_fmt; - const struct rkvdec_coded_fmt_desc *coded_fmt_desc; - struct v4l2_ctrl_handler ctrl_hdl; - struct rkvdec_dev *dev; -@@ -122,6 +143,7 @@ void rkvdec_run_preamble(struct rkvdec_c - void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); - - extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops; -+extern const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops; - extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops; - - #endif /* RKVDEC_H_ */ -diff -rupN linux.orig/include/drm/bridge/dw_hdmi.h linux/include/drm/bridge/dw_hdmi.h ---- linux.orig/include/drm/bridge/dw_hdmi.h 2024-01-03 20:53:31.683338719 +0000 -+++ linux/include/drm/bridge/dw_hdmi.h 2024-01-03 21:17:09.402615966 +0000 -@@ -156,10 +156,12 @@ struct dw_hdmi_plat_data { - - /* Synopsys PHY support */ - const struct dw_hdmi_mpll_config *mpll_cfg; -+ const struct dw_hdmi_mpll_config *mpll_cfg_420; - const struct dw_hdmi_curr_ctrl *cur_ctr; - const struct dw_hdmi_phy_config *phy_config; - int (*configure_phy)(struct dw_hdmi *hdmi, void *data, -- unsigned long mpixelclock); -+ unsigned long mpixelclock, -+ unsigned long mtmdsclock); - - unsigned int disable_cec : 1; - }; -diff -rupN linux.orig/include/linux/rockchip_pmu.h linux/include/linux/rockchip_pmu.h ---- linux.orig/include/linux/rockchip_pmu.h 1970-01-01 00:00:00.000000000 +0000 -+++ linux/include/linux/rockchip_pmu.h 2024-01-03 21:26:02.707011192 +0000 -@@ -0,0 +1,15 @@ -+/* -+ * pm_domain.h - Definitions and headers related to device power domains. -+ * -+ * Copyright (C) 2017 Randy Li . -+ * -+ * This file is released under the GPLv2. -+ */ -+ -+#ifndef _LINUX_ROCKCHIP_PM_H -+#define _LINUX_ROCKCHIP_PM_H -+#include -+ -+int rockchip_pmu_idle_request(struct device *dev, bool idle); -+ -+#endif /* _LINUX_ROCKCHIP_PM_H */ -diff -rupN linux.orig/include/media/cec.h linux/include/media/cec.h ---- linux.orig/include/media/cec.h 2024-01-03 20:53:31.811340450 +0000 -+++ linux/include/media/cec.h 2024-01-03 21:17:09.402615966 +0000 -@@ -239,6 +239,8 @@ struct cec_adapter { - struct task_struct *kthread; - wait_queue_head_t kthread_waitq; - -+ struct delayed_work debounce_work; -+ - const struct cec_adap_ops *ops; - void *priv; - u32 capabilities; -diff -rupN linux.orig/include/soc/rockchip/pm_domains.h linux/include/soc/rockchip/pm_domains.h ---- linux.orig/include/soc/rockchip/pm_domains.h 2024-01-03 20:53:31.831340722 +0000 -+++ linux/include/soc/rockchip/pm_domains.h 2024-01-03 21:26:02.707011192 +0000 -@@ -10,6 +10,7 @@ - - int rockchip_pmu_block(void); - void rockchip_pmu_unblock(void); -+int rockchip_pmu_idle_request(struct device *dev, bool idle); - - #else /* CONFIG_ROCKCHIP_PM_DOMAINS */ - -@@ -20,6 +21,11 @@ static inline int rockchip_pmu_block(voi - - static inline void rockchip_pmu_unblock(void) { } - -+static inline int rockchip_pmu_idle_request(struct device *dev, bool idle) -+{ -+ return -ENOTSUPP; -+} -+ - #endif /* CONFIG_ROCKCHIP_PM_DOMAINS */ - - #endif /* __SOC_ROCKCHIP_PM_DOMAINS_H__ */ -diff -rupN linux.orig/include/uapi/drm/drm_fourcc.h linux/include/uapi/drm/drm_fourcc.h ---- linux.orig/include/uapi/drm/drm_fourcc.h 2024-01-03 20:53:31.843340883 +0000 -+++ linux/include/uapi/drm/drm_fourcc.h 2024-01-03 21:08:52.940067739 +0000 -@@ -311,6 +311,8 @@ extern "C" { - * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian - */ - #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */ -+#define DRM_FORMAT_NV20 fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */ -+#define DRM_FORMAT_NV30 fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */ - - /* - * 2 plane YCbCr MSB aligned -diff -rupN linux.orig/include/uapi/linux/videodev2.h linux/include/uapi/linux/videodev2.h ---- linux.orig/include/uapi/linux/videodev2.h 2024-01-03 20:53:31.871341262 +0000 -+++ linux/include/uapi/linux/videodev2.h 2024-01-03 21:03:19.317345475 +0000 -@@ -627,6 +627,9 @@ struct v4l2_pix_format { - #define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/CrCb 4:4:4 */ - #define V4L2_PIX_FMT_P010 v4l2_fourcc('P', '0', '1', '0') /* 24 Y/CbCr 4:2:0 10-bit per component */ - -+#define V4L2_PIX_FMT_NV15 v4l2_fourcc('N', 'V', '1', '5') /* 15 Y/UV 4:2:0 10-bit packed */ -+#define V4L2_PIX_FMT_NV20 v4l2_fourcc('N', 'V', '2', '0') /* 20 Y/UV 4:2:2 10-bit packed */ -+ - /* two non contiguous planes - one Y, one Cr + Cb interleaved */ - #define V4L2_PIX_FMT_NV12M v4l2_fourcc('N', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 */ - #define V4L2_PIX_FMT_NV21M v4l2_fourcc('N', 'M', '2', '1') /* 21 Y/CrCb 4:2:0 */ -diff -rupN linux.orig/sound/soc/codecs/hdmi-codec.c linux/sound/soc/codecs/hdmi-codec.c ---- linux.orig/sound/soc/codecs/hdmi-codec.c 2024-01-03 20:53:32.111344512 +0000 -+++ linux/sound/soc/codecs/hdmi-codec.c 2024-01-03 21:27:13.822235237 +0000 -@@ -190,78 +190,69 @@ static const struct snd_pcm_chmap_elem h - */ - static const struct hdmi_codec_cea_spk_alloc hdmi_codec_channel_alloc[] = { - { .ca_id = 0x00, .n_ch = 2, -- .mask = FL | FR}, -- /* 2.1 */ -- { .ca_id = 0x01, .n_ch = 4, -- .mask = FL | FR | LFE}, -- /* Dolby Surround */ -+ .mask = FL | FR }, -+ { .ca_id = 0x03, .n_ch = 4, -+ .mask = FL | FR | LFE | FC }, - { .ca_id = 0x02, .n_ch = 4, - .mask = FL | FR | FC }, -- /* surround51 */ -+ { .ca_id = 0x01, .n_ch = 4, -+ .mask = FL | FR | LFE }, - { .ca_id = 0x0b, .n_ch = 6, -- .mask = FL | FR | LFE | FC | RL | RR}, -- /* surround40 */ -- { .ca_id = 0x08, .n_ch = 6, -- .mask = FL | FR | RL | RR }, -- /* surround41 */ -- { .ca_id = 0x09, .n_ch = 6, -- .mask = FL | FR | LFE | RL | RR }, -- /* surround50 */ -+ .mask = FL | FR | LFE | FC | RL | RR }, - { .ca_id = 0x0a, .n_ch = 6, - .mask = FL | FR | FC | RL | RR }, -- /* 6.1 */ -- { .ca_id = 0x0f, .n_ch = 8, -- .mask = FL | FR | LFE | FC | RL | RR | RC }, -- /* surround71 */ -+ { .ca_id = 0x09, .n_ch = 6, -+ .mask = FL | FR | LFE | RL | RR }, -+ { .ca_id = 0x08, .n_ch = 6, -+ .mask = FL | FR | RL | RR }, -+ { .ca_id = 0x07, .n_ch = 6, -+ .mask = FL | FR | LFE | FC | RC }, -+ { .ca_id = 0x06, .n_ch = 6, -+ .mask = FL | FR | FC | RC }, -+ { .ca_id = 0x05, .n_ch = 6, -+ .mask = FL | FR | LFE | RC }, -+ { .ca_id = 0x04, .n_ch = 6, -+ .mask = FL | FR | RC }, - { .ca_id = 0x13, .n_ch = 8, - .mask = FL | FR | LFE | FC | RL | RR | RLC | RRC }, -- /* others */ -- { .ca_id = 0x03, .n_ch = 8, -- .mask = FL | FR | LFE | FC }, -- { .ca_id = 0x04, .n_ch = 8, -- .mask = FL | FR | RC}, -- { .ca_id = 0x05, .n_ch = 8, -- .mask = FL | FR | LFE | RC }, -- { .ca_id = 0x06, .n_ch = 8, -- .mask = FL | FR | FC | RC }, -- { .ca_id = 0x07, .n_ch = 8, -- .mask = FL | FR | LFE | FC | RC }, -- { .ca_id = 0x0c, .n_ch = 8, -- .mask = FL | FR | RC | RL | RR }, -- { .ca_id = 0x0d, .n_ch = 8, -- .mask = FL | FR | LFE | RL | RR | RC }, -- { .ca_id = 0x0e, .n_ch = 8, -- .mask = FL | FR | FC | RL | RR | RC }, -- { .ca_id = 0x10, .n_ch = 8, -- .mask = FL | FR | RL | RR | RLC | RRC }, -- { .ca_id = 0x11, .n_ch = 8, -- .mask = FL | FR | LFE | RL | RR | RLC | RRC }, -+ { .ca_id = 0x1f, .n_ch = 8, -+ .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC }, - { .ca_id = 0x12, .n_ch = 8, - .mask = FL | FR | FC | RL | RR | RLC | RRC }, -- { .ca_id = 0x14, .n_ch = 8, -- .mask = FL | FR | FLC | FRC }, -- { .ca_id = 0x15, .n_ch = 8, -- .mask = FL | FR | LFE | FLC | FRC }, -- { .ca_id = 0x16, .n_ch = 8, -- .mask = FL | FR | FC | FLC | FRC }, -- { .ca_id = 0x17, .n_ch = 8, -- .mask = FL | FR | LFE | FC | FLC | FRC }, -- { .ca_id = 0x18, .n_ch = 8, -- .mask = FL | FR | RC | FLC | FRC }, -- { .ca_id = 0x19, .n_ch = 8, -- .mask = FL | FR | LFE | RC | FLC | FRC }, -- { .ca_id = 0x1a, .n_ch = 8, -- .mask = FL | FR | RC | FC | FLC | FRC }, -- { .ca_id = 0x1b, .n_ch = 8, -- .mask = FL | FR | LFE | RC | FC | FLC | FRC }, -- { .ca_id = 0x1c, .n_ch = 8, -- .mask = FL | FR | RL | RR | FLC | FRC }, -- { .ca_id = 0x1d, .n_ch = 8, -- .mask = FL | FR | LFE | RL | RR | FLC | FRC }, - { .ca_id = 0x1e, .n_ch = 8, - .mask = FL | FR | FC | RL | RR | FLC | FRC }, -- { .ca_id = 0x1f, .n_ch = 8, -- .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC }, -+ { .ca_id = 0x11, .n_ch = 8, -+ .mask = FL | FR | LFE | RL | RR | RLC | RRC }, -+ { .ca_id = 0x1d, .n_ch = 8, -+ .mask = FL | FR | LFE | RL | RR | FLC | FRC }, -+ { .ca_id = 0x10, .n_ch = 8, -+ .mask = FL | FR | RL | RR | RLC | RRC }, -+ { .ca_id = 0x1c, .n_ch = 8, -+ .mask = FL | FR | RL | RR | FLC | FRC }, -+ { .ca_id = 0x0f, .n_ch = 8, -+ .mask = FL | FR | LFE | FC | RL | RR | RC }, -+ { .ca_id = 0x1b, .n_ch = 8, -+ .mask = FL | FR | LFE | RC | FC | FLC | FRC }, -+ { .ca_id = 0x0e, .n_ch = 8, -+ .mask = FL | FR | FC | RL | RR | RC }, -+ { .ca_id = 0x1a, .n_ch = 8, -+ .mask = FL | FR | RC | FC | FLC | FRC }, -+ { .ca_id = 0x0d, .n_ch = 8, -+ .mask = FL | FR | LFE | RL | RR | RC }, -+ { .ca_id = 0x19, .n_ch = 8, -+ .mask = FL | FR | LFE | RC | FLC | FRC }, -+ { .ca_id = 0x0c, .n_ch = 8, -+ .mask = FL | FR | RC | RL | RR }, -+ { .ca_id = 0x18, .n_ch = 8, -+ .mask = FL | FR | RC | FLC | FRC }, -+ { .ca_id = 0x17, .n_ch = 8, -+ .mask = FL | FR | LFE | FC | FLC | FRC }, -+ { .ca_id = 0x16, .n_ch = 8, -+ .mask = FL | FR | FC | FLC | FRC }, -+ { .ca_id = 0x15, .n_ch = 8, -+ .mask = FL | FR | LFE | FLC | FRC }, -+ { .ca_id = 0x14, .n_ch = 8, -+ .mask = FL | FR | FLC | FRC }, - }; - - struct hdmi_codec_priv { diff --git a/projects/Rockchip/packages/linux/patches/RK3399/008-goodix-reset.patch b/projects/Rockchip/packages/linux/patches/RK3399/008-goodix-reset.patch deleted file mode 100644 index a8caba8dd..000000000 --- a/projects/Rockchip/packages/linux/patches/RK3399/008-goodix-reset.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -rupN linux.orig/drivers/input/touchscreen/goodix.c linux/drivers/input/touchscreen/goodix.c ---- linux.orig/drivers/input/touchscreen/goodix.c 2024-01-02 16:20:16.170247325 +0000 -+++ linux/drivers/input/touchscreen/goodix.c 2024-01-03 15:28:50.457334216 +0000 -@@ -1007,6 +1007,8 @@ retry_get_irq_gpio: - - /* Get the reset line GPIO pin number */ - gpiod = devm_gpiod_get_optional(dev, GOODIX_GPIO_RST_NAME, ts->gpiod_rst_flags); -+ if (IS_ERR(gpiod)) -+ gpiod = devm_gpiod_get_optional(dev, GOODIX_GPIO_RST_NAME, GPIOD_OUT_LOW); - if (IS_ERR(gpiod)) { - error = PTR_ERR(gpiod); - if (error != -EPROBE_DEFER) diff --git a/projects/Rockchip/packages/linux/patches/RK3399/999-clear-log-spam.patch b/projects/Rockchip/packages/linux/patches/RK3399/999-clear-log-spam.patch new file mode 100644 index 000000000..7477480d0 --- /dev/null +++ b/projects/Rockchip/packages/linux/patches/RK3399/999-clear-log-spam.patch @@ -0,0 +1,31 @@ +diff -rupN linux.orig/drivers/gpio/gpio-rockchip.c linux/drivers/gpio/gpio-rockchip.c +--- linux.orig/drivers/gpio/gpio-rockchip.c 2023-12-22 04:23:33.879905917 +0000 ++++ linux/drivers/gpio/gpio-rockchip.c 2023-12-22 05:08:03.636801366 +0000 +@@ -335,13 +335,13 @@ static void rockchip_irq_demux(struct ir + unsigned long pending; + unsigned int irq; + +- dev_dbg(bank->dev, "got irq for bank %s\n", bank->name); ++ //dev_dbg(bank->dev, "got irq for bank %s\n", bank->name); + + chained_irq_enter(chip, desc); + + pending = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status); + for_each_set_bit(irq, &pending, 32) { +- dev_dbg(bank->dev, "handling irq %d\n", irq); ++ //dev_dbg(bank->dev, "handling irq %d\n", irq); + + /* + * Triggering IRQ on both rising and falling edge +diff -rupN linux.orig/drivers/input/touchscreen/goodix.c linux/drivers/input/touchscreen/goodix.c +--- linux.orig/drivers/input/touchscreen/goodix.c 2023-12-22 04:23:34.199912947 +0000 ++++ linux/drivers/input/touchscreen/goodix.c 2023-12-22 05:08:59.121963345 +0000 +@@ -1019,7 +1019,7 @@ retry_get_irq_gpio: + default: + if (ts->gpiod_int && ts->gpiod_rst) { + ts->reset_controller_at_probe = true; +- ts->load_cfg_from_disk = true; ++ ts->load_cfg_from_disk = false; + ts->irq_pin_access_method = IRQ_PIN_ACCESS_GPIO; + } + } diff --git a/projects/Rockchip/packages/linux/patches/RK3399/999-remove-log-spam.patch b/projects/Rockchip/packages/linux/patches/RK3399/999-remove-log-spam.patch deleted file mode 100644 index 93a8bd1ce..000000000 --- a/projects/Rockchip/packages/linux/patches/RK3399/999-remove-log-spam.patch +++ /dev/null @@ -1,54 +0,0 @@ -diff -rupN linux.orig/drivers/input/touchscreen/goodix.c linux/drivers/input/touchscreen/goodix.c ---- linux.orig/drivers/input/touchscreen/goodix.c 2023-12-15 19:18:57.364913158 +0000 -+++ linux/drivers/input/touchscreen/goodix.c 2023-12-15 19:20:05.987107578 +0000 -@@ -1037,7 +1037,7 @@ retry_get_irq_gpio: - default: - if (ts->gpiod_int && ts->gpiod_rst) { - ts->reset_controller_at_probe = true; -- ts->load_cfg_from_disk = true; -+ ts->load_cfg_from_disk = false; - ts->irq_pin_access_method = IRQ_PIN_ACCESS_GPIO; - } - } -diff -rupN linux.orig/drivers/gpio/gpio-rockchip.c linux/drivers/gpio/gpio-rockchip.c ---- linux.orig/drivers/gpio/gpio-rockchip.c 2023-12-15 19:18:55.020838176 +0000 -+++ linux/drivers/gpio/gpio-rockchip.c 2023-12-15 19:20:05.987107578 +0000 -@@ -335,13 +335,13 @@ static void rockchip_irq_demux(struct ir - unsigned long pending; - unsigned int irq; - -- dev_dbg(bank->dev, "got irq for bank %s\n", bank->name); -+ //dev_dbg(bank->dev, "got irq for bank %s\n", bank->name); - - chained_irq_enter(chip, desc); - - pending = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status); - for_each_set_bit(irq, &pending, 32) { -- dev_dbg(bank->dev, "handling irq %d\n", irq); -+ //dev_dbg(bank->dev, "handling irq %d\n", irq); - - /* - * Triggering IRQ on both rising and falling edge -diff --git a/sound/soc/soc-pcm.c b/sound/soc/soc-pcm.c -index f3964060a044..dc1ffb3a098b 100644 ---- a/sound/soc/soc-pcm.c -+++ b/sound/soc/soc-pcm.c -@@ -41,9 +41,6 @@ static inline int _soc_pcm_ret(struct snd_soc_pcm_runtime *rtd, - case -ENOTSUPP: - break; - default: -- dev_err(rtd->dev, -- "ASoC: error at %s on %s: %d\n", -- func, rtd->dai_link->name, ret); - } - - return ret; -@@ -2438,8 +2435,6 @@ static int dpcm_fe_dai_prepare(struct snd_pcm_substream *substream) - - /* there is no point preparing this FE if there are no BEs */ - if (list_empty(&fe->dpcm[stream].be_clients)) { -- dev_err(fe->dev, "ASoC: no backend DAIs enabled for %s\n", -- fe->dai_link->name); - ret = -EINVAL; - goto out; - } diff --git a/projects/Rockchip/packages/u-boot/patches/RK3399/000-fix-gcc13.patch b/projects/Rockchip/packages/u-boot/patches/RK3399/000-fix-gcc13.patch deleted file mode 100644 index c84b52123..000000000 --- a/projects/Rockchip/packages/u-boot/patches/RK3399/000-fix-gcc13.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff --git a/Makefile b/Makefile -index ff76e8559..3ebe059b9 100644 ---- a/Makefile -+++ b/Makefile -@@ -606,6 +606,7 @@ endif - - KBUILD_CFLAGS += $(call cc-option,-Wno-format-nonliteral) - KBUILD_CFLAGS += $(call cc-disable-warning, address-of-packed-member) -+KBUILD_CFLAGS += $(call cc-disable-warning, enum-int-mismatch) - - # turn jbsr into jsr for m68k - ifeq ($(ARCH),m68k)