diff -rupN linux.orig/drivers/gpu/drm/panel/panel-elida-kd35t133.c linux/drivers/gpu/drm/panel/panel-elida-kd35t133.c
--- linux.orig/drivers/gpu/drm/panel/panel-elida-kd35t133.c	2024-01-17 03:47:11.674388741 +0000
+++ linux/drivers/gpu/drm/panel/panel-elida-kd35t133.c	2024-01-17 04:02:49.500183606 +0000
@@ -107,6 +107,8 @@ static int kd35t133_unprepare(struct drm
 	regulator_disable(ctx->iovcc);
 	regulator_disable(ctx->vdd);
 
+	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+
 	ctx->prepared = false;
 
 	return 0;
diff -rupN linux.orig/drivers/gpu/drm/panel/panel-newvision-nv3051d.c linux/drivers/gpu/drm/panel/panel-newvision-nv3051d.c
--- linux.orig/drivers/gpu/drm/panel/panel-newvision-nv3051d.c	2024-01-17 03:47:11.678388835 +0000
+++ linux/drivers/gpu/drm/panel/panel-newvision-nv3051d.c	2024-01-17 04:02:49.500183606 +0000
@@ -28,6 +28,7 @@ struct nv3051d_panel_info {
 	unsigned int num_modes;
 	u16 width_mm, height_mm;
 	u32 bus_flags;
+	unsigned long mode_flags;
 };
 
 struct panel_nv3051d {
@@ -385,15 +386,7 @@ static int panel_nv3051d_probe(struct mi
 
 	dsi->lanes = 4;
 	dsi->format = MIPI_DSI_FMT_RGB888;
-	dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
-			  MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET;
-
-	/*
-	 * The panel in the RG351V is identical to the 353P, except it
-	 * requires MIPI_DSI_CLOCK_NON_CONTINUOUS to operate correctly.
-	 */
-	if (of_device_is_compatible(dev->of_node, "anbernic,rg351v-panel"))
-		dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS;
+	dsi->mode_flags = ctx->panel_info->mode_flags;
 
 	drm_panel_init(&ctx->panel, &dsi->dev, &panel_nv3051d_funcs,
 		       DRM_MODE_CONNECTOR_DSI);
@@ -487,10 +480,24 @@ static const struct nv3051d_panel_info n
 	.width_mm = 70,
 	.height_mm = 57,
 	.bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
+	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+		      MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET,
+};
+
+static const struct nv3051d_panel_info nv3051d_rg351v_info = {
+	.display_modes = nv3051d_rgxx3_modes,
+	.num_modes = ARRAY_SIZE(nv3051d_rgxx3_modes),
+	.width_mm = 70,
+	.height_mm = 57,
+	.bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
+	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+		      MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET |
+		      MIPI_DSI_CLOCK_NON_CONTINUOUS,
 };
 
 static const struct of_device_id newvision_nv3051d_of_match[] = {
 	{ .compatible = "newvision,nv3051d", .data = &nv3051d_rgxx3_info },
+	{ .compatible = "anbernic,rg351v-panel", .data = &nv3051d_rg351v_info },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, newvision_nv3051d_of_match);
diff -rupN linux.orig/drivers/gpu/drm/panel/panel-sitronix-st7703.c linux/drivers/gpu/drm/panel/panel-sitronix-st7703.c
--- linux.orig/drivers/gpu/drm/panel/panel-sitronix-st7703.c	2024-01-17 03:47:11.678388835 +0000
+++ linux/drivers/gpu/drm/panel/panel-sitronix-st7703.c	2024-01-17 04:03:24.432977809 +0000
@@ -13,7 +13,7 @@
 #include <linux/media-bus-format.h>
 #include <linux/mod_devicetable.h>
 #include <linux/module.h>
-#include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/regulator/consumer.h>
 
 #include <video/display_timing.h>
@@ -46,6 +46,7 @@
 #define ST7703_CMD_SETIO	 0xC7
 #define ST7703_CMD_SETCABC	 0xC8
 #define ST7703_CMD_SETPANEL	 0xCC
+#define ST7703_CMD_UNKNOWN_C6	 0xC6
 #define ST7703_CMD_SETGAMMA	 0xE0
 #define ST7703_CMD_SETEQ	 0xE3
 #define ST7703_CMD_SETGIP1	 0xE9
@@ -77,6 +78,14 @@ static inline struct st7703 *panel_to_st
 	return container_of(panel, struct st7703, panel);
 }
 
+#define dsi_generic_write_seq(dsi, seq...) do {				\
+		static const u8 d[] = { seq };				\
+		int ret;						\
+		ret = mipi_dsi_generic_write(dsi, d, ARRAY_SIZE(d));	\
+		if (ret < 0)						\
+			return ret;					\
+	} while (0)
+
 static int jh057n_init_sequence(struct st7703 *ctx)
 {
 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
@@ -86,27 +95,27 @@ static int jh057n_init_sequence(struct s
 	 * resemble the ST7703 but the number of parameters often don't match
 	 * so it's likely a clone.
 	 */
-	mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETEXTC,
+	dsi_generic_write_seq(dsi, ST7703_CMD_SETEXTC,
 				   0xF1, 0x12, 0x83);
-	mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETRGBIF,
+	dsi_generic_write_seq(dsi, ST7703_CMD_SETRGBIF,
 				   0x10, 0x10, 0x05, 0x05, 0x03, 0xFF, 0x00, 0x00,
 				   0x00, 0x00);
-	mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETSCR,
+	dsi_generic_write_seq(dsi, ST7703_CMD_SETSCR,
 				   0x73, 0x73, 0x50, 0x50, 0x00, 0x00, 0x08, 0x70,
 				   0x00);
-	mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETVDC, 0x4E);
-	mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETPANEL, 0x0B);
-	mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETCYC, 0x80);
-	mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETDISP, 0xF0, 0x12, 0x30);
-	mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETEQ,
+	dsi_generic_write_seq(dsi, ST7703_CMD_SETVDC, 0x4E);
+	dsi_generic_write_seq(dsi, ST7703_CMD_SETPANEL, 0x0B);
+	dsi_generic_write_seq(dsi, ST7703_CMD_SETCYC, 0x80);
+	dsi_generic_write_seq(dsi, ST7703_CMD_SETDISP, 0xF0, 0x12, 0x30);
+	dsi_generic_write_seq(dsi, ST7703_CMD_SETEQ,
 				   0x07, 0x07, 0x0B, 0x0B, 0x03, 0x0B, 0x00, 0x00,
 				   0x00, 0x00, 0xFF, 0x00, 0xC0, 0x10);
-	mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETBGP, 0x08, 0x08);
+	dsi_generic_write_seq(dsi, ST7703_CMD_SETBGP, 0x08, 0x08);
 	msleep(20);
 
-	mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETVCOM, 0x3F, 0x3F);
-	mipi_dsi_generic_write_seq(dsi, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00);
-	mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETGIP1,
+	dsi_generic_write_seq(dsi, ST7703_CMD_SETVCOM, 0x3F, 0x3F);
+	dsi_generic_write_seq(dsi, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00);
+	dsi_generic_write_seq(dsi, ST7703_CMD_SETGIP1,
 				   0x82, 0x10, 0x06, 0x05, 0x9E, 0x0A, 0xA5, 0x12,
 				   0x31, 0x23, 0x37, 0x83, 0x04, 0xBC, 0x27, 0x38,
 				   0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0C, 0x00,
@@ -115,7 +124,7 @@ static int jh057n_init_sequence(struct s
 				   0x64, 0x20, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
 				   0x02, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 				   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
-	mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETGIP2,
+	dsi_generic_write_seq(dsi, ST7703_CMD_SETGIP2,
 				   0x02, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 				   0x00, 0x00, 0x00, 0x00, 0x02, 0x46, 0x02, 0x88,
 				   0x88, 0x88, 0x88, 0x88, 0x88, 0x64, 0x88, 0x13,
@@ -124,7 +133,7 @@ static int jh057n_init_sequence(struct s
 				   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 				   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0A,
 				   0xA5, 0x00, 0x00, 0x00, 0x00);
-	mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETGAMMA,
+	dsi_generic_write_seq(dsi, ST7703_CMD_SETGAMMA,
 				   0x00, 0x09, 0x0E, 0x29, 0x2D, 0x3C, 0x41, 0x37,
 				   0x07, 0x0B, 0x0D, 0x10, 0x11, 0x0F, 0x10, 0x11,
 				   0x18, 0x00, 0x09, 0x0E, 0x29, 0x2D, 0x3C, 0x41,
@@ -159,6 +168,15 @@ static const struct st7703_panel_desc jh
 	.init_sequence = jh057n_init_sequence,
 };
 
+#define dsi_dcs_write_seq(dsi, cmd, seq...) do {			\
+		static const u8 d[] = { seq };				\
+		int ret;						\
+		ret = mipi_dsi_dcs_write(dsi, cmd, d, ARRAY_SIZE(d));	\
+		if (ret < 0)						\
+			return ret;					\
+	} while (0)
+
+
 static int xbd599_init_sequence(struct st7703 *ctx)
 {
 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
@@ -168,9 +186,9 @@ static int xbd599_init_sequence(struct s
 	 */
 
 	/* Magic sequence to unlock user commands below. */
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEXTC, 0xF1, 0x12, 0x83);
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETEXTC, 0xF1, 0x12, 0x83);
 
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETMIPI,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETMIPI,
 			       0x33, /* VC_main = 0, Lane_Number = 3 (4 lanes) */
 			       0x81, /* DSI_LDO_SEL = 1.7V, RTERM = 90 Ohm */
 			       0x05, /* IHSRX = x6 (Low High Speed driving ability) */
@@ -182,14 +200,14 @@ static int xbd599_init_sequence(struct s
 			       0x44, 0x25, 0x00, 0x91, 0x0a, 0x00, 0x00, 0x02,
 			       0x4F, 0x11, 0x00, 0x00, 0x37);
 
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER_EXT,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER_EXT,
 			       0x25, /* PCCS = 2, ECP_DC_DIV = 1/4 HSYNC */
 			       0x22, /* DT = 15ms XDK_ECP = x2 */
 			       0x20, /* PFM_DC_DIV = /1 */
 			       0x03  /* ECP_SYNC_EN = 1, VGX_SYNC_EN = 1 */);
 
 	/* RGB I/F porch timing */
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETRGBIF,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETRGBIF,
 			       0x10, /* VBP_RGB_GEN */
 			       0x10, /* VFP_RGB_GEN */
 			       0x05, /* DE_BP_RGB_GEN */
@@ -200,7 +218,7 @@ static int xbd599_init_sequence(struct s
 			       0x00, 0x00);
 
 	/* Source driving settings. */
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETSCR,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETSCR,
 			       0x73, /* N_POPON */
 			       0x73, /* N_NOPON */
 			       0x50, /* I_POPON */
@@ -212,19 +230,19 @@ static int xbd599_init_sequence(struct s
 			       0x00  /* Undocumented */);
 
 	/* NVDDD_SEL = -1.8V, VDDD_SEL = out of range (possibly 1.9V?) */
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVDC, 0x4E);
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETVDC, 0x4E);
 
 	/*
 	 * SS_PANEL = 1 (reverse scan), GS_PANEL = 0 (normal scan)
 	 * REV_PANEL = 1 (normally black panel), BGR_PANEL = 1 (BGR)
 	 */
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPANEL, 0x0B);
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETPANEL, 0x0B);
 
 	/* Zig-Zag Type C column inversion. */
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETCYC, 0x80);
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETCYC, 0x80);
 
 	/* Set display resolution. */
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETDISP,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETDISP,
 			       0xF0, /* NL = 240 */
 			       0x12, /* RES_V_LSB = 0, BLK_CON = VSSD,
 				      * RESO_SEL = 720RGB
@@ -234,7 +252,7 @@ static int xbd599_init_sequence(struct s
 				      * ISC = 0 frames
 				      */);
 
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEQ,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETEQ,
 			       0x00, /* PNOEQ */
 			       0x00, /* NNOEQ */
 			       0x0B, /* PEQGND */
@@ -254,9 +272,10 @@ static int xbd599_init_sequence(struct s
 				      * ESD_DET_TIME_SEL = 0 frames
 				      */);
 
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETECO, 0x01, 0x00, 0xFF, 0xFF, 0x00);
+	/* Undocumented command. */
+	dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_C6, 0x01, 0x00, 0xFF, 0xFF, 0x00);
 
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER,
 			       0x74, /* VBTHS, VBTLS: VGH = 17V, VBL = -11V */
 			       0x00, /* FBOFF_VGH = 0, FBOFF_VGL = 0 */
 			       0x32, /* VRP  */
@@ -274,19 +293,20 @@ static int xbd599_init_sequence(struct s
 			       0x77  /* VGH3_R_DIV, VGL3_R_DIV (4.5MHz) */);
 
 	/* Reference voltage. */
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETBGP,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETBGP,
 			       0x07, /* VREF_SEL = 4.2V */
 			       0x07  /* NVREF_SEL = 4.2V */);
+	msleep(20);
 
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVCOM,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETVCOM,
 			       0x2C, /* VCOMDC_F = -0.67V */
 			       0x2C  /* VCOMDC_B = -0.67V */);
 
 	/* Undocumented command. */
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00);
+	dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00);
 
 	/* This command is to set forward GIP timing. */
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP1,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP1,
 			       0x82, 0x10, 0x06, 0x05, 0xA2, 0x0A, 0xA5, 0x12,
 			       0x31, 0x23, 0x37, 0x83, 0x04, 0xBC, 0x27, 0x38,
 			       0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0C, 0x00,
@@ -297,7 +317,7 @@ static int xbd599_init_sequence(struct s
 			       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
 
 	/* This command is to set backward GIP timing. */
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP2,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP2,
 			       0x02, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 			       0x00, 0x00, 0x00, 0x00, 0x02, 0x46, 0x02, 0x88,
 			       0x88, 0x88, 0x88, 0x88, 0x88, 0x64, 0x88, 0x13,
@@ -308,7 +328,7 @@ static int xbd599_init_sequence(struct s
 			       0xA5, 0x00, 0x00, 0x00, 0x00);
 
 	/* Adjust the gamma characteristics of the panel. */
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGAMMA,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETGAMMA,
 			       0x00, 0x09, 0x0D, 0x23, 0x27, 0x3C, 0x41, 0x35,
 			       0x07, 0x0D, 0x0E, 0x12, 0x13, 0x10, 0x12, 0x12,
 			       0x18, 0x00, 0x09, 0x0D, 0x23, 0x27, 0x3C, 0x41,
@@ -341,7 +361,15 @@ static const struct st7703_panel_desc xb
 	.init_sequence = xbd599_init_sequence,
 };
 
-static int rg353v2_init_sequence(struct st7703 *ctx)
+#define dsi_generic_write_seq(dsi, seq...) do {				\
+		static const u8 d[] = { seq };				\
+		int ret;						\
+		ret = mipi_dsi_generic_write(dsi, d, ARRAY_SIZE(d));	\
+		if (ret < 0)						\
+			return ret;					\
+	} while (0)
+
+static int rg351v2_init_sequence(struct st7703 *ctx)
 {
 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
 
@@ -349,44 +377,44 @@ static int rg353v2_init_sequence(struct
 	 * Init sequence was supplied by the panel vendor.
 	 */
 
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEXTC, 0xf1, 0x12, 0x83);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETAPID, 0x00, 0x00, 0x00,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETEXTC, 0xf1, 0x12, 0x83);
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETAPID, 0x00, 0x00, 0x00,
 			       0xda, 0x80);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETDISP, 0x00, 0x13, 0x70);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETRGBIF, 0x10, 0x10, 0x28,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETDISP, 0x00, 0x13, 0x70);
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETRGBIF, 0x10, 0x10, 0x28,
 			       0x28, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETCYC, 0x80);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETBGP, 0x0a, 0x0a);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVCOM, 0x92, 0x92);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER_EXT, 0x25, 0x22,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETCYC, 0x80);
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETBGP, 0x0a, 0x0a);
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETVCOM, 0x92, 0x92);
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER_EXT, 0x25, 0x22,
 			       0xf0, 0x63);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETMIPI, 0x33, 0x81, 0x05,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETMIPI, 0x33, 0x81, 0x05,
 			       0xf9, 0x0e, 0x0e, 0x20, 0x00, 0x00, 0x00, 0x00,
 			       0x00, 0x00, 0x00, 0x44, 0x25, 0x00, 0x90, 0x0a,
 			       0x00, 0x00, 0x01, 0x4f, 0x01, 0x00, 0x00, 0x37);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVDC, 0x47);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETSCR, 0x73, 0x73, 0x50, 0x50,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETVDC, 0x47);
+	dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00);
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETSCR, 0x73, 0x73, 0x50, 0x50,
 			       0x00, 0x00, 0x12, 0x50, 0x00);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER, 0x53, 0xc0, 0x32,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER, 0x53, 0xc0, 0x32,
 			       0x32, 0x77, 0xe1, 0xdd, 0xdd, 0x77, 0x77, 0x33,
 			       0x33);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETECO, 0x82, 0x00, 0xbf, 0xff,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETECO, 0x82, 0x00, 0xbf, 0xff,
 			       0x00, 0xff);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETIO, 0xb8, 0x00, 0x0a, 0x00,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETIO, 0xb8, 0x00, 0x0a, 0x00,
 			       0x00, 0x00);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETCABC, 0x10, 0x40, 0x1e,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETCABC, 0x10, 0x40, 0x1e,
 			       0x02);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPANEL, 0x0b);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGAMMA, 0x00, 0x07, 0x0d,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETPANEL, 0x0b);
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETGAMMA, 0x00, 0x07, 0x0d,
 			       0x37, 0x35, 0x3f, 0x41, 0x44, 0x06, 0x0c, 0x0d,
 			       0x0f, 0x11, 0x10, 0x12, 0x14, 0x1a, 0x00, 0x07,
 			       0x0d, 0x37, 0x35, 0x3f, 0x41, 0x44, 0x06, 0x0c,
 			       0x0d, 0x0f, 0x11, 0x10, 0x12, 0x14, 0x1a);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEQ, 0x07, 0x07, 0x0b, 0x0b,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETEQ, 0x07, 0x07, 0x0b, 0x0b,
 			       0x0b, 0x0b, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00,
 			       0xc0, 0x10);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP1, 0xc8, 0x10, 0x02, 0x00,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP1, 0xc8, 0x10, 0x02, 0x00,
 			       0x00, 0xb0, 0xb1, 0x11, 0x31, 0x23, 0x28, 0x80,
 			       0xb0, 0xb1, 0x27, 0x08, 0x00, 0x04, 0x02, 0x00,
 			       0x00, 0x00, 0x00, 0x04, 0x02, 0x00, 0x00, 0x00,
@@ -395,7 +423,7 @@ static int rg353v2_init_sequence(struct
 			       0x18, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x00,
 			       0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 			       0x00, 0x00, 0x00);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP2, 0x97, 0x0a, 0x82, 0x02,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP2, 0x97, 0x0a, 0x82, 0x02,
 			       0x03, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 			       0x81, 0x88, 0xba, 0x17, 0x53, 0x88, 0x88, 0x88,
 			       0x88, 0x88, 0x88, 0x80, 0x88, 0xba, 0x06, 0x42,
@@ -404,12 +432,12 @@ static int rg353v2_init_sequence(struct
 			       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 			       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 			       0x00);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_EF, 0xff, 0xff, 0x01);
+	dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_EF, 0xff, 0xff, 0x01);
 
 	return 0;
 }
 
-static const struct drm_display_mode rg353v2_mode = {
+static const struct drm_display_mode rg351v2_mode = {
 	.hdisplay	= 640,
 	.hsync_start	= 640 + 40,
 	.hsync_end	= 640 + 40 + 2,
@@ -424,15 +452,23 @@ static const struct drm_display_mode rg3
 	.height_mm	= 57,
 };
 
-static const struct st7703_panel_desc rg353v2_desc = {
-	.mode = &rg353v2_mode,
+static const struct st7703_panel_desc rg351v2_desc = {
+	.mode = &rg351v2_mode,
 	.lanes = 4,
 	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
 		      MIPI_DSI_MODE_NO_EOT_PACKET | MIPI_DSI_MODE_LPM,
 	.format = MIPI_DSI_FMT_RGB888,
-	.init_sequence = rg353v2_init_sequence,
+	.init_sequence = rg351v2_init_sequence,
 };
 
+#define dsi_generic_write_seq(dsi, seq...) do {				\
+		static const u8 d[] = { seq };				\
+		int ret;						\
+		ret = mipi_dsi_generic_write(dsi, d, ARRAY_SIZE(d));	\
+		if (ret < 0)						\
+			return ret;					\
+	} while (0)
+
 static int rgb30panel_init_sequence(struct st7703 *ctx)
 {
 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
@@ -446,31 +482,31 @@ static int rgb30panel_init_sequence(stru
 	mipi_dsi_dcs_exit_sleep_mode(dsi);
 	msleep(250);
 
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEXTC, 0xf1, 0x12, 0x83);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETMIPI, 0x33, 0x81, 0x05, 0xf9,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETEXTC, 0xf1, 0x12, 0x83);
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETMIPI, 0x33, 0x81, 0x05, 0xf9,
 			       0x0e, 0x0e, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
 			       0x00, 0x00, 0x44, 0x25, 0x00, 0x90, 0x0a, 0x00,
 			       0x00, 0x01, 0x4f, 0x01, 0x00, 0x00, 0x37);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER_EXT, 0x25, 0x22, 0xf0,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER_EXT, 0x25, 0x22, 0xf0,
 			       0x63);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETRGBIF, 0x10, 0x10, 0x28,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00);
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETRGBIF, 0x10, 0x10, 0x28,
 			       0x28, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETSCR, 0x73, 0x73, 0x50, 0x50,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETSCR, 0x73, 0x73, 0x50, 0x50,
 			       0x00, 0x00, 0x12, 0x70, 0x00);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVDC, 0x46);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPANEL, 0x0b);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETCYC, 0x80);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETDISP, 0x3c, 0x12, 0x30);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEQ, 0x07, 0x07, 0x0b, 0x0b,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETVDC, 0x46);
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETPANEL, 0x0b);
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETCYC, 0x80);
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETDISP, 0x3c, 0x12, 0x30);
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETEQ, 0x07, 0x07, 0x0b, 0x0b,
 			       0x03, 0x0b, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00,
 			       0xc0, 0x10);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER, 0x36, 0x00, 0x32,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER, 0x36, 0x00, 0x32,
 			       0x32, 0x77, 0xf1, 0xcc, 0xcc, 0x77, 0x77, 0x33,
 			       0x33);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETBGP, 0x0a, 0x0a);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVCOM, 0x88, 0x88);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP1, 0xc8, 0x10, 0x0a, 0x10,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETBGP, 0x0a, 0x0a);
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETVCOM, 0x88, 0x88);
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP1, 0xc8, 0x10, 0x0a, 0x10,
 			       0x0f, 0xa1, 0x80, 0x12, 0x31, 0x23, 0x47, 0x86,
 			       0xa1, 0x80, 0x47, 0x08, 0x00, 0x00, 0x0d, 0x00,
 			       0x00, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00,
@@ -479,7 +515,7 @@ static int rgb30panel_init_sequence(stru
 			       0x13, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x00,
 			       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 			       0x00, 0x00, 0x00);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP2, 0x96, 0x12, 0x01, 0x01,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP2, 0x96, 0x12, 0x01, 0x01,
 			       0x01, 0x78, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
 			       0x4f, 0x31, 0x8b, 0xa8, 0x31, 0x75, 0x88, 0x88,
 			       0x88, 0x88, 0x88, 0x4f, 0x20, 0x8b, 0xa8, 0x20,
@@ -488,7 +524,7 @@ static int rgb30panel_init_sequence(stru
 			       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 			       0x00, 0x00, 0x40, 0xa1, 0x80, 0x00, 0x00, 0x00,
 			       0x00);
-	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGAMMA, 0x00, 0x0a, 0x0f,
+	dsi_dcs_write_seq(dsi, ST7703_CMD_SETGAMMA, 0x00, 0x0a, 0x0f,
 			       0x29, 0x3b, 0x3f, 0x42, 0x39, 0x06, 0x0d, 0x10,
 			       0x13, 0x15, 0x14, 0x15, 0x10, 0x17, 0x00, 0x0a,
 			       0x0f, 0x29, 0x3b, 0x3f, 0x42, 0x39, 0x06, 0x0d,
@@ -667,7 +703,7 @@ static int allpixelson_set(void *data, u
 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
 
 	dev_dbg(ctx->dev, "Setting all pixels on\n");
-	mipi_dsi_generic_write_seq(dsi, ST7703_CMD_ALL_PIXEL_ON);
+	dsi_generic_write_seq(dsi, ST7703_CMD_ALL_PIXEL_ON);
 	msleep(val * 1000);
 	/* Reset the panel to get video back */
 	drm_panel_disable(&ctx->panel);
@@ -783,7 +819,7 @@ static void st7703_remove(struct mipi_ds
 }
 
 static const struct of_device_id st7703_of_match[] = {
-	{ .compatible = "anbernic,rg353v-panel-v2", .data = &rg353v2_desc },
+	{ .compatible = "anbernic,rg351v-panel-v2", .data = &rg351v2_desc },
 	{ .compatible = "powkiddy,rgb30-panel", .data = &rgb30panel_desc },
 	{ .compatible = "rocktech,jh057n00900", .data = &jh057n00900_panel_desc },
 	{ .compatible = "xingbangda,xbd599", .data = &xbd599_desc },
@@ -802,6 +838,6 @@ static struct mipi_dsi_driver st7703_dri
 };
 module_mipi_dsi_driver(st7703_driver);
 
-MODULE_AUTHOR("Guido Günther <agx@sigxcpu.org>");
+MODULE_AUTHOR("Guido Gأ¼nther <agx@sigxcpu.org>");
 MODULE_DESCRIPTION("DRM driver for Sitronix ST7703 based MIPI DSI panels");
 MODULE_LICENSE("GPL v2");