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distribution/projects/Rockchip/packages/linux/patches/RK3399/007-rk3399-vpu.patch
brooksytech 0a04dc78ac
RK3399: VPU driver, thanks @LibreElec
2024-01-04 13:52:40 +00:00

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diff -rupN linux.orig/Documentation/devicetree/bindings/media/rockchip,vdec.yaml linux/Documentation/devicetree/bindings/media/rockchip,vdec.yaml
--- linux.orig/Documentation/devicetree/bindings/media/rockchip,vdec.yaml 2024-01-03 20:53:28.383294161 +0000
+++ linux/Documentation/devicetree/bindings/media/rockchip,vdec.yaml 2024-01-03 21:26:02.707011192 +0000
@@ -53,6 +53,18 @@ properties:
iommus:
maxItems: 1
+ resets:
+ maxItems: 6
+
+ reset-names:
+ items:
+ - const: video_h
+ - const: video_a
+ - const: video_core
+ - const: video_cabac
+ - const: niu_a
+ - const: niu_h
+
required:
- compatible
- reg
@@ -60,6 +72,8 @@ required:
- clocks
- clock-names
- power-domains
+ - resets
+ - reset-names
additionalProperties: false
@@ -78,6 +92,11 @@ examples:
clock-names = "axi", "ahb", "cabac", "core";
power-domains = <&power RK3399_PD_VDU>;
iommus = <&vdec_mmu>;
+ resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>,
+ <&cru SRST_VDU_CORE>, <&cru SRST_VDU_CA>,
+ <&cru SRST_A_VDU_NOC>, <&cru SRST_H_VDU_NOC>;
+ reset-names = "video_h", "video_a", "video_core", "video_cabac",
+ "niu_a", "niu_h";
};
...
diff -rupN linux.orig/Documentation/devicetree/bindings/media/rockchip-iep.yaml linux/Documentation/devicetree/bindings/media/rockchip-iep.yaml
--- linux.orig/Documentation/devicetree/bindings/media/rockchip-iep.yaml 1970-01-01 00:00:00.000000000 +0000
+++ linux/Documentation/devicetree/bindings/media/rockchip-iep.yaml 2024-01-03 21:28:43.674043912 +0000
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/rockchip-iep.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip Image Enhancement Processor (IEP)
+
+description:
+ Rockchip IEP supports various image enhancement operations for YUV and RGB domains.
+ Deinterlacing, spatial and temporal sampling noise reduction are supported by the
+ YUV block. Gamma adjustment, edge enhancement, detail enhancement are supported in
+ the RGB block. Brightness, Saturation, Contrast, Hue adjustment is supported for
+ both domains. Furthermore it supports converting RGB to YUV / YUV to RGB.
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+ compatible:
+ oneOf:
+ - const: rockchip,rk3228-iep
+ - items:
+ - enum:
+ - rockchip,rk3288-iep
+ - rockchip,rk3328-iep
+ - rockchip,rk3368-iep
+ - rockchip,rk3399-iep
+ - const: rockchip,rk3228-iep
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: axi
+ - const: ahb
+
+ power-domains:
+ maxItems: 1
+
+ iommus:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rk3228-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/rk3228-power.h>
+ iep: iep@20070000 {
+ compatible = "rockchip,rk3228-iep";
+ reg = <0x20070000 0x800>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ clock-names = "axi", "ahb";
+ iommus = <&iep_mmu>;
+ power-domains = <&power RK3228_PD_VIO>;
+ };
diff -rupN linux.orig/arch/arm/boot/dts/rk3288-miqi.dts linux/arch/arm/boot/dts/rk3288-miqi.dts
--- linux.orig/arch/arm/boot/dts/rk3288-miqi.dts 2024-01-03 20:53:28.931301546 +0000
+++ linux/arch/arm/boot/dts/rk3288-miqi.dts 2024-01-03 21:27:13.822235237 +0000
@@ -78,6 +78,21 @@
regulator-always-on;
regulator-boot-on;
};
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "HDMI";
+ simple-audio-card,mclk-fs = <512>;
+
+ simple-audio-card,codec {
+ sound-dai = <&hdmi>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s>;
+ };
+ };
};
&cpu0 {
@@ -130,6 +145,8 @@
&hdmi {
ddc-i2c-bus = <&i2c5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_cec_c0>;
status = "okay";
};
@@ -283,6 +300,11 @@
status = "okay";
};
+&i2s {
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
+
&io_domains {
status = "okay";
diff -rupN linux.orig/arch/arm/boot/dts/rk3288-tinker.dtsi linux/arch/arm/boot/dts/rk3288-tinker.dtsi
--- linux.orig/arch/arm/boot/dts/rk3288-tinker.dtsi 2024-01-03 20:53:28.931301546 +0000
+++ linux/arch/arm/boot/dts/rk3288-tinker.dtsi 2024-01-03 21:27:13.822235237 +0000
@@ -73,7 +73,7 @@
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
- simple-audio-card,name = "rockchip,tinker-codec";
+ simple-audio-card,name = "HDMI";
simple-audio-card,mclk-fs = <512>;
simple-audio-card,codec {
diff -rupN linux.orig/arch/arm/boot/dts/rk3288.dtsi linux/arch/arm/boot/dts/rk3288.dtsi
--- linux.orig/arch/arm/boot/dts/rk3288.dtsi 2024-01-03 20:53:28.935301600 +0000
+++ linux/arch/arm/boot/dts/rk3288.dtsi 2024-01-03 21:28:43.674043912 +0000
@@ -984,14 +984,25 @@
reset-names = "crypto-rst";
};
+ iep: iep@ff90000 {
+ compatible = "rockchip,rk3288-iep", "rockchip,rk3228-iep";
+ reg = <0x0 0xff900000 0x0 0x800>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "iep";
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ clock-names = "axi", "ahb";
+ power-domains = <&power RK3288_PD_VIO>;
+ iommus = <&iep_mmu>;
+ };
+
iep_mmu: iommu@ff900800 {
compatible = "rockchip,iommu";
reg = <0x0 0xff900800 0x0 0x40>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
+ power-domains = <&power RK3288_PD_VIO>;
#iommu-cells = <0>;
- status = "disabled";
};
isp_mmu: iommu@ff914000 {
@@ -1017,7 +1028,7 @@
};
vopb: vop@ff930000 {
- compatible = "rockchip,rk3288-vop";
+ compatible = "rockchip,rk3288-vop-big";
reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
@@ -1026,6 +1037,8 @@
resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
reset-names = "axi", "ahb", "dclk";
iommus = <&vopb_mmu>;
+ assigned-clocks = <&cru DCLK_VOP0>;
+ assigned-clock-parents = <&cru PLL_NPLL>;
status = "disabled";
vopb_out: port {
@@ -1066,7 +1079,7 @@
};
vopl: vop@ff940000 {
- compatible = "rockchip,rk3288-vop";
+ compatible = "rockchip,rk3288-vop-lit";
reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
@@ -1081,11 +1094,6 @@
#address-cells = <1>;
#size-cells = <0>;
- vopl_out_hdmi: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&hdmi_in_vopl>;
- };
-
vopl_out_edp: endpoint@1 {
reg = <1>;
remote-endpoint = <&edp_in_vopl>;
@@ -1226,10 +1234,6 @@
reg = <0>;
remote-endpoint = <&vopb_out_hdmi>;
};
- hdmi_in_vopl: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vopl_out_hdmi>;
- };
};
};
};
@@ -1256,6 +1260,25 @@
power-domains = <&power RK3288_PD_VIDEO>;
};
+ hevc: hevc@ff9c0000 {
+ compatible = "rockchip,rk3288-hevc";
+ reg = <0x0 0xff9c0000 0x0 0x400>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_dec";
+ clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, <&cru SCLK_HEVC_CABAC>,
+ <&cru SCLK_HEVC_CORE>;
+ clock-names = "axi", "ahb", "cabac", "core";
+ assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
+ <&cru SCLK_HEVC_CORE>,
+ <&cru SCLK_HEVC_CABAC>;
+ assigned-clock-rates = <400000000>, <100000000>,
+ <300000000>, <300000000>;
+ iommus = <&hevc_mmu>;
+ power-domains = <&power RK3288_PD_HEVC>;
+ resets = <&cru SRST_HEVC>;
+ reset-names = "video_core";
+ };
+
hevc_mmu: iommu@ff9c0440 {
compatible = "rockchip,iommu";
reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
@@ -1263,7 +1286,7 @@
clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
- status = "disabled";
+ power-domains = <&power RK3288_PD_HEVC>;
};
gpu: gpu@ffa30000 {
diff -rupN linux.orig/arch/arm64/boot/dts/rockchip/rk3328-a1.dts linux/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
--- linux.orig/arch/arm64/boot/dts/rockchip/rk3328-a1.dts 2024-01-03 20:53:29.227305541 +0000
+++ linux/arch/arm64/boot/dts/rockchip/rk3328-a1.dts 2024-01-03 21:27:13.822235237 +0000
@@ -57,6 +57,24 @@
gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
linux,rc-map-name = "rc-beelink-gs1";
};
+
+ spdif_sound: spdif-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "SPDIF";
+
+ simple-audio-card,cpu {
+ sound-dai = <&spdif>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&spdif_dit>;
+ };
+ };
+
+ spdif_dit: spdif-dit {
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+ };
};
&analog_sound {
@@ -129,6 +147,14 @@
};
};
+&gmac2phy {
+ clock_in_out = "output";
+ assigned-clock-rate = <50000000>;
+ assigned-clocks = <&cru SCLK_MAC2PHY>;
+ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
+ status = "okay";
+};
+
&gpu {
mali-supply = <&vdd_logic>;
};
@@ -325,6 +351,11 @@
status = "okay";
};
+&spdif {
+ pinctrl-0 = <&spdifm0_tx>;
+ status = "okay";
+};
+
&tsadc {
rockchip,hw-tshut-mode = <0>;
rockchip,hw-tshut-polarity = <0>;
@@ -358,6 +389,11 @@
status = "okay";
};
+&usbdrd3 {
+ dr_mode = "host";
+ status = "okay";
+};
+
&vop {
status = "okay";
};
diff -rupN linux.orig/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts linux/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
--- linux.orig/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts 2024-01-03 20:53:29.227305541 +0000
+++ linux/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts 2024-01-03 21:27:13.822235237 +0000
@@ -88,6 +88,13 @@
regulator-boot-on;
};
+ ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&ir_int>;
+ pinctrl-names = "default";
+ };
+
leds {
compatible = "gpio-leds";
@@ -164,6 +171,10 @@
status = "okay";
};
+&gpu {
+ mali-supply = <&vdd_logic>;
+};
+
&hdmi {
status = "okay";
};
@@ -306,6 +317,13 @@
};
&pinctrl {
+
+ ir {
+ ir_int: ir-int {
+ rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
diff -rupN linux.orig/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts linux/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
--- linux.orig/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts 2024-01-03 20:53:29.227305541 +0000
+++ linux/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts 2024-01-03 21:27:13.822235237 +0000
@@ -162,6 +162,10 @@
status = "okay";
};
+&gpu {
+ mali-supply = <&vdd_logic>;
+};
+
&hdmi {
status = "okay";
};
diff -rupN linux.orig/arch/arm64/boot/dts/rockchip/rk3328.dtsi linux/arch/arm64/boot/dts/rockchip/rk3328.dtsi
--- linux.orig/arch/arm64/boot/dts/rockchip/rk3328.dtsi 2024-01-03 20:53:29.227305541 +0000
+++ linux/arch/arm64/boot/dts/rockchip/rk3328.dtsi 2024-01-03 21:32:47.747235430 +0000
@@ -300,6 +300,11 @@
#address-cells = <1>;
#size-cells = <0>;
+ power-domain@RK3328_PD_GPU {
+ reg = <RK3328_PD_GPU>;
+ clocks = <&cru ACLK_GPU>;
+ #power-domain-cells = <0>;
+ };
power-domain@RK3328_PD_HEVC {
reg = <RK3328_PD_HEVC>;
#power-domain-cells = <0>;
@@ -539,6 +544,11 @@
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <4096>;
};
+ map1 {
+ trip = <&target>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ contribution = <4096>;
+ };
};
};
@@ -620,7 +630,32 @@
"ppmmu1";
clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
clock-names = "bus", "core";
+ operating-points-v2 = <&gpu_opp_table>;
+ power-domains = <&power RK3328_PD_GPU>;
resets = <&cru SRST_GPU_A>;
+ #cooling-cells = <2>;
+ };
+
+ gpu_opp_table: gpu-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <1075000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <1075000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1075000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1150000>;
+ status = "disabled";
+ };
};
h265e_mmu: iommu@ff330200 {
@@ -674,6 +709,11 @@
assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>,
<&cru SCLK_VDEC_CORE>;
assigned-clock-rates = <400000000>, <400000000>, <300000000>;
+ resets = <&cru SRST_VDEC_H>, <&cru SRST_VDEC_A>,
+ <&cru SRST_VDEC_CORE>, <&cru SRST_VDEC_CABAC>,
+ <&cru SRST_VDEC_NIU_A>, <&cru SRST_VDEC_NIU_H>;
+ reset-names = "video_h", "video_a", "video_core", "video_cabac",
+ "niu_a", "niu_h";
iommus = <&vdec_mmu>;
power-domains = <&power RK3328_PD_VIDEO>;
};
@@ -720,6 +760,28 @@
status = "disabled";
};
+ iep: iep@ff3a0000 {
+ compatible = "rockchip,rk3328-iep", "rockchip,rk3228-iep";
+ reg = <0x0 0xff3a0000 0x0 0x800>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "iep";
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ clock-names = "axi", "ahb";
+ power-domains = <&power RK3328_PD_VIDEO>;
+ iommus = <&iep_mmu>;
+ };
+
+ iep_mmu: iommu@ff3a0800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff3a0800 0x0 0x40>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "iep_mmu";
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3328_PD_VIDEO>;
+ #iommu-cells = <0>;
+ };
+
hdmi: hdmi@ff3c0000 {
compatible = "rockchip,rk3328-dw-hdmi";
reg = <0x0 0xff3c0000 0x0 0x20000>;
@@ -811,8 +873,8 @@
<0>, <24000000>,
<24000000>, <24000000>,
<15000000>, <15000000>,
- <100000000>, <100000000>,
- <100000000>, <100000000>,
+ <300000000>, <100000000>,
+ <400000000>, <100000000>,
<50000000>, <100000000>,
<100000000>, <100000000>,
<50000000>, <50000000>,
@@ -871,6 +933,8 @@
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <150000000>;
+ resets = <&cru SRST_MMC0>;
+ reset-names = "reset";
status = "disabled";
};
@@ -883,6 +947,8 @@
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <150000000>;
+ resets = <&cru SRST_SDIO>;
+ reset-names = "reset";
status = "disabled";
};
@@ -895,6 +961,8 @@
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <150000000>;
+ resets = <&cru SRST_EMMC>;
+ reset-names = "reset";
status = "disabled";
};
@@ -993,6 +1061,20 @@
status = "disabled";
};
+ sdmmc_ext: mmc@ff5f0000 {
+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff5f0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>,
+ <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <150000000>;
+ resets = <&cru SRST_SDMMCEXT>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
usbdrd3: usb@ff600000 {
compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
reg = <0x0 0xff600000 0x0 0x100000>;
diff -rupN linux.orig/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi linux/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
--- linux.orig/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi 2024-01-03 20:53:29.231305593 +0000
+++ linux/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi 2024-01-03 21:27:13.822235237 +0000
@@ -215,7 +215,7 @@
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
- regulator-min-microvolt = <450000>;
+ regulator-min-microvolt = <430000>;
regulator-max-microvolt = <1400000>;
pwm-supply = <&vcc3v3_sys>;
};
@@ -536,7 +536,7 @@
pinctrl-names = "default";
pinctrl-0 = <&fusb1_int>;
vbus-supply = <&vcc_vbus_typec1>;
- status = "okay";
+ status = "disabled";
};
};
@@ -553,7 +553,7 @@
pinctrl-names = "default";
pinctrl-0 = <&fusb0_int>;
vbus-supply = <&vcc_vbus_typec0>;
- status = "okay";
+ status = "disabled";
};
mp8859: regulator@66 {
diff -rupN linux.orig/arch/arm64/boot/dts/rockchip/rk3399.dtsi linux/arch/arm64/boot/dts/rockchip/rk3399.dtsi
--- linux.orig/arch/arm64/boot/dts/rockchip/rk3399.dtsi 2024-01-03 20:53:29.231305593 +0000
+++ linux/arch/arm64/boot/dts/rockchip/rk3399.dtsi 2024-01-03 21:28:43.674043912 +0000
@@ -1347,6 +1347,11 @@
clock-names = "axi", "ahb", "cabac", "core";
iommus = <&vdec_mmu>;
power-domains = <&power RK3399_PD_VDU>;
+ resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>,
+ <&cru SRST_VDU_CORE>, <&cru SRST_VDU_CA>,
+ <&cru SRST_A_VDU_NOC>, <&cru SRST_H_VDU_NOC>;
+ reset-names = "video_h", "video_a", "video_core", "video_cabac",
+ "niu_a", "niu_h";
};
vdec_mmu: iommu@ff660480 {
@@ -1359,14 +1364,25 @@
#iommu-cells = <0>;
};
+ iep: iep@ff670000 {
+ compatible = "rockchip,rk3399-iep", "rockchip,rk3228-iep";
+ reg = <0x0 0xff670000 0x0 0x800>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "iep";
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ clock-names = "axi", "ahb";
+ power-domains = <&power RK3399_PD_IEP>;
+ iommus = <&iep_mmu>;
+ };
+
iep_mmu: iommu@ff670800 {
compatible = "rockchip,iommu";
reg = <0x0 0xff670800 0x0 0x40>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
+ power-domains = <&power RK3399_PD_IEP>;
#iommu-cells = <0>;
- status = "disabled";
};
rga: rga@ff680000 {
@@ -1471,7 +1487,7 @@
<1000000000>,
<150000000>, <75000000>,
<37500000>,
- <100000000>, <100000000>,
+ <300000000>, <100000000>,
<50000000>, <600000000>,
<100000000>, <50000000>,
<400000000>, <400000000>,
@@ -1730,11 +1746,6 @@
remote-endpoint = <&edp_in_vopl>;
};
- vopl_out_hdmi: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&hdmi_in_vopl>;
- };
-
vopl_out_mipi1: endpoint@3 {
reg = <3>;
remote-endpoint = <&mipi1_in_vopl>;
@@ -1892,7 +1903,7 @@
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
- simple-audio-card,name = "hdmi-sound";
+ simple-audio-card,name = "HDMI";
status = "disabled";
simple-audio-card,cpu {
@@ -1928,10 +1939,6 @@
reg = <0>;
remote-endpoint = <&vopb_out_hdmi>;
};
- hdmi_in_vopl: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vopl_out_hdmi>;
- };
};
};
};
diff -rupN linux.orig/drivers/clk/rockchip/clk-rk3228.c linux/drivers/clk/rockchip/clk-rk3228.c
--- linux.orig/drivers/clk/rockchip/clk-rk3228.c 2024-01-03 20:53:29.851313959 +0000
+++ linux/drivers/clk/rockchip/clk-rk3228.c 2024-01-03 21:17:09.402615966 +0000
@@ -409,7 +409,7 @@ static struct rockchip_clk_branch rk3228
RK2928_CLKSEL_CON(29), 0, 3, DFLAGS),
DIV(0, "sclk_vop_pre", "sclk_vop_src", 0,
RK2928_CLKSEL_CON(27), 8, 8, DFLAGS),
- MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, 0,
+ MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK2928_CLKSEL_CON(27), 1, 1, MFLAGS),
FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
diff -rupN linux.orig/drivers/clk/rockchip/clk-rk3288.c linux/drivers/clk/rockchip/clk-rk3288.c
--- linux.orig/drivers/clk/rockchip/clk-rk3288.c 2024-01-03 20:53:29.851313959 +0000
+++ linux/drivers/clk/rockchip/clk-rk3288.c 2024-01-03 21:17:09.402615966 +0000
@@ -121,6 +121,43 @@ static struct rockchip_pll_rate_table rk
{ /* sentinel */ },
};
+static struct rockchip_pll_rate_table rk3288_npll_rates[] = {
+ RK3066_PLL_RATE_NB(594000000, 1, 198, 8, 1),
+ RK3066_PLL_RATE_NB(585000000, 6, 585, 4, 32),
+ RK3066_PLL_RATE_NB(432000000, 3, 216, 4, 32),
+ RK3066_PLL_RATE_NB(426000000, 3, 213, 4, 32),
+ RK3066_PLL_RATE_NB(400000000, 1, 100, 6, 32),
+ RK3066_PLL_RATE(348500000, 8, 697, 6),
+ RK3066_PLL_RATE_NB(342000000, 3, 171, 4, 32),
+ RK3066_PLL_RATE_NB(297000000, 2, 198, 8, 16),
+ RK3066_PLL_RATE_NB(270000000, 1, 135, 12, 32),
+ RK3066_PLL_RATE_NB(260000000, 1, 130, 12, 32),
+ RK3066_PLL_RATE(241500000, 2, 161, 8),
+ RK3066_PLL_RATE(162000000, 1, 81, 12),
+ RK3066_PLL_RATE(154000000, 6, 539, 14),
+ RK3066_PLL_RATE_NB(148500000, 1, 99, 16, 32),
+ RK3066_PLL_RATE(148352000, 13, 1125, 14),
+ RK3066_PLL_RATE_NB(146250000, 6, 585, 16, 32),
+ RK3066_PLL_RATE(121750000, 6, 487, 16),
+ RK3066_PLL_RATE(119000000, 3, 238, 16),
+ RK3066_PLL_RATE_NB(108000000, 1, 54, 12, 32),
+ RK3066_PLL_RATE_NB(106500000, 4, 213, 12, 32),
+ RK3066_PLL_RATE(101000000, 3, 202, 16),
+ RK3066_PLL_RATE(88750000, 6, 355, 16),
+ RK3066_PLL_RATE_NB(85500000, 4, 171, 12, 32),
+ RK3066_PLL_RATE(83500000, 3, 167, 16),
+ RK3066_PLL_RATE(79500000, 1, 53, 16),
+ RK3066_PLL_RATE_NB(74250000, 4, 198, 16, 32),
+ RK3066_PLL_RATE(74176000, 26, 1125, 14),
+ RK3066_PLL_RATE(72000000, 1, 48, 16),
+ RK3066_PLL_RATE(71000000, 3, 142, 16),
+ RK3066_PLL_RATE(68250000, 2, 91, 16),
+ RK3066_PLL_RATE(65000000, 3, 130, 16),
+ RK3066_PLL_RATE(40000000, 3, 80, 16),
+ RK3066_PLL_RATE(33750000, 2, 45, 16),
+ { /* sentinel */ },
+};
+
#define RK3288_DIV_ACLK_CORE_M0_MASK 0xf
#define RK3288_DIV_ACLK_CORE_M0_SHIFT 0
#define RK3288_DIV_ACLK_CORE_MP_MASK 0xf
@@ -195,8 +232,9 @@ PNAME(mux_ddrphy_p) = { "dpll_ddr", "gp
PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu" };
PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
-PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
-PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
+PNAME(mux_pll_src_npll_cpll_gpll_p) = { "prevent:npll", "cpll", "gpll" };
+PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "prevent:npll" };
+PNAME(vop0_mux_pll_src_cpll_gpll_npll_p) = { "prevent:cpll", "prevent:gpll", "npll" };
PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "unstable:usbphy480m_src" };
PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "unstable:usbphy480m_src", "npll" };
@@ -232,7 +270,7 @@ static struct rockchip_pll_clock rk3288_
[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
[npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),
- RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
+ RK3288_MODE_CON, 14, 9, 0, rk3288_npll_rates),
};
static struct clk_div_table div_hclk_cpu_t[] = {
@@ -442,7 +480,7 @@ static struct rockchip_clk_branch rk3288
RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 4, GFLAGS),
- COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,
+ COMPOSITE(DCLK_VOP0, "dclk_vop0", vop0_mux_pll_src_cpll_gpll_npll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
RK3288_CLKGATE_CON(3), 1, GFLAGS),
COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,
diff -rupN linux.orig/drivers/clk/rockchip/clk-rk3399.c linux/drivers/clk/rockchip/clk-rk3399.c
--- linux.orig/drivers/clk/rockchip/clk-rk3399.c 2024-01-03 20:53:29.851313959 +0000
+++ linux/drivers/clk/rockchip/clk-rk3399.c 2024-01-03 21:17:09.402615966 +0000
@@ -105,6 +105,39 @@ static struct rockchip_pll_rate_table rk
{ /* sentinel */ },
};
+static struct rockchip_pll_rate_table rk3399_vpll_rates[] = {
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+ RK3036_PLL_RATE( 594000000, 1, 74, 3, 1, 0, 4194304), /* vco = 1782000000 fout = 594000000 */
+ RK3036_PLL_RATE( 593406592, 1, 74, 3, 1, 0, 2949838), /* vco = 1780219777 fout = 593406592.36908 */
+ RK3036_PLL_RATE( 319750000, 1, 79, 6, 1, 0, 15728640), /* vco = 1918500000 fout = 319750000 */
+ RK3036_PLL_RATE( 297000000, 1, 74, 6, 1, 0, 4194304), /* vco = 1782000000 fout = 297000000 */
+ RK3036_PLL_RATE( 296703296, 1, 74, 6, 1, 0, 2949838), /* vco = 1780219777 fout = 296703296.18454 */
+ RK3036_PLL_RATE( 241500000, 1, 60, 6, 1, 0, 6291456), /* vco = 1449000000 fout = 241500000 */
+ RK3036_PLL_RATE( 162000000, 1, 67, 5, 2, 0, 8388608), /* vco = 1620000000 fout = 162000000 */
+ RK3036_PLL_RATE( 148500000, 1, 74, 6, 2, 0, 4194304), /* vco = 1782000000 fout = 148500000*/
+ RK3036_PLL_RATE( 148351648, 1, 74, 6, 2, 0, 2949838), /* vco = 1780219777 fout = 148351648.09227 */
+ RK3036_PLL_RATE( 136750000, 1, 68, 2, 6, 0, 6291456), /* vco = 1641000000 fout = 136750000 */
+ RK3036_PLL_RATE( 135000000, 1, 56, 5, 2, 0, 4194304), /* vco = 1350000000 fout = 135000000 */
+ RK3036_PLL_RATE( 119000000, 1, 59, 6, 2, 0, 8388608), /* vco = 1428000000 fout = 119000000 */
+ RK3036_PLL_RATE( 108000000, 1, 63, 7, 2, 1, 0), /* vco = 1512000000 fout = 108000000 */
+ RK3036_PLL_RATE( 106500000, 1, 62, 7, 2, 0, 2097152), /* vco = 1491000000 fout = 106500000 */
+ RK3036_PLL_RATE( 88750000, 1, 55, 5, 3, 0, 7864320), /* vco = 1331250000 fout = 88750000 */
+ RK3036_PLL_RATE( 85500000, 1, 57, 4, 4, 1, 0), /* vco = 1368000000 fout = 85500000 */
+ RK3036_PLL_RATE( 78750000, 1, 59, 6, 3, 0, 1048576), /* vco = 1417500000 fout = 78750000 */
+ RK3036_PLL_RATE( 74250000, 1, 74, 6, 4, 0, 4194304), /* vco = 1782000000 fout = 74250000 */
+ RK3036_PLL_RATE( 74175824, 1, 74, 6, 4, 0, 2949838), /* vco = 1780219777 fout = 74175824.046135 */
+ RK3036_PLL_RATE( 71000000, 1, 71, 6, 4, 1, 0), /* vco = 1704000000 fout = 71000000 */
+ RK3036_PLL_RATE( 65000000, 1, 65, 6, 4, 0, 0), /* vco = 1560000000 fout = 65000000 */
+ RK3036_PLL_RATE( 59340659, 1, 59, 6, 4, 0, 5715310), /* vco = 1424175816 fout = 59340659.022331 */
+ RK3036_PLL_RATE( 54000000, 1, 63, 7, 4, 1, 0), /* vco = 1512000000 fout = 54000000 */
+ RK3036_PLL_RATE( 49500000, 1, 72, 5, 7, 0, 3145728), /* vco = 1732500000 fout = 49500000 */
+ RK3036_PLL_RATE( 40000000, 1, 70, 7, 6, 1, 0), /* vco = 1680000000 fout = 40000000 */
+ RK3036_PLL_RATE( 31500000, 1, 55, 7, 6, 0, 2097152), /* vco = 1323000000 fout = 31500000 */
+ RK3036_PLL_RATE( 27000000, 1, 55, 7, 7, 0, 2097152), /* vco = 1323000000 fout = 27000000 */
+ RK3036_PLL_RATE( 26973026, 1, 55, 7, 7, 0, 1173214), /* vco = 1321678296 fout = 26973026.450799 */
+ { /* sentinel */ },
+};
+
/* CRU parents */
PNAME(mux_pll_p) = { "xin24m", "xin32k" };
@@ -123,7 +156,7 @@ PNAME(mux_ddrclk_p) = { "clk_ddrc_lpl
PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src",
"gpll_aclk_cci_src",
"npll_aclk_cci_src",
- "vpll_aclk_cci_src" };
+ "prevent:vpll" };
PNAME(mux_cci_trace_p) = { "cpll_cci_trace",
"gpll_cci_trace" };
PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs",
@@ -149,10 +182,12 @@ PNAME(mux_pll_src_cpll_gpll_npll_upll_24
PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll",
"ppll", "upll", "xin24m" };
-PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" };
-PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll", "cpll", "gpll",
+PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "prevent:vpll", "cpll", "gpll" };
+PNAME(vop0_mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "prevent:cpll", "prevent:gpll" };
+
+PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "prevent:vpll", "cpll", "gpll",
"npll" };
-PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "vpll", "cpll", "gpll",
+PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "prevent:vpll", "cpll", "gpll",
"xin24m" };
PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div",
@@ -229,7 +264,7 @@ static struct rockchip_pll_clock rk3399_
[npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40),
RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
[vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48),
- RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
+ RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_vpll_rates),
};
static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
@@ -279,7 +314,7 @@ static struct rockchip_clk_branch rk3399
RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata =
- MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT,
+ MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3399_CLKSEL_CON(49), 11, 1, MFLAGS);
static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata =
@@ -1162,7 +1197,7 @@ static struct rockchip_clk_branch rk3399
GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(28), 0, GFLAGS),
- COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, 0,
+ COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", vop0_mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3399_CLKGATE_CON(10), 12, GFLAGS),
diff -rupN linux.orig/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c linux/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c
--- linux.orig/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c 2024-01-03 20:53:30.399321361 +0000
+++ linux/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c 2024-01-03 21:27:13.822235237 +0000
@@ -4,6 +4,7 @@
*
* Copyright (C) 2015-2017 Russell King.
*/
+#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
@@ -129,8 +130,15 @@ static irqreturn_t dw_hdmi_cec_hardirq(i
dw_hdmi_write(cec, stat, HDMI_IH_CEC_STAT0);
- if (stat & CEC_STAT_ERROR_INIT) {
- cec->tx_status = CEC_TX_STATUS_ERROR;
+ /* Status with both done and error_initiator bits have been seen
+ * on Rockchip RK3328 devices, transmit attempt seems to have failed
+ * when this happens, report as low drive and block cec-framework
+ * 100ms before core retransmits the failed message, this seems to
+ * mitigate the issue with failed transmit attempts.
+ */
+ if ((stat & (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) == (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) {
+ pr_debug("dw_hdmi_cec_hardirq: stat=%02x LOW_DRIVE\n", stat);
+ cec->tx_status = CEC_TX_STATUS_LOW_DRIVE;
cec->tx_done = true;
ret = IRQ_WAKE_THREAD;
} else if (stat & CEC_STAT_DONE) {
@@ -141,6 +149,10 @@ static irqreturn_t dw_hdmi_cec_hardirq(i
cec->tx_status = CEC_TX_STATUS_NACK;
cec->tx_done = true;
ret = IRQ_WAKE_THREAD;
+ } else if (stat & CEC_STAT_ERROR_INIT) {
+ cec->tx_status = CEC_TX_STATUS_ERROR;
+ cec->tx_done = true;
+ ret = IRQ_WAKE_THREAD;
}
if (stat & CEC_STAT_EOM) {
@@ -173,6 +185,8 @@ static irqreturn_t dw_hdmi_cec_thread(in
if (cec->tx_done) {
cec->tx_done = false;
+ if (cec->tx_status == CEC_TX_STATUS_LOW_DRIVE)
+ msleep(100);
cec_transmit_attempt_done(adap, cec->tx_status);
}
if (cec->rx_done) {
diff -rupN linux.orig/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c linux/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
--- linux.orig/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c 2024-01-03 20:53:30.399321361 +0000
+++ linux/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c 2024-01-03 21:27:13.822235237 +0000
@@ -34,9 +34,9 @@ static inline u8 hdmi_read(struct dw_hdm
return audio->read(hdmi, offset);
}
-static int dw_hdmi_i2s_hw_params(struct device *dev, void *data,
- struct hdmi_codec_daifmt *fmt,
- struct hdmi_codec_params *hparms)
+static int dw_hdmi_i2s_prepare(struct device *dev, void *data,
+ struct hdmi_codec_daifmt *fmt,
+ struct hdmi_codec_params *hparms)
{
struct dw_hdmi_i2s_audio_data *audio = data;
struct dw_hdmi *hdmi = audio->hdmi;
@@ -178,7 +178,7 @@ static int dw_hdmi_i2s_hook_plugged_cb(s
}
static const struct hdmi_codec_ops dw_hdmi_i2s_ops = {
- .hw_params = dw_hdmi_i2s_hw_params,
+ .prepare = dw_hdmi_i2s_prepare,
.audio_startup = dw_hdmi_i2s_audio_startup,
.audio_shutdown = dw_hdmi_i2s_audio_shutdown,
.get_eld = dw_hdmi_i2s_get_eld,
diff -rupN linux.orig/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c linux/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
--- linux.orig/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c 2024-01-03 20:53:30.399321361 +0000
+++ linux/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c 2024-01-03 21:17:09.402615966 +0000
@@ -82,15 +82,15 @@ static const u16 csc_coeff_rgb_out_eitu7
};
static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
- { 0x2591, 0x1322, 0x074b, 0x0000 },
- { 0x6535, 0x2000, 0x7acc, 0x0200 },
- { 0x6acd, 0x7534, 0x2000, 0x0200 }
+ { 0x2040, 0x1080, 0x0640, 0x0040 },
+ { 0xe880, 0x1c00, 0xfb80, 0x0200 },
+ { 0xed80, 0xf680, 0x1c00, 0x0200 }
};
static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
- { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
- { 0x62f0, 0x2000, 0x7d11, 0x0200 },
- { 0x6756, 0x78ab, 0x2000, 0x0200 }
+ { 0x2740, 0x0bc0, 0x0400, 0x0040 },
+ { 0xe680, 0x1c00, 0xfd80, 0x0200 },
+ { 0xea40, 0xf980, 0x1c00, 0x0200 }
};
static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = {
@@ -138,7 +138,8 @@ struct dw_hdmi_phy_data {
bool has_svsret;
int (*configure)(struct dw_hdmi *hdmi,
const struct dw_hdmi_plat_data *pdata,
- unsigned long mpixelclock);
+ unsigned long mpixelclock,
+ unsigned long mtmdsclock);
};
struct dw_hdmi {
@@ -1585,13 +1586,17 @@ static int dw_hdmi_phy_power_on(struct d
*/
static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
const struct dw_hdmi_plat_data *pdata,
- unsigned long mpixelclock)
+ unsigned long mpixelclock,
+ unsigned long mtmdsclock)
{
const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
+ int depth;
- /* TOFIX Will need 420 specific PHY configuration tables */
+ if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) &&
+ pdata->mpll_cfg_420)
+ mpll_config = pdata->mpll_cfg_420;
/* PLL/MPLL Cfg - always match on final entry */
for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
@@ -1599,11 +1604,11 @@ static int hdmi_phy_configure_dwc_hdmi_3
break;
for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
- if (mpixelclock <= curr_ctrl->mpixelclock)
+ if (mtmdsclock <= curr_ctrl->mpixelclock)
break;
for (; phy_config->mpixelclock != ~0UL; phy_config++)
- if (mpixelclock <= phy_config->mpixelclock)
+ if (mtmdsclock <= phy_config->mpixelclock)
break;
if (mpll_config->mpixelclock == ~0UL ||
@@ -1611,11 +1616,17 @@ static int hdmi_phy_configure_dwc_hdmi_3
phy_config->mpixelclock == ~0UL)
return -EINVAL;
- dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
+ depth = hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format);
+ if (depth > 8 && mpixelclock != mtmdsclock)
+ depth = fls(depth - 8) - 1;
+ else
+ depth = 0;
+
+ dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].cpce,
HDMI_3D_TX_PHY_CPCE_CTRL);
- dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
+ dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].gmp,
HDMI_3D_TX_PHY_GMPCTRL);
- dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
+ dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[depth],
HDMI_3D_TX_PHY_CURRCTRL);
dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
@@ -1660,9 +1671,9 @@ static int hdmi_phy_configure(struct dw_
/* Write to the PHY as configured by the platform */
if (pdata->configure_phy)
- ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock);
+ ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock, mtmdsclock);
else
- ret = phy->configure(hdmi, pdata, mpixelclock);
+ ret = phy->configure(hdmi, pdata, mpixelclock, mtmdsclock);
if (ret) {
dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n",
mpixelclock);
@@ -1779,6 +1790,7 @@ static void hdmi_config_AVI(struct dw_hd
const struct drm_connector *connector,
const struct drm_display_mode *mode)
{
+ const struct drm_connector_state *conn_state = connector->state;
struct hdmi_avi_infoframe frame;
u8 val;
@@ -1836,6 +1848,8 @@ static void hdmi_config_AVI(struct dw_hd
HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
}
+ drm_hdmi_avi_infoframe_content_type(&frame, conn_state);
+
/*
* The Designware IP uses a different byte format from standard
* AVI info frames, though generally the bits are in the correct
@@ -1992,6 +2006,21 @@ static void hdmi_config_drm_infoframe(st
HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);
}
+static unsigned int
+hdmi_get_tmdsclock(unsigned int bus_format, unsigned int pixelclock)
+{
+ int color_depth = hdmi_bus_fmt_color_depth(bus_format);
+ unsigned int tmdsclock = pixelclock;
+
+ if (!hdmi_bus_fmt_is_yuv422(bus_format) && color_depth > 8)
+ tmdsclock = (u64)pixelclock * color_depth / 8;
+
+ if (hdmi_bus_fmt_is_yuv420(bus_format))
+ tmdsclock /= 2;
+
+ return tmdsclock;
+}
+
static void hdmi_av_composer(struct dw_hdmi *hdmi,
const struct drm_display_info *display,
const struct drm_display_mode *mode)
@@ -2003,29 +2032,11 @@ static void hdmi_av_composer(struct dw_h
unsigned int vdisplay, hdisplay;
vmode->mpixelclock = mode->clock * 1000;
+ vmode->mtmdsclock =
+ hdmi_get_tmdsclock(hdmi->hdmi_data.enc_out_bus_format,
+ vmode->mpixelclock);
dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
-
- vmode->mtmdsclock = vmode->mpixelclock;
-
- if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
- switch (hdmi_bus_fmt_color_depth(
- hdmi->hdmi_data.enc_out_bus_format)) {
- case 16:
- vmode->mtmdsclock = vmode->mpixelclock * 2;
- break;
- case 12:
- vmode->mtmdsclock = vmode->mpixelclock * 3 / 2;
- break;
- case 10:
- vmode->mtmdsclock = vmode->mpixelclock * 5 / 4;
- break;
- }
- }
-
- if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
- vmode->mtmdsclock /= 2;
-
dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock);
/* Set up HDMI_FC_INVIDCONF */
@@ -2543,7 +2554,8 @@ static int dw_hdmi_connector_atomic_chec
if (!crtc)
return 0;
- if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
+ if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state) ||
+ old_state->content_type != new_state->content_type) {
crtc_state = drm_atomic_get_crtc_state(state, crtc);
if (IS_ERR(crtc_state))
return PTR_ERR(crtc_state);
@@ -2611,6 +2623,8 @@ static int dw_hdmi_connector_create(stru
drm_connector_attach_max_bpc_property(connector, 8, 16);
+ drm_connector_attach_content_type_property(connector);
+
if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe)
drm_connector_attach_hdr_output_metadata_property(connector);
@@ -2652,8 +2666,21 @@ static int dw_hdmi_connector_create(stru
* - MEDIA_BUS_FMT_RGB888_1X24,
*/
-/* Can return a maximum of 11 possible output formats for a mode/connector */
-#define MAX_OUTPUT_SEL_FORMATS 11
+/* Can return a maximum of 15 possible output formats for a mode/connector */
+#define MAX_OUTPUT_SEL_FORMATS 15
+
+static bool is_tmds_allowed(struct drm_display_info *info,
+ struct drm_display_mode *mode,
+ u32 bus_format)
+{
+ unsigned long tmdsclock = hdmi_get_tmdsclock(bus_format, mode->clock);
+ int max_tmds_clock = info->max_tmds_clock ? info->max_tmds_clock : 340000;
+
+ if (max_tmds_clock >= tmdsclock)
+ return true;
+
+ return false;
+}
static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
struct drm_bridge_state *bridge_state,
@@ -2665,8 +2692,6 @@ static u32 *dw_hdmi_bridge_atomic_get_ou
struct drm_display_info *info = &conn->display_info;
struct drm_display_mode *mode = &crtc_state->mode;
u8 max_bpc = conn_state->max_requested_bpc;
- bool is_hdmi2_sink = info->hdmi.scdc.supported ||
- (info->color_formats & DRM_COLOR_FORMAT_YCBCR420);
u32 *output_fmts;
unsigned int i = 0;
@@ -2690,29 +2715,33 @@ static u32 *dw_hdmi_bridge_atomic_get_ou
* If the current mode enforces 4:2:0, force the output but format
* to 4:2:0 and do not add the YUV422/444/RGB formats
*/
- if (conn->ycbcr_420_allowed &&
- (drm_mode_is_420_only(info, mode) ||
- (is_hdmi2_sink && drm_mode_is_420_also(info, mode)))) {
+ if (conn->ycbcr_420_allowed && drm_mode_is_420(info, mode) &&
+ (info->color_formats & DRM_COLOR_FORMAT_YCBCR420)) {
/* Order bus formats from 16bit to 8bit if supported */
if (max_bpc >= 16 && info->bpc == 16 &&
- (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48))
+ (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) &&
+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYYVYY16_0_5X48))
output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY16_0_5X48;
if (max_bpc >= 12 && info->bpc >= 12 &&
- (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36))
+ (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) &&
+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYYVYY12_0_5X36))
output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY12_0_5X36;
if (max_bpc >= 10 && info->bpc >= 10 &&
- (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30))
+ (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) &&
+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYYVYY10_0_5X30))
output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY10_0_5X30;
/* Default 8bit fallback */
- output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24;
+ if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYYVYY8_0_5X24))
+ output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24;
*num_output_fmts = i;
- return output_fmts;
+ if (drm_mode_is_420_only(info, mode))
+ return output_fmts;
}
/*
@@ -2721,39 +2750,50 @@ static u32 *dw_hdmi_bridge_atomic_get_ou
*/
/* Default 8bit RGB fallback */
- output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
+ if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB888_1X24))
+ output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
if (max_bpc >= 16 && info->bpc == 16) {
- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
+ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR444) &&
+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_YUV16_1X48))
output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
- output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
+ if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB161616_1X48))
+ output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
}
if (max_bpc >= 12 && info->bpc >= 12) {
- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
+ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR422) &&
+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYVY12_1X24))
output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
+ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR444) &&
+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_YUV12_1X36))
output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
- output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
+ if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB121212_1X36))
+ output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
}
if (max_bpc >= 10 && info->bpc >= 10) {
- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
+ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR422) &&
+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYVY10_1X20))
output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
+ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR444) &&
+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_YUV10_1X30))
output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
- output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
+ if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB101010_1X30))
+ output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
}
- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
+ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR422) &&
+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYVY8_1X16))
output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
+ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR444) &&
+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_YUV8_1X24))
output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
*num_output_fmts = i;
@@ -2935,11 +2975,20 @@ dw_hdmi_bridge_mode_valid(struct drm_bri
struct dw_hdmi *hdmi = bridge->driver_private;
const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
enum drm_mode_status mode_status = MODE_OK;
+ int max_tmds_clock = info->max_tmds_clock ? info->max_tmds_clock : 340000;
+ int clock = mode->clock;
/* We don't support double-clocked modes */
if (mode->flags & DRM_MODE_FLAG_DBLCLK)
return MODE_BAD;
+ if (pdata->ycbcr_420_allowed && drm_mode_is_420(info, mode) &&
+ (info->color_formats & DRM_COLOR_FORMAT_YCBCR420))
+ clock /= 2;
+
+ if (clock > max_tmds_clock)
+ return MODE_CLOCK_HIGH;
+
if (pdata->mode_valid)
mode_status = pdata->mode_valid(hdmi, pdata->priv_data, info,
mode);
@@ -3130,12 +3179,6 @@ static irqreturn_t dw_hdmi_irq(int irq,
phy_stat & HDMI_PHY_HPD,
phy_stat & HDMI_PHY_RX_SENSE);
- if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) {
- mutex_lock(&hdmi->cec_notifier_mutex);
- cec_notifier_phys_addr_invalidate(hdmi->cec_notifier);
- mutex_unlock(&hdmi->cec_notifier_mutex);
- }
-
if (phy_stat & HDMI_PHY_HPD)
status = connector_status_connected;
@@ -3152,6 +3195,14 @@ static irqreturn_t dw_hdmi_irq(int irq,
drm_helper_hpd_irq_event(hdmi->bridge.dev);
drm_bridge_hpd_notify(&hdmi->bridge, status);
}
+
+ if (status == connector_status_disconnected &&
+ (phy_stat & HDMI_PHY_RX_SENSE) &&
+ (phy_int_pol & HDMI_PHY_RX_SENSE)) {
+ mutex_lock(&hdmi->cec_notifier_mutex);
+ cec_notifier_phys_addr_invalidate(hdmi->cec_notifier);
+ mutex_unlock(&hdmi->cec_notifier_mutex);
+ }
}
hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
diff -rupN linux.orig/drivers/gpu/drm/drm_fourcc.c linux/drivers/gpu/drm/drm_fourcc.c
--- linux.orig/drivers/gpu/drm/drm_fourcc.c 2024-01-03 20:53:30.403321415 +0000
+++ linux/drivers/gpu/drm/drm_fourcc.c 2024-01-03 21:08:03.815052659 +0000
@@ -299,6 +299,14 @@ const struct drm_format_info *__drm_form
.num_planes = 2, .char_per_block = { 5, 5, 0 },
.block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 2,
.vsub = 2, .is_yuv = true },
+ { .format = DRM_FORMAT_NV20, .depth = 0,
+ .num_planes = 2, .char_per_block = { 5, 5, 0 },
+ .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 2,
+ .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_NV30, .depth = 0,
+ .num_planes = 2, .char_per_block = { 5, 5, 0 },
+ .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 1,
+ .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_Q410, .depth = 0,
.num_planes = 3, .char_per_block = { 2, 2, 2 },
.block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, .hsub = 1,
diff -rupN linux.orig/drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c linux/drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c
--- linux.orig/drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c 2024-01-03 20:53:30.535323197 +0000
+++ linux/drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c 2024-01-03 21:17:09.402615966 +0000
@@ -53,7 +53,8 @@ rcar_hdmi_mode_valid(struct dw_hdmi *hdm
}
static int rcar_hdmi_phy_configure(struct dw_hdmi *hdmi, void *data,
- unsigned long mpixelclock)
+ unsigned long mpixelclock,
+ unsigned long mtmdsclock)
{
const struct rcar_hdmi_phy_params *params = rcar_hdmi_phy_params;
diff -rupN linux.orig/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c linux/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
--- linux.orig/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c 2024-01-03 20:53:30.535323197 +0000
+++ linux/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c 2024-01-03 21:17:09.402615966 +0000
@@ -5,6 +5,7 @@
#include <linux/clk.h>
#include <linux/mfd/syscon.h>
+#include <linux/media-bus-format.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/phy/phy.h>
@@ -67,11 +68,13 @@ struct rockchip_hdmi_chip_data {
int lcdsel_grf_reg;
u32 lcdsel_big;
u32 lcdsel_lit;
+ bool ycbcr_444_allowed;
};
struct rockchip_hdmi {
struct device *dev;
struct regmap *regmap;
+ struct drm_bridge bridge;
struct rockchip_encoder encoder;
const struct rockchip_hdmi_chip_data *chip_data;
struct clk *ref_clk;
@@ -82,89 +85,177 @@ struct rockchip_hdmi {
struct phy *phy;
};
-static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder)
-{
- struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
+#define to_crtc_state(x) container_of(x, struct drm_crtc_state, x)
- return container_of(rkencoder, struct rockchip_hdmi, encoder);
+static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_bridge *bridge)
+{
+ return container_of(bridge, struct rockchip_hdmi, bridge);
}
static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
{
- 27000000, {
- { 0x00b3, 0x0000},
- { 0x2153, 0x0000},
- { 0x40f3, 0x0000}
- },
- }, {
- 36000000, {
- { 0x00b3, 0x0000},
- { 0x2153, 0x0000},
- { 0x40f3, 0x0000}
- },
- }, {
- 40000000, {
- { 0x00b3, 0x0000},
- { 0x2153, 0x0000},
- { 0x40f3, 0x0000}
- },
- }, {
- 54000000, {
- { 0x0072, 0x0001},
- { 0x2142, 0x0001},
- { 0x40a2, 0x0001},
- },
- }, {
- 65000000, {
- { 0x0072, 0x0001},
- { 0x2142, 0x0001},
- { 0x40a2, 0x0001},
- },
- }, {
- 66000000, {
- { 0x013e, 0x0003},
- { 0x217e, 0x0002},
- { 0x4061, 0x0002}
- },
- }, {
- 74250000, {
- { 0x0072, 0x0001},
- { 0x2145, 0x0002},
- { 0x4061, 0x0002}
- },
- }, {
- 83500000, {
- { 0x0072, 0x0001},
- },
- }, {
- 108000000, {
- { 0x0051, 0x0002},
- { 0x2145, 0x0002},
- { 0x4061, 0x0002}
- },
- }, {
- 106500000, {
- { 0x0051, 0x0002},
- { 0x2145, 0x0002},
- { 0x4061, 0x0002}
- },
- }, {
- 146250000, {
- { 0x0051, 0x0002},
- { 0x2145, 0x0002},
- { 0x4061, 0x0002}
- },
- }, {
- 148500000, {
- { 0x0051, 0x0003},
- { 0x214c, 0x0003},
- { 0x4064, 0x0003}
+ 30666000, {
+ { 0x00b3, 0x0000 },
+ { 0x2153, 0x0000 },
+ { 0x40f3, 0x0000 },
+ },
+ }, {
+ 36800000, {
+ { 0x00b3, 0x0000 },
+ { 0x2153, 0x0000 },
+ { 0x40a2, 0x0001 },
+ },
+ }, {
+ 46000000, {
+ { 0x00b3, 0x0000 },
+ { 0x2142, 0x0001 },
+ { 0x40a2, 0x0001 },
+ },
+ }, {
+ 61333000, {
+ { 0x0072, 0x0001 },
+ { 0x2142, 0x0001 },
+ { 0x40a2, 0x0001 },
+ },
+ }, {
+ 73600000, {
+ { 0x0072, 0x0001 },
+ { 0x2142, 0x0001 },
+ { 0x4061, 0x0002 },
+ },
+ }, {
+ 92000000, {
+ { 0x0072, 0x0001 },
+ { 0x2145, 0x0002 },
+ { 0x4061, 0x0002 },
+ },
+ }, {
+ 122666000, {
+ { 0x0051, 0x0002 },
+ { 0x2145, 0x0002 },
+ { 0x4061, 0x0002 },
+ },
+ }, {
+ 147200000, {
+ { 0x0051, 0x0002 },
+ { 0x2145, 0x0002 },
+ { 0x4064, 0x0003 },
+ },
+ }, {
+ 184000000, {
+ { 0x0051, 0x0002 },
+ { 0x214c, 0x0003 },
+ { 0x4064, 0x0003 },
+ },
+ }, {
+ 226666000, {
+ { 0x0040, 0x0003 },
+ { 0x214c, 0x0003 },
+ { 0x4064, 0x0003 },
+ },
+ }, {
+ 272000000, {
+ { 0x0040, 0x0003 },
+ { 0x214c, 0x0003 },
+ { 0x5a64, 0x0003 },
+ },
+ }, {
+ 340000000, {
+ { 0x0040, 0x0003 },
+ { 0x3b4c, 0x0003 },
+ { 0x5a64, 0x0003 },
+ },
+ }, {
+ 600000000, {
+ { 0x1a40, 0x0003 },
+ { 0x3b4c, 0x0003 },
+ { 0x5a64, 0x0003 },
+ },
+ }, {
+ ~0UL, {
+ { 0x0000, 0x0000 },
+ { 0x0000, 0x0000 },
+ { 0x0000, 0x0000 },
+ },
+ }
+};
+
+static const struct dw_hdmi_mpll_config rockchip_mpll_cfg_420[] = {
+ {
+ 30666000, {
+ { 0x00b7, 0x0000 },
+ { 0x2157, 0x0000 },
+ { 0x40f7, 0x0000 },
+ },
+ }, {
+ 92000000, {
+ { 0x00b7, 0x0000 },
+ { 0x2143, 0x0001 },
+ { 0x40a3, 0x0001 },
+ },
+ }, {
+ 184000000, {
+ { 0x0073, 0x0001 },
+ { 0x2146, 0x0002 },
+ { 0x4062, 0x0002 },
+ },
+ }, {
+ 340000000, {
+ { 0x0052, 0x0003 },
+ { 0x214d, 0x0003 },
+ { 0x4065, 0x0003 },
+ },
+ }, {
+ 600000000, {
+ { 0x0041, 0x0003 },
+ { 0x3b4d, 0x0003 },
+ { 0x5a65, 0x0003 },
+ },
+ }, {
+ ~0UL, {
+ { 0x0000, 0x0000 },
+ { 0x0000, 0x0000 },
+ { 0x0000, 0x0000 },
+ },
+ }
+};
+
+static const struct dw_hdmi_mpll_config rockchip_rk3288w_mpll_cfg_420[] = {
+ {
+ 30666000, {
+ { 0x00b7, 0x0000 },
+ { 0x2157, 0x0000 },
+ { 0x40f7, 0x0000 },
+ },
+ }, {
+ 92000000, {
+ { 0x00b7, 0x0000 },
+ { 0x2143, 0x0001 },
+ { 0x40a3, 0x0001 },
+ },
+ }, {
+ 184000000, {
+ { 0x0073, 0x0001 },
+ { 0x2146, 0x0002 },
+ { 0x4062, 0x0002 },
+ },
+ }, {
+ 340000000, {
+ { 0x0052, 0x0003 },
+ { 0x214d, 0x0003 },
+ { 0x4065, 0x0003 },
+ },
+ }, {
+ 600000000, {
+ { 0x0040, 0x0003 },
+ { 0x3b4c, 0x0003 },
+ { 0x5a65, 0x0003 },
},
- }, {
+ }, {
~0UL, {
- { 0x00a0, 0x000a },
- { 0x2001, 0x000f },
- { 0x4002, 0x000f },
+ { 0x0000, 0x0000 },
+ { 0x0000, 0x0000 },
+ { 0x0000, 0x0000 },
},
}
};
@@ -172,20 +263,8 @@ static const struct dw_hdmi_mpll_config
static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
/* pixelclk bpp8 bpp10 bpp12 */
{
- 40000000, { 0x0018, 0x0018, 0x0018 },
- }, {
- 65000000, { 0x0028, 0x0028, 0x0028 },
- }, {
- 66000000, { 0x0038, 0x0038, 0x0038 },
- }, {
- 74250000, { 0x0028, 0x0038, 0x0038 },
- }, {
- 83500000, { 0x0028, 0x0038, 0x0038 },
- }, {
- 146250000, { 0x0038, 0x0038, 0x0038 },
- }, {
- 148500000, { 0x0000, 0x0038, 0x0038 },
- }, {
+ 600000000, { 0x0000, 0x0000, 0x0000 },
+ }, {
~0UL, { 0x0000, 0x0000, 0x0000},
}
};
@@ -193,8 +272,9 @@ static const struct dw_hdmi_curr_ctrl ro
static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
/*pixelclk symbol term vlev*/
{ 74250000, 0x8009, 0x0004, 0x0272},
- { 148500000, 0x802b, 0x0004, 0x028d},
+ { 165000000, 0x802b, 0x0004, 0x0209},
{ 297000000, 0x8039, 0x0005, 0x028d},
+ { 594000000, 0x8039, 0x0000, 0x019d},
{ ~0UL, 0x0000, 0x0000, 0x0000}
};
@@ -245,45 +325,52 @@ dw_hdmi_rockchip_mode_valid(struct dw_hd
const struct drm_display_info *info,
const struct drm_display_mode *mode)
{
- const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
- int pclk = mode->clock * 1000;
- bool valid = false;
- int i;
+ struct dw_hdmi_plat_data *pdata = (struct dw_hdmi_plat_data *)data;
+ const struct dw_hdmi_mpll_config *mpll_cfg = pdata->mpll_cfg;
+ int clock = mode->clock;
+ unsigned int i = 0;
- for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
- if (pclk == mpll_cfg[i].mpixelclock) {
- valid = true;
- break;
- }
+ if (pdata->ycbcr_420_allowed && drm_mode_is_420(info, mode) &&
+ (info->color_formats & DRM_COLOR_FORMAT_YCBCR420)) {
+ clock /= 2;
+ mpll_cfg = pdata->mpll_cfg_420;
}
- return (valid) ? MODE_OK : MODE_BAD;
-}
+ if ((!mpll_cfg && clock > 340000) ||
+ (info->max_tmds_clock && clock > info->max_tmds_clock))
+ return MODE_CLOCK_HIGH;
-static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
-{
-}
+ if (mpll_cfg) {
+ while ((clock * 1000) < mpll_cfg[i].mpixelclock &&
+ mpll_cfg[i].mpixelclock != (~0UL))
+ i++;
-static bool
-dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adj_mode)
-{
- return true;
-}
+ if (mpll_cfg[i].mpixelclock == (~0UL))
+ return MODE_CLOCK_HIGH;
+ }
-static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
- struct drm_display_mode *mode,
- struct drm_display_mode *adj_mode)
+ return MODE_OK;
+}
+static void
+dw_hdmi_rockchip_bridge_mode_set(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ const struct drm_display_mode *adjusted_mode)
{
- struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
+ struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge);
+ struct drm_crtc_state *crtc_state = to_crtc_state(adjusted_mode);
+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
- clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000);
+ if (hdmi->phy)
+ phy_set_bus_width(hdmi->phy, s->bus_width);
+
+ clk_set_rate(hdmi->ref_clk, adjusted_mode->clock * 1000);
}
-static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
+static void dw_hdmi_rockchip_bridge_enable(struct drm_bridge *bridge)
{
- struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
+ struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge);
+ struct drm_encoder *encoder = bridge->encoder;
+
u32 val;
int ret;
@@ -311,25 +398,143 @@ static void dw_hdmi_rockchip_encoder_ena
ret ? "LIT" : "BIG");
}
+static bool is_rgb(u32 format)
+{
+ switch (format) {
+ case MEDIA_BUS_FMT_RGB888_1X24:
+ case MEDIA_BUS_FMT_RGB101010_1X30:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool is_yuv444(u32 format)
+{
+ switch (format) {
+ case MEDIA_BUS_FMT_YUV10_1X30:
+ case MEDIA_BUS_FMT_YUV8_1X24:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool is_yuv420(u32 format)
+{
+ switch (format) {
+ case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
+ case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool is_10bit(u32 format)
+{
+ switch (format) {
+ case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
+ case MEDIA_BUS_FMT_RGB101010_1X30:
+ case MEDIA_BUS_FMT_YUV10_1X30:
+ return true;
+ default:
+ return false;
+ }
+}
+
static int
-dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
- struct drm_crtc_state *crtc_state,
- struct drm_connector_state *conn_state)
+dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
{
struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
+ struct drm_atomic_state *state = bridge_state->base.state;
+ struct drm_crtc_state *old_crtc_state;
+ struct rockchip_crtc_state *old_state;
+ struct drm_bridge *next_bridge;
+ struct drm_bridge_state *next_bridge_state;
+ u32 format = bridge_state->output_bus_cfg.format;
s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
s->output_type = DRM_MODE_CONNECTOR_HDMIA;
+ s->output_bpc = 10;
+ s->bus_format = format;
+
+ next_bridge = drm_bridge_get_next_bridge(bridge);
+ if (next_bridge) {
+ next_bridge_state = drm_atomic_get_new_bridge_state(state,
+ next_bridge);
+ format = next_bridge_state->output_bus_cfg.format;
+ }
+
+ s->bus_width = is_10bit(format) ? 10 : 8;
+
+ if (is_yuv420(format)) {
+ s->output_mode = ROCKCHIP_OUT_MODE_YUV420;
+ s->bus_width /= 2;
+ }
+
+ old_crtc_state = drm_atomic_get_old_crtc_state(state, conn_state->crtc);
+ if (old_crtc_state && !crtc_state->mode_changed) {
+ old_state = to_rockchip_crtc_state(old_crtc_state);
+ if (s->bus_format != old_state->bus_format ||
+ s->bus_width != old_state->bus_width)
+ crtc_state->mode_changed = true;
+ }
return 0;
}
-static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
- .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
- .mode_set = dw_hdmi_rockchip_encoder_mode_set,
- .enable = dw_hdmi_rockchip_encoder_enable,
- .disable = dw_hdmi_rockchip_encoder_disable,
- .atomic_check = dw_hdmi_rockchip_encoder_atomic_check,
+static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ u32 output_fmt,
+ unsigned int *num_input_fmts)
+{
+ struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge);
+ struct drm_encoder *encoder = bridge->encoder;
+ struct drm_connector *connector = conn_state->connector;
+ u32 *input_fmt;
+ bool has_10bit = true;
+
+ *num_input_fmts = 0;
+
+ if (drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder))
+ has_10bit = false;
+
+ if (!has_10bit && is_10bit(output_fmt))
+ return NULL;
+
+ if (is_yuv444(output_fmt)) {
+ if (!hdmi->chip_data->ycbcr_444_allowed)
+ return NULL;
+ } else if (is_yuv420(output_fmt)) {
+ if (!connector->ycbcr_420_allowed)
+ return NULL;
+ } else if (!is_rgb(output_fmt))
+ return NULL;
+
+ input_fmt = kzalloc(sizeof(*input_fmt), GFP_KERNEL);
+ if (!input_fmt)
+ return NULL;
+
+ *num_input_fmts = 1;
+ *input_fmt = output_fmt;
+
+ return input_fmt;
+}
+
+static const struct drm_bridge_funcs dw_hdmi_rockchip_bridge_funcs = {
+ .mode_set = dw_hdmi_rockchip_bridge_mode_set,
+ .enable = dw_hdmi_rockchip_bridge_enable,
+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
+ .atomic_get_input_bus_fmts = dw_hdmi_rockchip_get_input_bus_fmts,
+ .atomic_check = dw_hdmi_rockchip_bridge_atomic_check,
+ .atomic_reset = drm_atomic_helper_bridge_reset,
};
static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data,
@@ -338,6 +543,8 @@ static int dw_hdmi_rockchip_genphy_init(
{
struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
+ dw_hdmi_set_high_tmds_clock_ratio(dw_hdmi, display);
+
return phy_power_on(hdmi->phy);
}
@@ -422,17 +629,16 @@ static const struct dw_hdmi_phy_ops rk32
static struct rockchip_hdmi_chip_data rk3228_chip_data = {
.lcdsel_grf_reg = -1,
+ .ycbcr_444_allowed = true,
};
static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = {
.mode_valid = dw_hdmi_rockchip_mode_valid,
- .mpll_cfg = rockchip_mpll_cfg,
- .cur_ctr = rockchip_cur_ctr,
- .phy_config = rockchip_phy_config,
.phy_data = &rk3228_chip_data,
.phy_ops = &rk3228_hdmi_phy_ops,
.phy_name = "inno_dw_hdmi_phy2",
.phy_force_vendor = true,
+ .ycbcr_420_allowed = true,
};
static struct rockchip_hdmi_chip_data rk3288_chip_data = {
@@ -444,6 +650,7 @@ static struct rockchip_hdmi_chip_data rk
static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
.mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
+ .mpll_cfg_420 = rockchip_rk3288w_mpll_cfg_420,
.cur_ctr = rockchip_cur_ctr,
.phy_config = rockchip_phy_config,
.phy_data = &rk3288_chip_data,
@@ -459,18 +666,17 @@ static const struct dw_hdmi_phy_ops rk33
static struct rockchip_hdmi_chip_data rk3328_chip_data = {
.lcdsel_grf_reg = -1,
+ .ycbcr_444_allowed = true,
};
static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
.mode_valid = dw_hdmi_rockchip_mode_valid,
- .mpll_cfg = rockchip_mpll_cfg,
- .cur_ctr = rockchip_cur_ctr,
- .phy_config = rockchip_phy_config,
.phy_data = &rk3328_chip_data,
.phy_ops = &rk3328_hdmi_phy_ops,
.phy_name = "inno_dw_hdmi_phy2",
.phy_force_vendor = true,
.use_drm_infoframe = true,
+ .ycbcr_420_allowed = true,
};
static struct rockchip_hdmi_chip_data rk3399_chip_data = {
@@ -482,6 +688,7 @@ static struct rockchip_hdmi_chip_data rk
static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
.mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
+ .mpll_cfg_420 = rockchip_mpll_cfg_420,
.cur_ctr = rockchip_cur_ctr,
.phy_config = rockchip_phy_config,
.phy_data = &rk3399_chip_data,
@@ -528,6 +735,7 @@ static int dw_hdmi_rockchip_bind(struct
struct dw_hdmi_plat_data *plat_data;
const struct of_device_id *match;
struct drm_device *drm = data;
+ struct drm_bridge *next_bridge;
struct drm_encoder *encoder;
struct rockchip_hdmi *hdmi;
int ret;
@@ -546,6 +754,7 @@ static int dw_hdmi_rockchip_bind(struct
return -ENOMEM;
hdmi->dev = &pdev->dev;
+ plat_data->priv_data = plat_data;
hdmi->chip_data = plat_data->phy_data;
plat_data->phy_data = hdmi;
encoder = &hdmi->encoder.encoder;
@@ -574,7 +783,7 @@ static int dw_hdmi_rockchip_bind(struct
if (IS_ERR(hdmi->phy)) {
ret = PTR_ERR(hdmi->phy);
if (ret != -EPROBE_DEFER)
- DRM_DEV_ERROR(hdmi->dev, "failed to get phy\n");
+ DRM_DEV_ERROR(hdmi->dev, "Failed to get phy: %d\n", ret);
return ret;
}
@@ -605,15 +814,21 @@ static int dw_hdmi_rockchip_bind(struct
RK3568_HDMI_SCLIN_MSK));
}
- drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
- drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
+ ret = drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
+ if (ret) {
+ DRM_DEV_ERROR(hdmi->dev, "Failed to init encoder: %d\n", ret);
+ goto err_disable_clk;
+ }
+
+ hdmi->bridge.funcs = &dw_hdmi_rockchip_bridge_funcs;
+ drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0);
platform_set_drvdata(pdev, hdmi);
- hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data);
+ hdmi->hdmi = dw_hdmi_probe(pdev, plat_data);
/*
- * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
+ * If dw_hdmi_probe() fails we'll never call dw_hdmi_unbind(),
* which would have called the encoder cleanup. Do it manually.
*/
if (IS_ERR(hdmi->hdmi)) {
@@ -621,10 +836,26 @@ static int dw_hdmi_rockchip_bind(struct
goto err_bind;
}
+ next_bridge = of_drm_find_bridge(pdev->dev.of_node);
+ if (!next_bridge) {
+ ret = -EPROBE_DEFER;
+ goto err_dw_hdmi_remove;
+ }
+
+ ret = drm_bridge_attach(encoder, next_bridge, &hdmi->bridge, 0);
+ if (ret) {
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(hdmi->dev, "Failed to attach dw-hdmi bridge: %d\n", ret);
+ goto err_dw_hdmi_remove;
+ }
+
return 0;
+err_dw_hdmi_remove:
+ dw_hdmi_remove(hdmi->hdmi);
err_bind:
drm_encoder_cleanup(encoder);
+err_disable_clk:
clk_disable_unprepare(hdmi->ref_clk);
err_clk:
regulator_disable(hdmi->avdd_1v8);
@@ -639,7 +870,7 @@ static void dw_hdmi_rockchip_unbind(stru
{
struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
- dw_hdmi_unbind(hdmi->hdmi);
+ dw_hdmi_remove(hdmi->hdmi);
drm_encoder_cleanup(&hdmi->encoder.encoder);
clk_disable_unprepare(hdmi->ref_clk);
diff -rupN linux.orig/drivers/gpu/drm/rockchip/rockchip_drm_drv.h linux/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
--- linux.orig/drivers/gpu/drm/rockchip/rockchip_drm_drv.h 2024-01-03 20:53:30.535323197 +0000
+++ linux/drivers/gpu/drm/rockchip/rockchip_drm_drv.h 2024-01-03 21:17:09.402615966 +0000
@@ -34,6 +34,7 @@ struct rockchip_crtc_state {
u32 bus_format;
u32 bus_flags;
int color_space;
+ int bus_width;
};
#define to_rockchip_crtc_state(s) \
container_of(s, struct rockchip_crtc_state, base)
diff -rupN linux.orig/drivers/gpu/drm/rockchip/rockchip_drm_fb.c linux/drivers/gpu/drm/rockchip/rockchip_drm_fb.c
--- linux.orig/drivers/gpu/drm/rockchip/rockchip_drm_fb.c 2024-01-03 20:53:30.539323252 +0000
+++ linux/drivers/gpu/drm/rockchip/rockchip_drm_fb.c 2024-01-03 21:17:09.402615966 +0000
@@ -133,6 +133,8 @@ void rockchip_drm_mode_config_init(struc
dev->mode_config.max_width = 4096;
dev->mode_config.max_height = 4096;
+ dev->mode_config.normalize_zpos = true;
+
dev->mode_config.funcs = &rockchip_drm_mode_config_funcs;
dev->mode_config.helper_private = &rockchip_mode_config_helpers;
diff -rupN linux.orig/drivers/gpu/drm/rockchip/rockchip_drm_vop.c linux/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
--- linux.orig/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 2024-01-03 20:53:30.539323252 +0000
+++ linux/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 2024-01-03 21:17:09.402615966 +0000
@@ -10,6 +10,7 @@
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/log2.h>
+#include <linux/media-bus-format.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
@@ -281,6 +282,18 @@ static bool has_uv_swapped(uint32_t form
}
}
+static bool is_fmt_10(uint32_t format)
+{
+ switch (format) {
+ case DRM_FORMAT_NV15:
+ case DRM_FORMAT_NV20:
+ case DRM_FORMAT_NV30:
+ return true;
+ default:
+ return false;
+ }
+}
+
static enum vop_data_format vop_convert_format(uint32_t format)
{
switch (format) {
@@ -296,12 +309,15 @@ static enum vop_data_format vop_convert_
case DRM_FORMAT_BGR565:
return VOP_FMT_RGB565;
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV15:
case DRM_FORMAT_NV21:
return VOP_FMT_YUV420SP;
case DRM_FORMAT_NV16:
+ case DRM_FORMAT_NV20:
case DRM_FORMAT_NV61:
return VOP_FMT_YUV422SP;
case DRM_FORMAT_NV24:
+ case DRM_FORMAT_NV30:
case DRM_FORMAT_NV42:
return VOP_FMT_YUV444SP;
default:
@@ -333,6 +349,30 @@ static int vop_convert_afbc_format(uint3
return -EINVAL;
}
+static bool is_yuv_output(uint32_t bus_format)
+{
+ switch (bus_format) {
+ case MEDIA_BUS_FMT_YUV8_1X24:
+ case MEDIA_BUS_FMT_YUV10_1X30:
+ case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
+ case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool bus_fmt_has_uv_swapped(uint32_t bus_format)
+{
+ switch (bus_format) {
+ case MEDIA_BUS_FMT_YUV8_1X24:
+ case MEDIA_BUS_FMT_YUV10_1X30:
+ return true;
+ default:
+ return false;
+ }
+}
+
static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
uint32_t dst, bool is_horizontal,
int vsu_mode, int *vskiplines)
@@ -385,8 +425,8 @@ static void scl_vop_cal_scl_fac(struct v
if (info->is_yuv)
is_yuv = true;
- if (dst_w > 3840) {
- DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
+ if (dst_w > 4096) {
+ DRM_DEV_ERROR(vop->dev, "Maximum dst width (4096) exceeded\n");
return;
}
@@ -927,6 +967,7 @@ static void vop_plane_atomic_update(stru
int format;
int is_yuv = fb->format->is_yuv;
int i;
+ int skiplines = 0;
/*
* can't update plane when vop is disabled.
@@ -945,8 +986,14 @@ static void vop_plane_atomic_update(stru
obj = fb->obj[0];
rk_obj = to_rockchip_obj(obj);
+ /*
+ * Force skip lines when image is yuv and 3840 width,
+ * fixes a "jumping" green lines issue on RK3328.
+ */
actual_w = drm_rect_width(src) >> 16;
- actual_h = drm_rect_height(src) >> 16;
+ if (actual_w == 3840 && is_yuv)
+ skiplines = 1;
+ actual_h = drm_rect_height(src) >> (16 + skiplines);
act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
dsp_info = (drm_rect_height(dest) - 1) << 16;
@@ -956,7 +1003,12 @@ static void vop_plane_atomic_update(stru
dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
- offset = (src->x1 >> 16) * fb->format->cpp[0];
+ if (fb->format->block_w[0])
+ offset = (src->x1 >> 16) * fb->format->char_per_block[0] /
+ fb->format->block_w[0];
+ else
+ offset = (src->x1 >> 16) * fb->format->cpp[0];
+
offset += (src->y1 >> 16) * fb->pitches[0];
dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
@@ -982,7 +1034,8 @@ static void vop_plane_atomic_update(stru
}
VOP_WIN_SET(vop, win, format, format);
- VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
+ VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format));
+ VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4 >> skiplines));
VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
VOP_WIN_SET(vop, win, y_mir_en,
@@ -998,11 +1051,15 @@ static void vop_plane_atomic_update(stru
uv_obj = fb->obj[1];
rk_uv_obj = to_rockchip_obj(uv_obj);
- offset = (src->x1 >> 16) * bpp / hsub;
+ if (fb->format->block_w[1])
+ offset = (src->x1 >> 16) * bpp /
+ fb->format->block_w[1] / hsub;
+ else
+ offset = (src->x1 >> 16) * bpp / hsub;
offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
- VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
+ VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4 >> skiplines));
VOP_WIN_SET(vop, win, uv_mst, dma_addr);
for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) {
@@ -1183,6 +1240,79 @@ static void vop_crtc_disable_vblank(stru
spin_unlock_irqrestore(&vop->irq_lock, flags);
}
+static bool vop_crtc_is_tmds(struct drm_crtc *crtc)
+{
+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
+ struct drm_encoder *encoder;
+
+ switch (s->output_type) {
+ case DRM_MODE_CONNECTOR_LVDS:
+ case DRM_MODE_CONNECTOR_DSI:
+ return false;
+ case DRM_MODE_CONNECTOR_eDP:
+ case DRM_MODE_CONNECTOR_HDMIA:
+ case DRM_MODE_CONNECTOR_DisplayPort:
+ return true;
+ }
+
+ drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
+ if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
+ return true;
+
+ return false;
+}
+
+static enum drm_mode_status vop_crtc_size_valid(struct drm_crtc *crtc,
+ const struct drm_display_mode *mode)
+{
+ struct vop *vop = to_vop(crtc);
+ const struct vop_rect *max_output = &vop->data->max_output;
+
+ if (max_output->width && max_output->height) {
+ /* only the size of the resulting rect matters */
+ if(drm_mode_validate_size(mode, max_output->width,
+ max_output->height) != MODE_OK) {
+ return drm_mode_validate_size(mode, max_output->height,
+ max_output->width);
+ }
+ }
+
+ return MODE_OK;
+}
+
+/*
+ * The VESA DMT standard specifies a 0.5% pixel clock frequency tolerance.
+ * The CVT spec reuses that tolerance in its examples.
+ */
+#define CLOCK_TOLERANCE_PER_MILLE 5
+
+static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc,
+ const struct drm_display_mode *mode)
+{
+ struct vop *vop = to_vop(crtc);
+ long rounded_rate;
+ long lowest, highest;
+
+ if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+ return MODE_NO_INTERLACE;
+
+ if (vop_crtc_is_tmds(crtc)) {
+ rounded_rate = clk_round_rate(vop->dclk, mode->clock * 1000 + 999);
+ if (rounded_rate < 0)
+ return MODE_NOCLOCK;
+
+ lowest = mode->clock * (1000 - CLOCK_TOLERANCE_PER_MILLE);
+ if (rounded_rate < lowest)
+ return MODE_CLOCK_LOW;
+
+ highest = mode->clock * (1000 + CLOCK_TOLERANCE_PER_MILLE);
+ if (rounded_rate > highest)
+ return MODE_CLOCK_HIGH;
+ }
+
+ return vop_crtc_size_valid(crtc, mode);
+}
+
static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
@@ -1190,6 +1320,9 @@ static bool vop_crtc_mode_fixup(struct d
struct vop *vop = to_vop(crtc);
unsigned long rate;
+ if (vop_crtc_size_valid(crtc, adjusted_mode) != MODE_OK)
+ return false;
+
/*
* Clock craziness.
*
@@ -1356,6 +1489,7 @@ static void vop_crtc_atomic_enable(struc
u16 vact_end = vact_st + vdisplay;
uint32_t pin_pol, val;
int dither_bpc = s->output_bpc ? s->output_bpc : 10;
+ bool yuv_output = is_yuv_output(s->bus_format);
int ret;
if (old_state && old_state->self_refresh_active) {
@@ -1421,6 +1555,8 @@ static void vop_crtc_atomic_enable(struc
!(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
s->output_mode = ROCKCHIP_OUT_MODE_P888;
+ VOP_REG_SET(vop, common, dsp_data_swap, bus_fmt_has_uv_swapped(s->bus_format) ? 2 : 0);
+
if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8)
VOP_REG_SET(vop, common, pre_dither_down, 1);
else
@@ -1436,6 +1572,24 @@ static void vop_crtc_atomic_enable(struc
VOP_REG_SET(vop, common, out_mode, s->output_mode);
+ VOP_REG_SET(vop, common, dclk_ddr,
+ s->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0);
+
+ VOP_REG_SET(vop, common, overlay_mode, yuv_output);
+ VOP_REG_SET(vop, common, dsp_out_yuv, yuv_output);
+
+ /*
+ * Background color is 10bit depth if vop version >= 3.5
+ */
+ if (!yuv_output)
+ val = 0;
+ else if (VOP_MAJOR(vop_data->version) == 3 &&
+ VOP_MINOR(vop_data->version) >= 5)
+ val = 0x20010200;
+ else
+ val = 0x801080;
+ VOP_REG_SET(vop, common, dsp_background, val);
+
VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len);
val = hact_st << 16;
val |= hact_end;
@@ -1594,6 +1748,7 @@ static void vop_crtc_atomic_flush(struct
}
static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
+ .mode_valid = vop_crtc_mode_valid,
.mode_fixup = vop_crtc_mode_fixup,
.atomic_check = vop_crtc_atomic_check,
.atomic_begin = vop_crtc_atomic_begin,
@@ -1817,8 +1972,23 @@ out:
return ret;
}
-static void vop_plane_add_properties(struct drm_plane *plane,
- const struct vop_win_data *win_data)
+static bool plane_supports_yuv_format(const struct drm_plane *plane)
+{
+ const struct drm_format_info *info;
+ int i;
+
+ for (i = 0; i < plane->format_count; i++) {
+ info = drm_format_info(plane->format_types[i]);
+ if (info->is_yuv)
+ return true;
+ }
+
+ return false;
+}
+
+static void vop_plane_add_properties(struct drm_plane *plane, int zpos,
+ const struct vop_win_data *win_data,
+ const struct vop_data *vop_data)
{
unsigned int flags = 0;
@@ -1827,6 +1997,21 @@ static void vop_plane_add_properties(str
if (flags)
drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
DRM_MODE_ROTATE_0 | flags);
+
+ drm_plane_create_zpos_immutable_property(plane, zpos);
+
+ if (!plane_supports_yuv_format(plane))
+ return;
+
+ flags = BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709);
+ if (vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)
+ flags |= BIT(DRM_COLOR_YCBCR_BT2020);
+
+ drm_plane_create_color_properties(plane, flags,
+ BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
+ BIT(DRM_COLOR_YCBCR_FULL_RANGE),
+ DRM_COLOR_YCBCR_BT601,
+ DRM_COLOR_YCBCR_LIMITED_RANGE);
}
static int vop_create_crtc(struct vop *vop)
@@ -1840,19 +2025,10 @@ static int vop_create_crtc(struct vop *v
int ret;
int i;
- /*
- * Create drm_plane for primary and cursor planes first, since we need
- * to pass them to drm_crtc_init_with_planes, which sets the
- * "possible_crtcs" to the newly initialized crtc.
- */
for (i = 0; i < vop_data->win_size; i++) {
struct vop_win *vop_win = &vop->win[i];
const struct vop_win_data *win_data = vop_win->data;
- if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
- win_data->type != DRM_PLANE_TYPE_CURSOR)
- continue;
-
ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
0, &vop_plane_funcs,
win_data->phy->data_formats,
@@ -1867,7 +2043,7 @@ static int vop_create_crtc(struct vop *v
plane = &vop_win->base;
drm_plane_helper_add(plane, &plane_helper_funcs);
- vop_plane_add_properties(plane, win_data);
+ vop_plane_add_properties(plane, i, win_data, vop_data);
if (plane->type == DRM_PLANE_TYPE_PRIMARY)
primary = plane;
else if (plane->type == DRM_PLANE_TYPE_CURSOR)
@@ -1885,32 +2061,13 @@ static int vop_create_crtc(struct vop *v
drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size);
}
- /*
- * Create drm_planes for overlay windows with possible_crtcs restricted
- * to the newly created crtc.
- */
+ /* Set possible_crtcs to the newly created crtc for overlay windows */
for (i = 0; i < vop_data->win_size; i++) {
struct vop_win *vop_win = &vop->win[i];
- const struct vop_win_data *win_data = vop_win->data;
- unsigned long possible_crtcs = drm_crtc_mask(crtc);
-
- if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
- continue;
- ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
- possible_crtcs,
- &vop_plane_funcs,
- win_data->phy->data_formats,
- win_data->phy->nformats,
- win_data->phy->format_modifiers,
- win_data->type, NULL);
- if (ret) {
- DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
- ret);
- goto err_cleanup_crtc;
- }
- drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
- vop_plane_add_properties(&vop_win->base, win_data);
+ plane = &vop_win->base;
+ if (plane->type == DRM_PLANE_TYPE_OVERLAY)
+ plane->possible_crtcs = drm_crtc_mask(crtc);
}
port = of_get_child_by_name(dev->of_node, "port");
diff -rupN linux.orig/drivers/gpu/drm/rockchip/rockchip_drm_vop.h linux/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
--- linux.orig/drivers/gpu/drm/rockchip/rockchip_drm_vop.h 2024-01-03 20:53:30.539323252 +0000
+++ linux/drivers/gpu/drm/rockchip/rockchip_drm_vop.h 2024-01-03 21:17:09.402615966 +0000
@@ -119,10 +119,17 @@ struct vop_common {
struct vop_reg mmu_en;
struct vop_reg out_mode;
struct vop_reg standby;
+
+ struct vop_reg overlay_mode;
+ struct vop_reg dclk_ddr;
+ struct vop_reg dsp_data_swap;
+ struct vop_reg dsp_out_yuv;
+ struct vop_reg dsp_background;
};
struct vop_misc {
struct vop_reg global_regdone_en;
+ struct vop_reg win_channel[4];
};
struct vop_intr {
@@ -181,6 +188,7 @@ struct vop_win_phy {
struct vop_reg enable;
struct vop_reg gate;
struct vop_reg format;
+ struct vop_reg fmt_10;
struct vop_reg rb_swap;
struct vop_reg uv_swap;
struct vop_reg act_info;
@@ -213,6 +221,11 @@ struct vop_win_data {
enum drm_plane_type type;
};
+struct vop_rect {
+ int width;
+ int height;
+};
+
struct vop_data {
uint32_t version;
const struct vop_intr *intr;
@@ -225,6 +238,7 @@ struct vop_data {
const struct vop_win_data *win;
unsigned int win_size;
unsigned int lut_size;
+ struct vop_rect max_output;
#define VOP_FEATURE_OUTPUT_RGB10 BIT(0)
#define VOP_FEATURE_INTERNAL_RGB BIT(1)
@@ -273,11 +287,12 @@ struct vop_data {
/*
* display output interface supported by rockchip lcdc
*/
-#define ROCKCHIP_OUT_MODE_P888 0
-#define ROCKCHIP_OUT_MODE_P666 1
-#define ROCKCHIP_OUT_MODE_P565 2
+#define ROCKCHIP_OUT_MODE_P888 0
+#define ROCKCHIP_OUT_MODE_P666 1
+#define ROCKCHIP_OUT_MODE_P565 2
+#define ROCKCHIP_OUT_MODE_YUV420 14
/* for use special outface */
-#define ROCKCHIP_OUT_MODE_AAAA 15
+#define ROCKCHIP_OUT_MODE_AAAA 15
/* output flags */
#define ROCKCHIP_OUTPUT_DSI_DUAL BIT(0)
diff -rupN linux.orig/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h linux/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
--- linux.orig/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h 2024-01-03 20:53:30.539323252 +0000
+++ linux/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h 2024-01-03 21:17:09.398615878 +0000
@@ -27,11 +27,6 @@ enum win_dly_mode {
VOP2_DLY_MODE_MAX,
};
-struct vop_rect {
- int width;
- int height;
-};
-
enum vop2_scale_up_mode {
VOP2_SCALE_UP_NRST_NBOR,
VOP2_SCALE_UP_BIL,
diff -rupN linux.orig/drivers/gpu/drm/rockchip/rockchip_vop_reg.c linux/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
--- linux.orig/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 2024-01-03 20:53:30.539323252 +0000
+++ linux/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 2024-01-03 21:17:09.402615966 +0000
@@ -53,6 +53,23 @@ static const uint32_t formats_win_full[]
DRM_FORMAT_NV42,
};
+static const uint32_t formats_win_full_10[] = {
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_BGR888,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_BGR565,
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_NV16,
+ DRM_FORMAT_NV24,
+ DRM_FORMAT_NV15,
+ DRM_FORMAT_NV20,
+ DRM_FORMAT_NV30,
+};
+
static const uint64_t format_modifiers_win_full[] = {
DRM_FORMAT_MOD_LINEAR,
DRM_FORMAT_MOD_INVALID,
@@ -621,11 +638,12 @@ static const struct vop_scl_regs rk3288_
static const struct vop_win_phy rk3288_win01_data = {
.scl = &rk3288_win_full_scl,
- .data_formats = formats_win_full,
- .nformats = ARRAY_SIZE(formats_win_full),
+ .data_formats = formats_win_full_10,
+ .nformats = ARRAY_SIZE(formats_win_full_10),
.format_modifiers = format_modifiers_win_full,
.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
+ .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
.uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15),
.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
@@ -687,6 +705,12 @@ static const struct vop_common rk3288_co
.dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
.out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
.cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0),
+
+ .overlay_mode = VOP_REG(RK3288_SYS_CTRL, 0x1, 16),
+ .dclk_ddr = VOP_REG(RK3288_DSP_CTRL0, 0x1, 8),
+ .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12),
+ .dsp_out_yuv = VOP_REG(RK3288_POST_SCL_CTRL, 0x1, 2),
+ .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0),
};
/*
@@ -722,9 +746,23 @@ static const struct vop_intr rk3288_vop_
.clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
};
-static const struct vop_data rk3288_vop = {
+static const struct vop_data rk3288_vop_big = {
.version = VOP_VERSION(3, 1),
.feature = VOP_FEATURE_OUTPUT_RGB10,
+ .max_output = { 3840, 2160 },
+ .intr = &rk3288_vop_intr,
+ .common = &rk3288_common,
+ .modeset = &rk3288_modeset,
+ .output = &rk3288_output,
+ .win = rk3288_vop_win_data,
+ .win_size = ARRAY_SIZE(rk3288_vop_win_data),
+ .lut_size = 1024,
+};
+
+static const struct vop_data rk3288_vop_lit = {
+ .version = VOP_VERSION(3, 1),
+ .feature = VOP_FEATURE_OUTPUT_RGB10,
+ .max_output = { 2560, 1600 },
.intr = &rk3288_vop_intr,
.common = &rk3288_common,
.modeset = &rk3288_modeset,
@@ -756,11 +794,12 @@ static const struct vop_intr rk3368_vop_
static const struct vop_win_phy rk3368_win01_data = {
.scl = &rk3288_win_full_scl,
- .data_formats = formats_win_full,
- .nformats = ARRAY_SIZE(formats_win_full),
+ .data_formats = formats_win_full_10,
+ .nformats = ARRAY_SIZE(formats_win_full_10),
.format_modifiers = format_modifiers_win_full,
.enable = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 0),
.format = VOP_REG(RK3368_WIN0_CTRL0, 0x7, 1),
+ .fmt_10 = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 4),
.rb_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 12),
.uv_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 15),
.x_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 21),
@@ -826,6 +865,7 @@ static const struct vop_misc rk3368_misc
static const struct vop_data rk3368_vop = {
.version = VOP_VERSION(3, 2),
+ .max_output = { 4096, 2160 },
.intr = &rk3368_vop_intr,
.common = &rk3288_common,
.modeset = &rk3288_modeset,
@@ -847,6 +887,7 @@ static const struct vop_intr rk3366_vop_
static const struct vop_data rk3366_vop = {
.version = VOP_VERSION(3, 4),
+ .max_output = { 4096, 2160 },
.intr = &rk3366_vop_intr,
.common = &rk3288_common,
.modeset = &rk3288_modeset,
@@ -891,6 +932,11 @@ static const struct vop_common rk3399_co
.dsp_blank = VOP_REG(RK3399_DSP_CTRL0, 0x3, 18),
.out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0),
.cfg_done = VOP_REG_SYNC(RK3399_REG_CFG_DONE, 0x1, 0),
+
+ .overlay_mode = VOP_REG(RK3399_SYS_CTRL, 0x1, 16),
+ .dsp_data_swap = VOP_REG(RK3399_DSP_CTRL0, 0x1f, 12),
+ .dsp_out_yuv = VOP_REG(RK3288_POST_SCL_CTRL, 0x1, 2),
+ .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0),
};
static const struct vop_yuv2yuv_phy rk3399_yuv2yuv_win01_data = {
@@ -924,11 +970,12 @@ static const struct vop_win_yuv2yuv_data
static const struct vop_win_phy rk3399_win01_data = {
.scl = &rk3288_win_full_scl,
- .data_formats = formats_win_full,
- .nformats = ARRAY_SIZE(formats_win_full),
+ .data_formats = formats_win_full_10,
+ .nformats = ARRAY_SIZE(formats_win_full_10),
.format_modifiers = format_modifiers_win_full_afbc,
.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
+ .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
.uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15),
.x_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 21),
@@ -974,6 +1021,7 @@ static const struct vop_afbc rk3399_vop_
static const struct vop_data rk3399_vop_big = {
.version = VOP_VERSION(3, 5),
.feature = VOP_FEATURE_OUTPUT_RGB10,
+ .max_output = { 4096, 2160 },
.intr = &rk3366_vop_intr,
.common = &rk3399_common,
.modeset = &rk3288_modeset,
@@ -1001,6 +1049,7 @@ static const struct vop_win_yuv2yuv_data
static const struct vop_data rk3399_vop_lit = {
.version = VOP_VERSION(3, 6),
+ .max_output = { 2560, 1600 },
.intr = &rk3366_vop_intr,
.common = &rk3399_common,
.modeset = &rk3288_modeset,
@@ -1022,6 +1071,7 @@ static const struct vop_win_data rk3228_
static const struct vop_data rk3228_vop = {
.version = VOP_VERSION(3, 7),
.feature = VOP_FEATURE_OUTPUT_RGB10,
+ .max_output = { 4096, 2160 },
.intr = &rk3366_vop_intr,
.common = &rk3288_common,
.modeset = &rk3288_modeset,
@@ -1057,6 +1107,10 @@ static const struct vop_output rk3328_ou
static const struct vop_misc rk3328_misc = {
.global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11),
+
+ .win_channel[0] = VOP_REG(RK3328_WIN0_CTRL2, 0xff, 0),
+ .win_channel[1] = VOP_REG(RK3328_WIN1_CTRL2, 0xff, 0),
+ .win_channel[2] = VOP_REG(RK3328_WIN2_CTRL2, 0xff, 0),
};
static const struct vop_common rk3328_common = {
@@ -1069,6 +1123,12 @@ static const struct vop_common rk3328_co
.dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18),
.out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0),
.cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0),
+
+ .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16),
+ .dclk_ddr = VOP_REG(RK3328_DSP_CTRL0, 0x1, 8),
+ .dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12),
+ .dsp_out_yuv = VOP_REG(RK3328_POST_SCL_CTRL, 0x1, 2),
+ .dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0),
};
static const struct vop_intr rk3328_vop_intr = {
@@ -1093,6 +1153,7 @@ static const struct vop_win_data rk3328_
static const struct vop_data rk3328_vop = {
.version = VOP_VERSION(3, 8),
.feature = VOP_FEATURE_OUTPUT_RGB10,
+ .max_output = { 4096, 2160 },
.intr = &rk3328_vop_intr,
.common = &rk3328_common,
.modeset = &rk3328_modeset,
@@ -1115,8 +1176,10 @@ static const struct of_device_id vop_dri
.data = &rk3066_vop },
{ .compatible = "rockchip,rk3188-vop",
.data = &rk3188_vop },
- { .compatible = "rockchip,rk3288-vop",
- .data = &rk3288_vop },
+ { .compatible = "rockchip,rk3288-vop-big",
+ .data = &rk3288_vop_big },
+ { .compatible = "rockchip,rk3288-vop-lit",
+ .data = &rk3288_vop_lit },
{ .compatible = "rockchip,rk3368-vop",
.data = &rk3368_vop },
{ .compatible = "rockchip,rk3366-vop",
diff -rupN linux.orig/drivers/media/cec/core/cec-adap.c linux/drivers/media/cec/core/cec-adap.c
--- linux.orig/drivers/media/cec/core/cec-adap.c 2024-01-03 20:53:30.727325791 +0000
+++ linux/drivers/media/cec/core/cec-adap.c 2024-01-03 21:17:09.402615966 +0000
@@ -1679,8 +1679,15 @@ void cec_s_phys_addr(struct cec_adapter
if (IS_ERR_OR_NULL(adap))
return;
+ cancel_delayed_work_sync(&adap->debounce_work);
+
mutex_lock(&adap->lock);
- __cec_s_phys_addr(adap, phys_addr, block);
+ if (cec_debounce_ms > 0 && !block && phys_addr == CEC_PHYS_ADDR_INVALID &&
+ adap->phys_addr != phys_addr)
+ schedule_delayed_work(&adap->debounce_work,
+ msecs_to_jiffies(cec_debounce_ms));
+ else
+ __cec_s_phys_addr(adap, phys_addr, block);
mutex_unlock(&adap->lock);
}
EXPORT_SYMBOL_GPL(cec_s_phys_addr);
diff -rupN linux.orig/drivers/media/cec/core/cec-core.c linux/drivers/media/cec/core/cec-core.c
--- linux.orig/drivers/media/cec/core/cec-core.c 2024-01-03 20:53:30.727325791 +0000
+++ linux/drivers/media/cec/core/cec-core.c 2024-01-03 21:17:09.402615966 +0000
@@ -40,6 +40,10 @@ static bool debug_phys_addr;
module_param(debug_phys_addr, bool, 0644);
MODULE_PARM_DESC(debug_phys_addr, "add CEC_CAP_PHYS_ADDR if set");
+int cec_debounce_ms;
+module_param_named(debounce_ms, cec_debounce_ms, int, 0644);
+MODULE_PARM_DESC(debounce_ms, "debounce invalid phys addr");
+
static dev_t cec_dev_t;
/* Active devices */
@@ -188,6 +192,8 @@ static void cec_devnode_unregister(struc
mutex_unlock(&devnode->lock);
+ cancel_delayed_work_sync(&adap->debounce_work);
+
mutex_lock(&adap->lock);
__cec_s_phys_addr(adap, CEC_PHYS_ADDR_INVALID, false);
__cec_s_log_addrs(adap, NULL, false);
@@ -248,6 +254,17 @@ static const struct file_operations cec_
};
#endif
+static void cec_s_phys_addr_debounce(struct work_struct *work)
+{
+ struct delayed_work *delayed_work = to_delayed_work(work);
+ struct cec_adapter *adap =
+ container_of(delayed_work, struct cec_adapter, debounce_work);
+
+ mutex_lock(&adap->lock);
+ __cec_s_phys_addr(adap, CEC_PHYS_ADDR_INVALID, false);
+ mutex_unlock(&adap->lock);
+}
+
struct cec_adapter *cec_allocate_adapter(const struct cec_adap_ops *ops,
void *priv, const char *name, u32 caps,
u8 available_las)
@@ -285,6 +302,7 @@ struct cec_adapter *cec_allocate_adapter
INIT_LIST_HEAD(&adap->transmit_queue);
INIT_LIST_HEAD(&adap->wait_queue);
init_waitqueue_head(&adap->kthread_waitq);
+ INIT_DELAYED_WORK(&adap->debounce_work, cec_s_phys_addr_debounce);
/* adap->devnode initialization */
INIT_LIST_HEAD(&adap->devnode.fhs);
diff -rupN linux.orig/drivers/media/cec/core/cec-priv.h linux/drivers/media/cec/core/cec-priv.h
--- linux.orig/drivers/media/cec/core/cec-priv.h 2024-01-03 20:53:30.727325791 +0000
+++ linux/drivers/media/cec/core/cec-priv.h 2024-01-03 21:17:09.402615966 +0000
@@ -37,6 +37,7 @@ static inline bool msg_is_raw(const stru
/* cec-core.c */
extern int cec_debug;
+extern int cec_debounce_ms;
int cec_get_device(struct cec_devnode *devnode);
void cec_put_device(struct cec_devnode *devnode);
diff -rupN linux.orig/drivers/media/platform/rockchip/Kconfig linux/drivers/media/platform/rockchip/Kconfig
--- linux.orig/drivers/media/platform/rockchip/Kconfig 2024-01-03 20:53:30.799326767 +0000
+++ linux/drivers/media/platform/rockchip/Kconfig 2024-01-03 21:28:43.674043912 +0000
@@ -2,5 +2,6 @@
comment "Rockchip media platform drivers"
+source "drivers/media/platform/rockchip/iep/Kconfig"
source "drivers/media/platform/rockchip/rga/Kconfig"
source "drivers/media/platform/rockchip/rkisp1/Kconfig"
diff -rupN linux.orig/drivers/media/platform/rockchip/Makefile linux/drivers/media/platform/rockchip/Makefile
--- linux.orig/drivers/media/platform/rockchip/Makefile 2024-01-03 20:53:30.799326767 +0000
+++ linux/drivers/media/platform/rockchip/Makefile 2024-01-03 21:28:43.674043912 +0000
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
+obj-y += iep/
obj-y += rga/
obj-y += rkisp1/
diff -rupN linux.orig/drivers/media/platform/rockchip/iep/Kconfig linux/drivers/media/platform/rockchip/iep/Kconfig
--- linux.orig/drivers/media/platform/rockchip/iep/Kconfig 1970-01-01 00:00:00.000000000 +0000
+++ linux/drivers/media/platform/rockchip/iep/Kconfig 2024-01-03 21:28:43.674043912 +0000
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config VIDEO_ROCKCHIP_IEP
+ tristate "Rockchip Image Enhancement Processor"
+ depends on V4L_MEM2MEM_DRIVERS
+ depends on VIDEO_DEV
+ depends on ARCH_ROCKCHIP || COMPILE_TEST
+ select VIDEOBUF2_DMA_CONTIG
+ select V4L2_MEM2MEM_DEV
+ help
+ This is a v4l2 driver for Rockchip Image Enhancement Processor (IEP)
+ found in most Rockchip RK3xxx SoCs.
+ Rockchip IEP supports various enhancement operations for RGB and YUV
+ images. The driver currently implements YUV deinterlacing only.
+ To compile this driver as a module, choose M here: the module
+ will be called rockchip-iep
diff -rupN linux.orig/drivers/media/platform/rockchip/iep/Makefile linux/drivers/media/platform/rockchip/iep/Makefile
--- linux.orig/drivers/media/platform/rockchip/iep/Makefile 1970-01-01 00:00:00.000000000 +0000
+++ linux/drivers/media/platform/rockchip/iep/Makefile 2024-01-03 21:28:43.674043912 +0000
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+rockchip-iep-objs := iep.o
+
+obj-$(CONFIG_VIDEO_ROCKCHIP_IEP) += rockchip-iep.o
diff -rupN linux.orig/drivers/media/platform/rockchip/iep/iep-regs.h linux/drivers/media/platform/rockchip/iep/iep-regs.h
--- linux.orig/drivers/media/platform/rockchip/iep/iep-regs.h 1970-01-01 00:00:00.000000000 +0000
+++ linux/drivers/media/platform/rockchip/iep/iep-regs.h 2024-01-03 21:28:43.674043912 +0000
@@ -0,0 +1,291 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Rockchip Image Enhancement Processor (IEP) driver
+ *
+ * Copyright (C) 2020 Alex Bee <knaerzche@gmail.com>
+ *
+ */
+
+#ifndef __IEP_REGS_H__
+#define __IEP_REGS_H__
+
+/* IEP Registers addresses */
+#define IEP_CONFIG0 0x000 /* Configuration register0 */
+#define IEP_VOP_DIRECT_PATH BIT(0)
+#define IEP_DEIN_HIGH_FREQ_SHFT 1
+#define IEP_DEIN_HIGH_FREQ_MASK (0x7f << IEP_DEIN_HIGH_FREQ_SHFT)
+#define IEP_DEIN_MODE_SHFT 8
+#define IEP_DEIN_MODE_MASK (7 << IEP_DEIN_MODE_SHFT)
+#define IEP_DEIN_HIGH_FREQ_EN BIT(11)
+#define IEP_DEIN_EDGE_INTPOL_EN BIT(12)
+#define IEP_YUV_DENOISE_EN BIT(13)
+#define IEP_YUV_ENHNC_EN BIT(14)
+#define IEP_DEIN_EDGE_INTPOL_SMTH_EN BIT(15)
+#define IEP_RGB_CLR_ENHNC_EN BIT(16)
+#define IEP_RGB_CNTRST_ENHNC_EN BIT(17)
+#define IEP_RGB_ENHNC_MODE_BYPASS (0 << 18)
+#define IEP_RGB_ENHNC_MODE_DNS BIT(18)
+#define IEP_RGB_ENHNC_MODE_DTL (2 << 18)
+#define IEP_RGB_ENHNC_MODE_EDG (3 << 18)
+#define IEP_RGB_ENHNC_MODE_MASK (3 << 18)
+#define IEP_RGB_CNTRST_ENHNC_DDE_FRST BIT(20)
+#define IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT 21
+#define IEP_DEIN_EDGE_INTPOL_RADIUS_MASK (3 << IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT)
+#define IEP_DEIN_EDGE_INTPOL_SELECT BIT(23)
+
+#define IEP_CONFIG1 0x004 /* Configuration register1 */
+#define IEP_SRC_FMT_SHFT 0
+#define IEP_SRC_FMT_MASK (3 << IEP_SRC_FMT_SHFT)
+#define IEP_SRC_RGB_SWP_SHFT 2
+#define IEP_SRC_RGB_SWP_MASK (2 << IEP_SRC_RGB_SWP_SHFT)
+#define IEP_SRC_YUV_SWP_SHFT 4
+#define IEP_SRC_YUV_SWP_MASK (3 << IEP_SRC_YUV_SWP_SHFT)
+#define IEP_DST_FMT_SHFT 8
+#define IEP_DST_FMT_MASK (3 << IEP_DST_FMT_SHFT)
+#define IEP_DST_RGB_SWP_SHFT 10
+#define IEP_DST_RGB_SWP_MASK (2 << IEP_DST_RGB_SWP_SHFT)
+#define IEP_DST_YUV_SWP_SHFT 12
+#define IEP_DST_YUV_SWP_MASK (3 << IEP_DST_YUV_SWP_SHFT)
+#define IEP_DTH_UP_EN BIT(14)
+#define IEP_DTH_DWN_EN BIT(15)
+#define IEP_YUV2RGB_COE_BT601_1 (0 << 16)
+#define IEP_YUV2RGB_COE_BT601_F BIT(16)
+#define IEP_YUV2RGB_COE_BT709_1 (2 << 16)
+#define IEP_YUV2RGB_COE_BT709_F (3 << 16)
+#define IEP_YUV2RGB_COE_MASK (3 << 16)
+#define IEP_RGB2YUV_COE_BT601_1 (0 << 18)
+#define IEP_RGB2YUV_COE_BT601_F BIT(18)
+#define IEP_RGB2YUV_COE_BT709_1 (2 << 18)
+#define IEP_RGB2YUV_COE_BT709_F (3 << 18)
+#define IEP_RGB2YUV_COE_MASK (3 << 18)
+#define IEP_YUV2RGB_EN BIT(20)
+#define IEP_RGB2YUV_EN BIT(21)
+#define IEP_YUV2RGB_CLIP_EN BIT(22)
+#define IEP_RGB2YUV_CLIP_EN BIT(23)
+#define IEP_GLB_ALPHA_SHFT 24
+#define IEP_GLB_ALPHA_MASK (0x7f << IEP_GLB_ALPHA_SHFT)
+
+#define IEP_STATUS 0x008 /* Status register */
+#define IEP_STATUS_YUV_DNS BIT(0)
+#define IEP_STATUS_SCL BIT(1)
+#define IEP_STATUS_DIL BIT(2)
+#define IEP_STATUS_DDE BIT(3)
+#define IEP_STATUS_DMA_WR_YUV BIT(4)
+#define IEP_STATUS_DMA_RE_YUV BIT(5)
+#define IEP_STATUS_DMA_WR_RGB BIT(6)
+#define IEP_STATUS_DMA_RE_RGB BIT(7)
+#define IEP_STATUS_VOP_DIRECT_PATH BIT(8)
+#define IEP_STATUS_DMA_IA_WR_YUV BIT(16)
+#define IEP_STATUS_DMA_IA_RE_YUV BIT(17)
+#define IEP_STATUS_DMA_IA_WR_RGB BIT(18)
+#define IEP_STATUS_DMA_IA_RE_RGB BIT(19)
+
+#define IEP_INT 0x00c /* Interrupt register*/
+#define IEP_INT_FRAME_DONE BIT(0) /* Frame process done interrupt */
+#define IEP_INT_FRAME_DONE_EN BIT(8) /* Frame process done interrupt enable */
+#define IEP_INT_FRAME_DONE_CLR BIT(16) /* Frame process done interrupt clear */
+
+#define IEP_FRM_START 0x010 /* Frame start */
+#define IEP_SRST 0x014 /* Soft reset */
+#define IEP_CONFIG_DONE 0x018 /* Configuration done */
+#define IEP_FRM_CNT 0x01c /* Frame counter */
+
+#define IEP_VIR_IMG_WIDTH 0x020 /* Image virtual width */
+#define IEP_IMG_SCL_FCT 0x024 /* Scaling factor */
+#define IEP_SRC_IMG_SIZE 0x028 /* src image width/height */
+#define IEP_DST_IMG_SIZE 0x02c /* dst image width/height */
+#define IEP_DST_IMG_WIDTH_TILE0 0x030 /* dst image tile0 width */
+#define IEP_DST_IMG_WIDTH_TILE1 0x034 /* dst image tile1 width */
+#define IEP_DST_IMG_WIDTH_TILE2 0x038 /* dst image tile2 width */
+#define IEP_DST_IMG_WIDTH_TILE3 0x03c /* dst image tile3 width */
+
+#define IEP_ENH_YUV_CNFG_0 0x040 /* Brightness, contrast, saturation adjustment */
+#define IEP_YUV_BRIGHTNESS_SHFT 0
+#define IEP_YUV_BRIGHTNESS_MASK (0x3f << IEP_YUV_BRIGHTNESS_SHFT)
+#define IEP_YUV_CONTRAST_SHFT 8
+#define IEP_YUV_CONTRAST_MASK (0xff << IEP_YUV_CONTRAST_SHFT)
+#define IEP_YUV_SATURATION_SHFT 16
+#define IEP_YUV_SATURATION_MASK (0x1ff << IEP_YUV_SATURATION_SHFT)
+
+#define IEP_ENH_YUV_CNFG_1 0x044 /* Hue configuration */
+#define IEP_YUV_COS_HUE_SHFT 0
+#define IEP_YUV_COS_HUE_MASK (0xff << IEP_YUV_COS_HUE_SHFT)
+#define IEP_YUV_SIN_HUE_SHFT 8
+#define IEP_YUV_SIN_HUE_MASK (0xff << IEP_YUV_SIN_HUE_SHFT)
+
+#define IEP_ENH_YUV_CNFG_2 0x048 /* Color bar configuration */
+#define IEP_YUV_COLOR_BAR_Y_SHFT 0
+#define IEP_YUV_COLOR_BAR_Y_MASK (0xff << IEP_YUV_COLOR_BAR_Y_SHFT)
+#define IEP_YUV_COLOR_BAR_U_SHFT 8
+#define IEP_YUV_COLOR_BAR_U_MASK (0xff << IEP_YUV_COLOR_BAR_U_SHFT)
+#define IEP_YUV_COLOR_BAR_V_SHFT 16
+#define IEP_YUV_COLOR_BAR_V_MASK (0xff << IEP_YUV_COLOR_BAR_V_SHFT)
+#define IEP_YUV_VIDEO_MODE_SHFT 24
+#define IEP_YUV_VIDEO_MODE_MASK (3 << IEP_YUV_VIDEO_MODE_SHFT)
+
+#define IEP_ENH_RGB_CNFG 0x04c /* RGB enhancement configuration */
+#define IEP_ENH_RGB_C_COE 0x050 /* RGB color enhancement coefficient */
+
+#define IEP_RAW_CONFIG0 0x058 /* Raw configuration register0 */
+#define IEP_RAW_CONFIG1 0x05c /* Raw configuration register1 */
+#define IEP_RAW_VIR_IMG_WIDTH 0x060 /* Raw image virtual width */
+#define IEP_RAW_IMG_SCL_FCT 0x064 /* Raw scaling factor */
+#define IEP_RAW_SRC_IMG_SIZE 0x068 /* Raw src image width/height */
+#define IEP_RAW_DST_IMG_SIZE 0x06c /* Raw src image width/height */
+#define IEP_RAW_ENH_YUV_CNFG_0 0x070 /* Raw brightness,contrast,saturation adjustment */
+#define IEP_RAW_ENH_YUV_CNFG_1 0x074 /* Raw hue configuration */
+#define IEP_RAW_ENH_YUV_CNFG_2 0x078 /* Raw color bar configuration */
+#define IEP_RAW_ENH_RGB_CNFG 0x07c /* Raw RGB enhancement configuration */
+
+#define IEP_SRC_ADDR_Y_RGB 0x080 /* Start addr. of src image 0 (Y/RGB) */
+#define IEP_SRC_ADDR_CBCR 0x084 /* Start addr. of src image 0 (Cb/Cr) */
+#define IEP_SRC_ADDR_CR 0x088 /* Start addr. of src image 0 (Cr) */
+#define IEP_SRC_ADDR_Y1 0x08c /* Start addr. of src image 1 (Y) */
+#define IEP_SRC_ADDR_CBCR1 0x090 /* Start addr. of src image 1 (Cb/Cr) */
+#define IEP_SRC_ADDR_CR1 0x094 /* Start addr. of src image 1 (Cr) */
+#define IEP_SRC_ADDR_Y_ITEMP 0x098 /* Start addr. of src image(Y int part) */
+#define IEP_SRC_ADDR_CBCR_ITEMP 0x09c /* Start addr. of src image(CBCR int part) */
+#define IEP_SRC_ADDR_CR_ITEMP 0x0a0 /* Start addr. of src image(CR int part) */
+#define IEP_SRC_ADDR_Y_FTEMP 0x0a4 /* Start addr. of src image(Y frac part) */
+#define IEP_SRC_ADDR_CBCR_FTEMP 0x0a8 /* Start addr. of src image(CBCR frac part) */
+#define IEP_SRC_ADDR_CR_FTEMP 0x0ac /* Start addr. of src image(CR frac part) */
+
+#define IEP_DST_ADDR_Y_RGB 0x0b0 /* Start addr. of dst image 0 (Y/RGB) */
+#define IEP_DST_ADDR_CBCR 0x0b4 /* Start addr. of dst image 0 (Cb/Cr) */
+#define IEP_DST_ADDR_CR 0x0b8 /* Start addr. of dst image 0 (Cr) */
+#define IEP_DST_ADDR_Y1 0x0bc /* Start addr. of dst image 1 (Y) */
+#define IEP_DST_ADDR_CBCR1 0x0c0 /* Start addr. of dst image 1 (Cb/Cr) */
+#define IEP_DST_ADDR_CR1 0x0c4 /* Start addr. of dst image 1 (Cr) */
+#define IEP_DST_ADDR_Y_ITEMP 0x0c8 /* Start addr. of dst image(Y int part) */
+#define IEP_DST_ADDR_CBCR_ITEMP 0x0cc /* Start addr. of dst image(CBCR int part)*/
+#define IEP_DST_ADDR_CR_ITEMP 0x0d0 /* Start addr. of dst image(CR int part) */
+#define IEP_DST_ADDR_Y_FTEMP 0x0d4 /* Start addr. of dst image(Y frac part) */
+#define IEP_DST_ADDR_CBCR_FTEMP 0x0d8 /* Start addr. of dst image(CBCR frac part) */
+#define IEP_DST_ADDR_CR_FTEMP 0x0dc /* Start addr. of dst image(CR frac part)*/
+
+#define IEP_DEIN_MTN_TAB0 0x0e0 /* Deinterlace motion table0 */
+#define IEP_DEIN_MTN_TAB1 0x0e4 /* Deinterlace motion table1 */
+#define IEP_DEIN_MTN_TAB2 0x0e8 /* Deinterlace motion table2 */
+#define IEP_DEIN_MTN_TAB3 0x0ec /* Deinterlace motion table3 */
+#define IEP_DEIN_MTN_TAB4 0x0f0 /* Deinterlace motion table4 */
+#define IEP_DEIN_MTN_TAB5 0x0f4 /* Deinterlace motion table5 */
+#define IEP_DEIN_MTN_TAB6 0x0f8 /* Deinterlace motion table6 */
+#define IEP_DEIN_MTN_TAB7 0x0fc /* Deinterlace motion table7 */
+
+#define IEP_ENH_CG_TAB 0x100 /* Contrast and gamma enhancement table */
+#define IEP_ENH_DDE_COE0 0x400 /* Denoise,detail and edge enhancement coefficient */
+#define IEP_ENH_DDE_COE1 0x500 /* Denoise,detail and edge enhancement coefficient1 */
+
+#define IEP_INT_MASK (IEP_INT_FRAME_DONE)
+
+/* IEP colorformats */
+#define IEP_COLOR_FMT_XRGB 0U
+#define IEP_COLOR_FMT_RGB565 1U
+#define IEP_COLOR_FMT_YUV422 2U
+#define IEP_COLOR_FMT_YUV420 3U
+
+/* IEP YUV color swaps */
+#define IEP_YUV_SWP_SP_UV 0U
+#define IEP_YUV_SWP_SP_VU 1U
+#define IEP_YUV_SWP_P 2U
+
+/* IEP XRGB color swaps */
+#define XRGB_SWP_XRGB 0U
+#define XRGB_SWP_XBGR 1U
+#define XRGB_SWP_BGRX 2U
+
+/* IEP RGB565 color swaps */
+#define RGB565_SWP_RGB 0U
+#define RGB565_SWP_BGR 1U
+
+#define FMT_IS_YUV(fmt) (fmt == IEP_COLOR_FMT_XRGB || fmt == IEP_COLOR_FMT_RGB565 ? 0 : 1)
+
+#define IEP_IMG_SIZE(w, h) (((w - 1) & 0x1fff) << 0 | \
+ ((h - 1) & 0x1fff) << 16)
+
+#define IEP_VIR_WIDTH(src_w, dst_w) (((src_w / 4) & 0x1fff) << 0 | \
+ ((dst_w / 4) & 0x1fff) << 16)
+
+#define IEP_Y_STRIDE(w, h) (w * h)
+#define IEP_UV_STRIDE(w, h, fac) (w * h + w * h / fac)
+
+#define IEP_SRC_FMT_SWP_MASK(f) (FMT_IS_YUV(f) ? IEP_SRC_YUV_SWP_MASK : IEP_SRC_RGB_SWP_MASK)
+#define IEP_DST_FMT_SWP_MASK(f) (FMT_IS_YUV(f) ? IEP_DST_YUV_SWP_MASK : IEP_DST_RGB_SWP_MASK)
+
+#define IEP_SRC_FMT(f, swp) (f << IEP_SRC_FMT_SHFT | \
+ (swp << (FMT_IS_YUV(f) ? IEP_SRC_YUV_SWP_SHFT : IEP_SRC_RGB_SWP_SHFT)))
+#define IEP_DST_FMT(f, swp) (f << IEP_DST_FMT_SHFT | \
+ (swp << (FMT_IS_YUV(f) ? IEP_DST_YUV_SWP_SHFT : IEP_DST_RGB_SWP_SHFT)))
+
+/* IEP DEINTERLACE MODES */
+#define IEP_DEIN_MODE_YUV 0U
+#define IEP_DEIN_MODE_I4O2 1U
+#define IEP_DEIN_MODE_I4O1B 2U
+#define IEP_DEIN_MODE_I4O1T 3U
+#define IEP_DEIN_MODE_I2O1B 4U
+#define IEP_DEIN_MODE_I2O1T 5U
+#define IEP_DEIN_MODE_BYPASS 6U
+
+#define IEP_DEIN_IN_FIELDS_2 2U
+#define IEP_DEIN_IN_FIELDS_4 4U
+
+#define IEP_DEIN_OUT_FRAMES_1 1U
+#define IEP_DEIN_OUT_FRAMES_2 2U
+
+/* values taken from BSP driver */
+static const u32 default_dein_motion_tbl[][2] = {
+ { IEP_DEIN_MTN_TAB0, 0x40404040 },
+ { IEP_DEIN_MTN_TAB1, 0x3c3e3f3f },
+ { IEP_DEIN_MTN_TAB2, 0x3336393b },
+ { IEP_DEIN_MTN_TAB3, 0x272a2d31 },
+ { IEP_DEIN_MTN_TAB4, 0x181c2023 },
+ { IEP_DEIN_MTN_TAB5, 0x0c0e1215 },
+ { IEP_DEIN_MTN_TAB6, 0x03040609 },
+ { IEP_DEIN_MTN_TAB7, 0x00000001 },
+
+};
+
+#define IEP_DEIN_IN_IMG0_Y(bff) (bff ? IEP_SRC_ADDR_Y_RGB : IEP_SRC_ADDR_Y1)
+#define IEP_DEIN_IN_IMG0_CBCR(bff) (bff ? IEP_SRC_ADDR_CBCR : IEP_SRC_ADDR_CBCR1)
+#define IEP_DEIN_IN_IMG0_CR(bff) (bff ? IEP_SRC_ADDR_CR : IEP_SRC_ADDR_CR1)
+#define IEP_DEIN_IN_IMG1_Y(bff) (IEP_DEIN_IN_IMG0_Y(!bff))
+#define IEP_DEIN_IN_IMG1_CBCR(bff) (IEP_DEIN_IN_IMG0_CBCR(!bff))
+#define IEP_DEIN_IN_IMG1_CR(bff) (IEP_DEIN_IN_IMG0_CR(!bff))
+
+#define IEP_DEIN_OUT_IMG0_Y(bff) (bff ? IEP_DST_ADDR_Y1 : IEP_DST_ADDR_Y_RGB)
+#define IEP_DEIN_OUT_IMG0_CBCR(bff) (bff ? IEP_DST_ADDR_CBCR1 : IEP_DST_ADDR_CBCR)
+#define IEP_DEIN_OUT_IMG0_CR(bff) (bff ? IEP_DST_ADDR_CR1 : IEP_DST_ADDR_CR)
+#define IEP_DEIN_OUT_IMG1_Y(bff) (IEP_DEIN_OUT_IMG0_Y(!bff))
+#define IEP_DEIN_OUT_IMG1_CBCR(bff) (IEP_DEIN_OUT_IMG0_CBCR(!bff))
+#define IEP_DEIN_OUT_IMG1_CR(bff) (IEP_DEIN_OUT_IMG0_CR(!bff))
+
+#define IEP_DEIN_MODE(m) (m << IEP_DEIN_MODE_SHFT)
+
+#define IEP_DEIN_IN_MODE_FIELDS(m) ((m == IEP_DEIN_MODE_I4O1T || m == IEP_DEIN_MODE_I4O1B \
+ || m == IEP_DEIN_MODE_I4O2) \
+ ? IEP_DEIN_IN_FIELDS_4 : IEP_DEIN_IN_FIELDS_2)
+
+#define IEP_DEIN_OUT_MODE_FRAMES(m) (m == IEP_DEIN_MODE_I4O2 \
+ ? IEP_DEIN_OUT_FRAMES_2 : IEP_DEIN_OUT_FRAMES_1)
+
+#define IEP_DEIN_OUT_MODE_1FRM_TOP_FIELD(m) (m == IEP_DEIN_MODE_I4O1T || IEP_DEIN_MODE_I2O1T \
+ ? 1 : 0)
+
+#define IEP_DEIN_EDGE_INTPOL_RADIUS(r) (r << IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT)
+
+#define IEP_DEIN_HIGH_FREQ(f) (f << IEP_DEIN_HIGH_FREQ_SHFT)
+
+/* YUV Enhance video modes */
+#define VIDEO_MODE_BLACK_SCREEN 0U
+#define VIDEO_MODE_BLUE_SCREEN 1U
+#define VIDEO_MODE_COLOR_BARS 2U
+#define VIDEO_MODE_NORMAL_VIDEO 3U
+
+#define YUV_VIDEO_MODE(m) ((m << IEP_YUV_VIDEO_MODE_SHFT) & IEP_YUV_VIDEO_MODE_MASK)
+#define YUV_BRIGHTNESS(v) ((v << IEP_YUV_BRIGHTNESS_SHFT) & IEP_YUV_BRIGHTNESS_MASK)
+#define YUV_CONTRAST(v) ((v << IEP_YUV_CONTRAST_SHFT) & IEP_YUV_CONTRAST_MASK)
+#define YUV_SATURATION(v) ((v << IEP_YUV_SATURATION_SHFT) & IEP_YUV_SATURATION_MASK)
+#define YUV_COS_HUE(v) ((v << IEP_YUV_COS_HUE_SHFT) & IEP_YUV_COS_HUE_MASK)
+#define YUV_SIN_HUE(v) ((v << IEP_YUV_SIN_HUE_SHFT) & IEP_YUV_SIN_HUE_MASK)
+
+#endif
diff -rupN linux.orig/drivers/media/platform/rockchip/iep/iep.c linux/drivers/media/platform/rockchip/iep/iep.c
--- linux.orig/drivers/media/platform/rockchip/iep/iep.c 1970-01-01 00:00:00.000000000 +0000
+++ linux/drivers/media/platform/rockchip/iep/iep.c 2024-01-03 21:28:43.674043912 +0000
@@ -0,0 +1,1089 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Rockchip Image Enhancement Processor (IEP) driver
+ *
+ * Copyright (C) 2020 Alex Bee <knaerzche@gmail.com>
+ *
+ * Based on Allwinner sun8i deinterlacer with scaler driver
+ * Copyright (C) 2019 Jernej Skrabec <jernej.skrabec@siol.net>
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#include <media/v4l2-device.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-mem2mem.h>
+#include <media/videobuf2-v4l2.h>
+#include <media/videobuf2-core.h>
+#include <media/videobuf2-dma-contig.h>
+#include <linux/videodev2.h>
+
+#include "iep-regs.h"
+#include "iep.h"
+
+static struct iep_fmt formats[] = {
+ {
+ .fourcc = V4L2_PIX_FMT_NV12,
+ .color_swap = IEP_YUV_SWP_SP_UV,
+ .hw_format = IEP_COLOR_FMT_YUV420,
+ .depth = 12,
+ .uv_factor = 4,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_NV21,
+ .color_swap = IEP_YUV_SWP_SP_VU,
+ .hw_format = IEP_COLOR_FMT_YUV420,
+ .depth = 12,
+ .uv_factor = 4,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_NV16,
+ .color_swap = IEP_YUV_SWP_SP_UV,
+ .hw_format = IEP_COLOR_FMT_YUV422,
+ .depth = 16,
+ .uv_factor = 2,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_NV61,
+ .color_swap = IEP_YUV_SWP_SP_VU,
+ .hw_format = IEP_COLOR_FMT_YUV422,
+ .depth = 16,
+ .uv_factor = 2,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_YUV420,
+ .color_swap = IEP_YUV_SWP_P,
+ .hw_format = IEP_COLOR_FMT_YUV420,
+ .depth = 12,
+ .uv_factor = 4,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_YUV422P,
+ .color_swap = IEP_YUV_SWP_P,
+ .hw_format = IEP_COLOR_FMT_YUV422,
+ .depth = 16,
+ .uv_factor = 2,
+ },
+};
+
+static struct iep_fmt *iep_fmt_find(struct v4l2_pix_format *pix_fmt)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(formats); i++) {
+ if (formats[i].fourcc == pix_fmt->pixelformat)
+ return &formats[i];
+ }
+
+ return NULL;
+}
+
+static bool iep_check_pix_format(u32 pixelformat)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(formats); i++)
+ if (formats[i].fourcc == pixelformat)
+ return true;
+
+ return false;
+}
+
+static struct vb2_v4l2_buffer *iep_m2m_next_dst_buf(struct iep_ctx *ctx)
+{
+ struct vb2_v4l2_buffer *dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
+
+ /* application has set a dst sequence: take it as start point */
+ if (ctx->dst_sequence == 0 && dst_buf->sequence > 0)
+ ctx->dst_sequence = dst_buf->sequence;
+
+ dst_buf->sequence = ctx->dst_sequence++;
+
+ return dst_buf;
+}
+
+static void iep_m2m_dst_bufs_done(struct iep_ctx *ctx, enum vb2_buffer_state state)
+{
+ if (ctx->dst0_buf) {
+ v4l2_m2m_buf_done(ctx->dst0_buf, state);
+ ctx->dst_buffs_done++;
+ ctx->dst0_buf = NULL;
+ }
+
+ if (ctx->dst1_buf) {
+ v4l2_m2m_buf_done(ctx->dst1_buf, state);
+ ctx->dst_buffs_done++;
+ ctx->dst1_buf = NULL;
+ }
+}
+
+static void iep_setup_formats(struct iep_ctx *ctx)
+{
+ /* setup src dimensions */
+ iep_write(ctx->iep, IEP_SRC_IMG_SIZE,
+ IEP_IMG_SIZE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height));
+
+ /* setup dst dimensions */
+ iep_write(ctx->iep, IEP_DST_IMG_SIZE,
+ IEP_IMG_SIZE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height));
+
+ /* setup virtual width */
+ iep_write(ctx->iep, IEP_VIR_IMG_WIDTH,
+ IEP_VIR_WIDTH(ctx->src_fmt.pix.width, ctx->dst_fmt.pix.width));
+
+ /* setup src format */
+ iep_shadow_mod(ctx->iep, IEP_CONFIG1, IEP_RAW_CONFIG1,
+ IEP_SRC_FMT_MASK | IEP_SRC_FMT_SWP_MASK(ctx->src_fmt.hw_fmt->hw_format),
+ IEP_SRC_FMT(ctx->src_fmt.hw_fmt->hw_format,
+ ctx->src_fmt.hw_fmt->color_swap));
+ /* setup dst format */
+ iep_shadow_mod(ctx->iep, IEP_CONFIG1, IEP_RAW_CONFIG1,
+ IEP_DST_FMT_MASK | IEP_DST_FMT_SWP_MASK(ctx->dst_fmt.hw_fmt->hw_format),
+ IEP_DST_FMT(ctx->dst_fmt.hw_fmt->hw_format,
+ ctx->dst_fmt.hw_fmt->color_swap));
+
+ ctx->fmt_changed = false;
+}
+
+static void iep_dein_init(struct rockchip_iep *iep)
+{
+ unsigned int i;
+
+ /* values taken from BSP driver */
+ iep_shadow_mod(iep, IEP_CONFIG0, IEP_RAW_CONFIG0,
+ (IEP_DEIN_EDGE_INTPOL_SMTH_EN |
+ IEP_DEIN_EDGE_INTPOL_RADIUS_MASK |
+ IEP_DEIN_HIGH_FREQ_EN |
+ IEP_DEIN_HIGH_FREQ_MASK),
+ (IEP_DEIN_EDGE_INTPOL_SMTH_EN |
+ IEP_DEIN_EDGE_INTPOL_RADIUS(3) |
+ IEP_DEIN_HIGH_FREQ_EN |
+ IEP_DEIN_HIGH_FREQ(64)));
+
+ for (i = 0; i < ARRAY_SIZE(default_dein_motion_tbl); i++)
+ iep_write(iep, default_dein_motion_tbl[i][0],
+ default_dein_motion_tbl[i][1]);
+}
+
+static void iep_init(struct rockchip_iep *iep)
+{
+ iep_write(iep, IEP_CONFIG0,
+ IEP_DEIN_MODE(IEP_DEIN_MODE_BYPASS) // |
+ //IEP_YUV_ENHNC_EN
+ );
+
+ /* TODO: B/S/C/H works
+ * only in 1-frame-out modes
+ iep_write(iep, IEP_ENH_YUV_CNFG_0,
+ YUV_BRIGHTNESS(0) |
+ YUV_CONTRAST(128) |
+ YUV_SATURATION(128));
+
+ iep_write(iep, IEP_ENH_YUV_CNFG_1,
+ YUV_COS_HUE(255) |
+ YUV_SIN_HUE(255));
+
+ iep_write(iep, IEP_ENH_YUV_CNFG_2,
+ YUV_VIDEO_MODE(VIDEO_MODE_NORMAL_VIDEO));
+
+ */
+
+ /* reset frame counter */
+ iep_write(iep, IEP_FRM_CNT, 0);
+}
+
+static void iep_device_run(void *priv)
+{
+ struct iep_ctx *ctx = priv;
+ struct rockchip_iep *iep = ctx->iep;
+ struct vb2_v4l2_buffer *src, *dst;
+ unsigned int dein_mode;
+ dma_addr_t addr;
+
+ if (ctx->fmt_changed)
+ iep_setup_formats(ctx);
+
+ if (ctx->prev_src_buf)
+ dein_mode = IEP_DEIN_MODE_I4O2;
+ else
+ dein_mode = ctx->field_bff ? IEP_DEIN_MODE_I2O1B : IEP_DEIN_MODE_I2O1T;
+
+ iep_shadow_mod(iep, IEP_CONFIG0, IEP_RAW_CONFIG0,
+ IEP_DEIN_MODE_MASK, IEP_DEIN_MODE(dein_mode));
+
+ /* sync RAW_xxx registers with actual used */
+ iep_write(iep, IEP_CONFIG_DONE, 1);
+
+ /* setup src buff(s)/addresses */
+ src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
+ addr = vb2_dma_contig_plane_dma_addr(&src->vb2_buf, 0);
+
+ iep_write(iep, IEP_DEIN_IN_IMG0_Y(ctx->field_bff), addr);
+
+ iep_write(iep, IEP_DEIN_IN_IMG0_CBCR(ctx->field_bff),
+ addr + ctx->src_fmt.y_stride);
+
+ iep_write(iep, IEP_DEIN_IN_IMG0_CR(ctx->field_bff),
+ addr + ctx->src_fmt.uv_stride);
+
+ if (IEP_DEIN_IN_MODE_FIELDS(dein_mode) == IEP_DEIN_IN_FIELDS_4)
+ addr = vb2_dma_contig_plane_dma_addr(&ctx->prev_src_buf->vb2_buf, 0);
+
+ iep_write(iep, IEP_DEIN_IN_IMG1_Y(ctx->field_bff), addr);
+
+ iep_write(iep, IEP_DEIN_IN_IMG1_CBCR(ctx->field_bff),
+ addr + ctx->src_fmt.y_stride);
+
+ iep_write(iep, IEP_DEIN_IN_IMG1_CR(ctx->field_bff),
+ addr + ctx->src_fmt.uv_stride);
+
+ /* setup dst buff(s)/addresses */
+ dst = iep_m2m_next_dst_buf(ctx);
+ addr = vb2_dma_contig_plane_dma_addr(&dst->vb2_buf, 0);
+
+ if (IEP_DEIN_OUT_MODE_FRAMES(dein_mode) == IEP_DEIN_OUT_FRAMES_2) {
+ v4l2_m2m_buf_copy_metadata(ctx->prev_src_buf, dst, true);
+
+ iep_write(iep, IEP_DEIN_OUT_IMG0_Y(ctx->field_bff), addr);
+
+ iep_write(iep, IEP_DEIN_OUT_IMG0_CBCR(ctx->field_bff),
+ addr + ctx->dst_fmt.y_stride);
+
+ iep_write(iep, IEP_DEIN_OUT_IMG0_CR(ctx->field_bff),
+ addr + ctx->dst_fmt.uv_stride);
+
+ ctx->dst0_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
+
+ dst = iep_m2m_next_dst_buf(ctx);
+ addr = vb2_dma_contig_plane_dma_addr(&dst->vb2_buf, 0);
+ }
+
+ v4l2_m2m_buf_copy_metadata(src, dst, true);
+
+ iep_write(iep, IEP_DEIN_OUT_IMG1_Y(ctx->field_bff), addr);
+
+ iep_write(iep, IEP_DEIN_OUT_IMG1_CBCR(ctx->field_bff),
+ addr + ctx->dst_fmt.y_stride);
+
+ iep_write(iep, IEP_DEIN_OUT_IMG1_CR(ctx->field_bff),
+ addr + ctx->dst_fmt.uv_stride);
+
+ ctx->dst1_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
+
+ iep_mod(ctx->iep, IEP_INT, IEP_INT_FRAME_DONE_EN,
+ IEP_INT_FRAME_DONE_EN);
+
+ /* start HW */
+ iep_write(iep, IEP_FRM_START, 1);
+}
+
+static int iep_job_ready(void *priv)
+{
+ struct iep_ctx *ctx = priv;
+
+ return v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) >= 2 &&
+ v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) >= 1;
+}
+
+static void iep_job_abort(void *priv)
+{
+ struct iep_ctx *ctx = priv;
+
+ /* Will cancel the transaction in the next interrupt handler */
+ ctx->job_abort = true;
+}
+
+static const struct v4l2_m2m_ops iep_m2m_ops = {
+ .device_run = iep_device_run,
+ .job_ready = iep_job_ready,
+ .job_abort = iep_job_abort,
+};
+
+static int iep_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers,
+ unsigned int *nplanes, unsigned int sizes[],
+ struct device *alloc_devs[])
+{
+ struct iep_ctx *ctx = vb2_get_drv_priv(vq);
+ struct v4l2_pix_format *pix_fmt;
+
+ if (V4L2_TYPE_IS_OUTPUT(vq->type))
+ pix_fmt = &ctx->src_fmt.pix;
+ else
+ pix_fmt = &ctx->dst_fmt.pix;
+
+ if (*nplanes) {
+ if (sizes[0] < pix_fmt->sizeimage)
+ return -EINVAL;
+ } else {
+ sizes[0] = pix_fmt->sizeimage;
+ *nplanes = 1;
+ }
+
+ return 0;
+}
+
+static int iep_buf_prepare(struct vb2_buffer *vb)
+{
+ struct vb2_queue *vq = vb->vb2_queue;
+ struct iep_ctx *ctx = vb2_get_drv_priv(vq);
+ struct v4l2_pix_format *pix_fmt;
+
+ if (V4L2_TYPE_IS_OUTPUT(vq->type))
+ pix_fmt = &ctx->src_fmt.pix;
+ else
+ pix_fmt = &ctx->dst_fmt.pix;
+
+ if (vb2_plane_size(vb, 0) < pix_fmt->sizeimage)
+ return -EINVAL;
+
+ /* set bytesused for capture buffers */
+ if (!V4L2_TYPE_IS_OUTPUT(vq->type))
+ vb2_set_plane_payload(vb, 0, pix_fmt->sizeimage);
+
+ return 0;
+}
+
+static void iep_buf_queue(struct vb2_buffer *vb)
+{
+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+ struct iep_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
+
+ v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
+}
+
+static void iep_queue_cleanup(struct vb2_queue *vq, u32 state)
+{
+ struct iep_ctx *ctx = vb2_get_drv_priv(vq);
+ struct vb2_v4l2_buffer *vbuf;
+
+ do {
+ if (V4L2_TYPE_IS_OUTPUT(vq->type))
+ vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
+ else
+ vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
+
+ if (vbuf)
+ v4l2_m2m_buf_done(vbuf, state);
+ } while (vbuf);
+
+ if (V4L2_TYPE_IS_OUTPUT(vq->type) && ctx->prev_src_buf)
+ v4l2_m2m_buf_done(ctx->prev_src_buf, state);
+ else
+ iep_m2m_dst_bufs_done(ctx, state);
+}
+
+static int iep_start_streaming(struct vb2_queue *vq, unsigned int count)
+{
+ struct iep_ctx *ctx = vb2_get_drv_priv(vq);
+ struct device *dev = ctx->iep->dev;
+ int ret;
+
+ if (V4L2_TYPE_IS_OUTPUT(vq->type)) {
+ ret = pm_runtime_get_sync(dev);
+ if (ret < 0) {
+ dev_err(dev, "Failed to enable module\n");
+ goto err_runtime_get;
+ }
+
+ ctx->field_order_bff =
+ ctx->src_fmt.pix.field == V4L2_FIELD_INTERLACED_BT;
+ ctx->field_bff = ctx->field_order_bff;
+
+ ctx->src_sequence = 0;
+ ctx->dst_sequence = 0;
+
+ ctx->prev_src_buf = NULL;
+
+ ctx->dst0_buf = NULL;
+ ctx->dst1_buf = NULL;
+ ctx->dst_buffs_done = 0;
+
+ ctx->job_abort = false;
+
+ iep_init(ctx->iep);
+ //if (ctx->src_fmt.pix.field != ctx->dst_fmt.pix.field)
+ iep_dein_init(ctx->iep);
+ }
+
+ return 0;
+
+err_runtime_get:
+ iep_queue_cleanup(vq, VB2_BUF_STATE_QUEUED);
+
+ return ret;
+}
+
+static void iep_stop_streaming(struct vb2_queue *vq)
+{
+ struct iep_ctx *ctx = vb2_get_drv_priv(vq);
+
+ if (V4L2_TYPE_IS_OUTPUT(vq->type)) {
+ pm_runtime_mark_last_busy(ctx->iep->dev);
+ pm_runtime_put_autosuspend(ctx->iep->dev);
+ }
+
+ iep_queue_cleanup(vq, VB2_BUF_STATE_ERROR);
+}
+
+static const struct vb2_ops iep_qops = {
+ .queue_setup = iep_queue_setup,
+ .buf_prepare = iep_buf_prepare,
+ .buf_queue = iep_buf_queue,
+ .start_streaming = iep_start_streaming,
+ .stop_streaming = iep_stop_streaming,
+ .wait_prepare = vb2_ops_wait_prepare,
+ .wait_finish = vb2_ops_wait_finish,
+};
+
+static int iep_queue_init(void *priv, struct vb2_queue *src_vq,
+ struct vb2_queue *dst_vq)
+{
+ struct iep_ctx *ctx = priv;
+ int ret;
+
+ src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
+ src_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES |
+ DMA_ATTR_NO_KERNEL_MAPPING;
+ src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
+ src_vq->drv_priv = ctx;
+ src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
+ src_vq->min_buffers_needed = 1;
+ src_vq->ops = &iep_qops;
+ src_vq->mem_ops = &vb2_dma_contig_memops;
+ src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
+ src_vq->lock = &ctx->iep->mutex;
+ src_vq->dev = ctx->iep->v4l2_dev.dev;
+
+ ret = vb2_queue_init(src_vq);
+ if (ret)
+ return ret;
+
+ dst_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES |
+ DMA_ATTR_NO_KERNEL_MAPPING;
+ dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+ dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
+ dst_vq->drv_priv = ctx;
+ dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
+ dst_vq->min_buffers_needed = 2;
+ dst_vq->ops = &iep_qops;
+ dst_vq->mem_ops = &vb2_dma_contig_memops;
+ dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
+ dst_vq->lock = &ctx->iep->mutex;
+ dst_vq->dev = ctx->iep->v4l2_dev.dev;
+
+ ret = vb2_queue_init(dst_vq);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void iep_prepare_format(struct v4l2_pix_format *pix_fmt)
+{
+ unsigned int height = pix_fmt->height;
+ unsigned int width = pix_fmt->width;
+ unsigned int sizeimage, bytesperline;
+
+ struct iep_fmt *hw_fmt = iep_fmt_find(pix_fmt);
+
+ if (!hw_fmt) {
+ hw_fmt = &formats[0];
+ pix_fmt->pixelformat = hw_fmt->fourcc;
+ }
+
+ width = ALIGN(clamp(width, IEP_MIN_WIDTH,
+ IEP_MAX_WIDTH), 16);
+ height = ALIGN(clamp(height, IEP_MIN_HEIGHT,
+ IEP_MAX_HEIGHT), 16);
+
+ bytesperline = FMT_IS_YUV(hw_fmt->hw_format)
+ ? width : (width * hw_fmt->depth) >> 3;
+
+ sizeimage = height * (width * hw_fmt->depth) >> 3;
+
+ pix_fmt->width = width;
+ pix_fmt->height = height;
+ pix_fmt->bytesperline = bytesperline;
+ pix_fmt->sizeimage = sizeimage;
+}
+
+static int iep_open(struct file *file)
+{
+ struct rockchip_iep *iep = video_drvdata(file);
+ struct iep_ctx *ctx = NULL;
+
+ int ret;
+
+ if (mutex_lock_interruptible(&iep->mutex))
+ return -ERESTARTSYS;
+
+ ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
+ if (!ctx) {
+ mutex_unlock(&iep->mutex);
+ return -ENOMEM;
+ }
+
+ /* default output format */
+ ctx->src_fmt.pix.pixelformat = formats[0].fourcc;
+ ctx->src_fmt.pix.field = V4L2_FIELD_INTERLACED;
+ ctx->src_fmt.pix.width = IEP_DEFAULT_WIDTH;
+ ctx->src_fmt.pix.height = IEP_DEFAULT_HEIGHT;
+ iep_prepare_format(&ctx->src_fmt.pix);
+ ctx->src_fmt.hw_fmt = &formats[0];
+ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height);
+ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height,
+ ctx->src_fmt.hw_fmt->uv_factor);
+
+ /* default capture format */
+ ctx->dst_fmt.pix.pixelformat = formats[0].fourcc;
+ ctx->dst_fmt.pix.field = V4L2_FIELD_NONE;
+ ctx->dst_fmt.pix.width = IEP_DEFAULT_WIDTH;
+ ctx->dst_fmt.pix.height = IEP_DEFAULT_HEIGHT;
+ iep_prepare_format(&ctx->dst_fmt.pix);
+ ctx->dst_fmt.hw_fmt = &formats[0];
+ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height);
+ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height,
+ ctx->dst_fmt.hw_fmt->uv_factor);
+ /* ensure fmts are written to HW */
+ ctx->fmt_changed = true;
+
+ v4l2_fh_init(&ctx->fh, video_devdata(file));
+ file->private_data = &ctx->fh;
+ ctx->iep = iep;
+
+ ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(iep->m2m_dev, ctx,
+ &iep_queue_init);
+
+ if (IS_ERR(ctx->fh.m2m_ctx)) {
+ ret = PTR_ERR(ctx->fh.m2m_ctx);
+ goto err_free;
+ }
+
+ v4l2_fh_add(&ctx->fh);
+
+ mutex_unlock(&iep->mutex);
+
+ return 0;
+
+err_free:
+ kfree(ctx);
+ mutex_unlock(&iep->mutex);
+
+ return ret;
+}
+
+static int iep_release(struct file *file)
+{
+ struct rockchip_iep *iep = video_drvdata(file);
+ struct iep_ctx *ctx = container_of(file->private_data,
+ struct iep_ctx, fh);
+
+ mutex_lock(&iep->mutex);
+
+ v4l2_fh_del(&ctx->fh);
+ v4l2_fh_exit(&ctx->fh);
+ v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
+ kfree(ctx);
+
+ mutex_unlock(&iep->mutex);
+ return 0;
+}
+
+static const struct v4l2_file_operations iep_fops = {
+ .owner = THIS_MODULE,
+ .open = iep_open,
+ .release = iep_release,
+ .poll = v4l2_m2m_fop_poll,
+ .unlocked_ioctl = video_ioctl2,
+ .mmap = v4l2_m2m_fop_mmap,
+};
+
+static int iep_querycap(struct file *file, void *priv,
+ struct v4l2_capability *cap)
+{
+ strscpy(cap->driver, IEP_NAME, sizeof(cap->driver));
+ strscpy(cap->card, IEP_NAME, sizeof(cap->card));
+ snprintf(cap->bus_info, sizeof(cap->bus_info),
+ "platform:%s", IEP_NAME);
+
+ return 0;
+}
+
+static int iep_enum_fmt(struct file *file, void *priv,
+ struct v4l2_fmtdesc *f)
+{
+ struct iep_fmt *fmt;
+
+ if (f->index < ARRAY_SIZE(formats)) {
+ fmt = &formats[f->index];
+ f->pixelformat = fmt->fourcc;
+
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int iep_enum_framesizes(struct file *file, void *priv,
+ struct v4l2_frmsizeenum *fsize)
+{
+ if (fsize->index != 0)
+ return -EINVAL;
+
+ if (!iep_check_pix_format(fsize->pixel_format))
+ return -EINVAL;
+
+ fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
+
+ fsize->stepwise.min_width = IEP_MIN_WIDTH;
+ fsize->stepwise.max_width = IEP_MAX_WIDTH;
+ fsize->stepwise.step_width = 16;
+
+ fsize->stepwise.min_height = IEP_MIN_HEIGHT;
+ fsize->stepwise.max_height = IEP_MAX_HEIGHT;
+ fsize->stepwise.step_height = 16;
+
+ return 0;
+}
+
+static inline struct iep_ctx *iep_file2ctx(struct file *file)
+{
+ return container_of(file->private_data, struct iep_ctx, fh);
+}
+
+static int iep_g_fmt_vid_cap(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct iep_ctx *ctx = iep_file2ctx(file);
+
+ f->fmt.pix = ctx->dst_fmt.pix;
+
+ return 0;
+}
+
+static int iep_g_fmt_vid_out(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct iep_ctx *ctx = iep_file2ctx(file);
+
+ f->fmt.pix = ctx->src_fmt.pix;
+
+ return 0;
+}
+
+static int iep_try_fmt_vid_cap(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ f->fmt.pix.field = V4L2_FIELD_NONE;
+ iep_prepare_format(&f->fmt.pix);
+
+ return 0;
+}
+
+static int iep_try_fmt_vid_out(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ if (f->fmt.pix.field != V4L2_FIELD_INTERLACED_TB &&
+ f->fmt.pix.field != V4L2_FIELD_INTERLACED_BT &&
+ f->fmt.pix.field != V4L2_FIELD_INTERLACED)
+ f->fmt.pix.field = V4L2_FIELD_INTERLACED;
+
+ iep_prepare_format(&f->fmt.pix);
+
+ return 0;
+}
+
+static int iep_s_fmt_vid_out(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct iep_ctx *ctx = iep_file2ctx(file);
+ struct vb2_queue *vq;
+
+ int ret;
+
+ ret = iep_try_fmt_vid_out(file, priv, f);
+ if (ret)
+ return ret;
+
+ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
+ if (vb2_is_busy(vq))
+ return -EBUSY;
+
+ ctx->src_fmt.pix = f->fmt.pix;
+ ctx->src_fmt.hw_fmt = iep_fmt_find(&f->fmt.pix);
+ ctx->src_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height);
+ ctx->src_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height,
+ ctx->src_fmt.hw_fmt->uv_factor);
+
+ /* Propagate colorspace information to capture. */
+ ctx->dst_fmt.pix.colorspace = f->fmt.pix.colorspace;
+ ctx->dst_fmt.pix.xfer_func = f->fmt.pix.xfer_func;
+ ctx->dst_fmt.pix.ycbcr_enc = f->fmt.pix.ycbcr_enc;
+ ctx->dst_fmt.pix.quantization = f->fmt.pix.quantization;
+
+ /* scaling is not supported */
+ ctx->dst_fmt.pix.width = f->fmt.pix.width;
+ ctx->dst_fmt.pix.height = f->fmt.pix.height;
+ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height);
+ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height,
+ ctx->dst_fmt.hw_fmt->uv_factor);
+
+ ctx->fmt_changed = true;
+
+ return 0;
+}
+
+static int iep_s_fmt_vid_cap(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct iep_ctx *ctx = iep_file2ctx(file);
+ struct vb2_queue *vq;
+ int ret;
+
+ ret = iep_try_fmt_vid_cap(file, priv, f);
+ if (ret)
+ return ret;
+
+ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
+ if (vb2_is_busy(vq))
+ return -EBUSY;
+
+ /* scaling is not supported */
+ f->fmt.pix.width = ctx->src_fmt.pix.width;
+ f->fmt.pix.height = ctx->src_fmt.pix.height;
+
+ ctx->dst_fmt.pix = f->fmt.pix;
+ ctx->dst_fmt.hw_fmt = iep_fmt_find(&f->fmt.pix);
+
+ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height);
+ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height,
+ ctx->dst_fmt.hw_fmt->uv_factor);
+
+ ctx->fmt_changed = true;
+
+ return 0;
+}
+
+static const struct v4l2_ioctl_ops iep_ioctl_ops = {
+ .vidioc_querycap = iep_querycap,
+
+ .vidioc_enum_framesizes = iep_enum_framesizes,
+
+ .vidioc_enum_fmt_vid_cap = iep_enum_fmt,
+ .vidioc_g_fmt_vid_cap = iep_g_fmt_vid_cap,
+ .vidioc_try_fmt_vid_cap = iep_try_fmt_vid_cap,
+ .vidioc_s_fmt_vid_cap = iep_s_fmt_vid_cap,
+
+ .vidioc_enum_fmt_vid_out = iep_enum_fmt,
+ .vidioc_g_fmt_vid_out = iep_g_fmt_vid_out,
+ .vidioc_try_fmt_vid_out = iep_try_fmt_vid_out,
+ .vidioc_s_fmt_vid_out = iep_s_fmt_vid_out,
+
+ .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
+ .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
+ .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
+ .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
+ .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
+ .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
+ .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
+
+ .vidioc_streamon = v4l2_m2m_ioctl_streamon,
+ .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
+};
+
+static const struct video_device iep_video_device = {
+ .name = IEP_NAME,
+ .vfl_dir = VFL_DIR_M2M,
+ .fops = &iep_fops,
+ .ioctl_ops = &iep_ioctl_ops,
+ .minor = -1,
+ .release = video_device_release_empty,
+ .device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,
+};
+
+static int iep_parse_dt(struct rockchip_iep *iep)
+{
+ int ret = 0;
+
+ iep->axi_clk = devm_clk_get(iep->dev, "axi");
+ if (IS_ERR(iep->axi_clk)) {
+ dev_err(iep->dev, "failed to get aclk clock\n");
+ return PTR_ERR(iep->axi_clk);
+ }
+
+ iep->ahb_clk = devm_clk_get(iep->dev, "ahb");
+ if (IS_ERR(iep->ahb_clk)) {
+ dev_err(iep->dev, "failed to get hclk clock\n");
+ return PTR_ERR(iep->ahb_clk);
+ }
+
+ ret = clk_set_rate(iep->axi_clk, 300000000);
+
+ if (ret)
+ dev_err(iep->dev, "failed to set axi clock rate to 300 MHz\n");
+
+ return ret;
+}
+
+static irqreturn_t iep_isr(int irq, void *prv)
+{
+ struct rockchip_iep *iep = prv;
+ struct iep_ctx *ctx;
+ u32 val;
+ enum vb2_buffer_state state = VB2_BUF_STATE_DONE;
+
+ ctx = v4l2_m2m_get_curr_priv(iep->m2m_dev);
+ if (!ctx) {
+ v4l2_err(&iep->v4l2_dev,
+ "Instance released before the end of transaction\n");
+ return IRQ_NONE;
+ }
+
+ /*
+ * The irq is shared with the iommu. If the runtime-pm state of the
+ * iep-device is disabled or the interrupt status doesn't match the
+ * expeceted mask the irq has been targeted to the iommu.
+ */
+
+ if (!pm_runtime_active(iep->dev) ||
+ !(iep_read(iep, IEP_INT) & IEP_INT_MASK))
+ return IRQ_NONE;
+
+ /* disable interrupt - will be re-enabled at next iep_device_run */
+ iep_mod(ctx->iep, IEP_INT,
+ IEP_INT_FRAME_DONE_EN, 0);
+
+ iep_mod(iep, IEP_INT, IEP_INT_FRAME_DONE_CLR,
+ IEP_INT_FRAME_DONE_CLR);
+
+ /* wait for all status regs to show "idle" */
+ val = readl_poll_timeout(iep->regs + IEP_STATUS, val,
+ (val == 0), 100, IEP_TIMEOUT);
+
+ if (val) {
+ dev_err(iep->dev,
+ "Failed to wait for job to finish: status: %u\n", val);
+ state = VB2_BUF_STATE_ERROR;
+ ctx->job_abort = true;
+ }
+
+ iep_m2m_dst_bufs_done(ctx, state);
+
+ ctx->field_bff = (ctx->dst_buffs_done % 2 == 0)
+ ? ctx->field_order_bff : !ctx->field_order_bff;
+
+ if (ctx->dst_buffs_done == 2 || ctx->job_abort) {
+ if (ctx->prev_src_buf)
+ v4l2_m2m_buf_done(ctx->prev_src_buf, state);
+
+ /* current src buff will be next prev */
+ ctx->prev_src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
+
+ v4l2_m2m_job_finish(ctx->iep->m2m_dev, ctx->fh.m2m_ctx);
+ ctx->dst_buffs_done = 0;
+
+ } else {
+ iep_device_run(ctx);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int iep_probe(struct platform_device *pdev)
+{
+ struct rockchip_iep *iep;
+ struct video_device *vfd;
+ struct resource *res;
+ int ret = 0;
+ int irq;
+
+ if (!pdev->dev.of_node)
+ return -ENODEV;
+
+ iep = devm_kzalloc(&pdev->dev, sizeof(*iep), GFP_KERNEL);
+ if (!iep)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, iep);
+ iep->dev = &pdev->dev;
+ iep->vfd = iep_video_device;
+
+ ret = iep_parse_dt(iep);
+ if (ret)
+ dev_err(&pdev->dev, "Unable to parse OF data\n");
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ iep->regs = devm_ioremap_resource(iep->dev, res);
+ if (IS_ERR(iep->regs)) {
+ ret = PTR_ERR(iep->regs);
+ goto err_put_clk;
+ }
+
+ ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
+ if (ret) {
+ dev_err(&pdev->dev, "Could not set DMA coherent mask.\n");
+ goto err_put_clk;
+ }
+
+ vb2_dma_contig_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32));
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ ret = irq;
+ goto err_put_clk;
+ }
+
+ /* IRQ is shared with IOMMU */
+ ret = devm_request_irq(iep->dev, irq, iep_isr, IRQF_SHARED,
+ dev_name(iep->dev), iep);
+ if (ret < 0) {
+ dev_err(iep->dev, "failed to request irq\n");
+ goto err_put_clk;
+ }
+
+ mutex_init(&iep->mutex);
+
+ ret = v4l2_device_register(&pdev->dev, &iep->v4l2_dev);
+ if (ret) {
+ dev_err(iep->dev, "Failed to register V4L2 device\n");
+
+ return ret;
+ }
+
+ vfd = &iep->vfd;
+ vfd->lock = &iep->mutex;
+ vfd->v4l2_dev = &iep->v4l2_dev;
+
+ snprintf(vfd->name, sizeof(vfd->name), "%s",
+ iep_video_device.name);
+
+ video_set_drvdata(vfd, iep);
+
+ ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0);
+ if (ret) {
+ v4l2_err(&iep->v4l2_dev, "Failed to register video device\n");
+
+ goto err_v4l2;
+ }
+
+ v4l2_info(&iep->v4l2_dev,
+ "Device %s registered as /dev/video%d\n", vfd->name, vfd->num);
+
+ iep->m2m_dev = v4l2_m2m_init(&iep_m2m_ops);
+ if (IS_ERR(iep->m2m_dev)) {
+ v4l2_err(&iep->v4l2_dev,
+ "Failed to initialize V4L2 M2M device\n");
+ ret = PTR_ERR(iep->m2m_dev);
+
+ goto err_video;
+ }
+
+ pm_runtime_set_autosuspend_delay(iep->dev, 100);
+ pm_runtime_use_autosuspend(iep->dev);
+ pm_runtime_enable(iep->dev);
+
+ return ret;
+
+err_video:
+ video_unregister_device(&iep->vfd);
+err_v4l2:
+ v4l2_device_unregister(&iep->v4l2_dev);
+err_put_clk:
+ pm_runtime_dont_use_autosuspend(iep->dev);
+ pm_runtime_disable(iep->dev);
+
+return ret;
+}
+
+static int iep_remove(struct platform_device *pdev)
+{
+ struct rockchip_iep *iep = platform_get_drvdata(pdev);
+
+ pm_runtime_dont_use_autosuspend(iep->dev);
+ pm_runtime_disable(iep->dev);
+
+ v4l2_m2m_release(iep->m2m_dev);
+ video_unregister_device(&iep->vfd);
+ v4l2_device_unregister(&iep->v4l2_dev);
+
+ return 0;
+}
+
+static int __maybe_unused iep_runtime_suspend(struct device *dev)
+{
+ struct rockchip_iep *iep = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(iep->ahb_clk);
+ clk_disable_unprepare(iep->axi_clk);
+
+ return 0;
+}
+
+static int __maybe_unused iep_runtime_resume(struct device *dev)
+{
+ struct rockchip_iep *iep;
+ int ret = 0;
+
+ iep = dev_get_drvdata(dev);
+
+ ret = clk_prepare_enable(iep->axi_clk);
+ if (ret) {
+ dev_err(iep->dev, "Cannot enable axi clock: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(iep->ahb_clk);
+ if (ret) {
+ dev_err(iep->dev, "Cannot enable ahb clock: %d\n", ret);
+ goto err_disable_axi_clk;
+ }
+
+ return ret;
+
+err_disable_axi_clk:
+ clk_disable_unprepare(iep->axi_clk);
+ return ret;
+}
+
+static const struct dev_pm_ops iep_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+ pm_runtime_force_resume)
+ SET_RUNTIME_PM_OPS(iep_runtime_suspend,
+ iep_runtime_resume, NULL)
+};
+
+static const struct of_device_id rockchip_iep_match[] = {
+ {
+ .compatible = "rockchip,rk3228-iep",
+ },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, rockchip_iep_match);
+
+static struct platform_driver iep_pdrv = {
+ .probe = iep_probe,
+ .remove = iep_remove,
+ .driver = {
+ .name = IEP_NAME,
+ .pm = &iep_pm_ops,
+ .of_match_table = rockchip_iep_match,
+ },
+};
+
+module_platform_driver(iep_pdrv);
+
+MODULE_AUTHOR("Alex Bee <knaerzche@gmail.com>");
+MODULE_DESCRIPTION("Rockchip Image Enhancement Processor");
+MODULE_LICENSE("GPL v2");
diff -rupN linux.orig/drivers/media/platform/rockchip/iep/iep.h linux/drivers/media/platform/rockchip/iep/iep.h
--- linux.orig/drivers/media/platform/rockchip/iep/iep.h 1970-01-01 00:00:00.000000000 +0000
+++ linux/drivers/media/platform/rockchip/iep/iep.h 2024-01-03 21:28:43.674043912 +0000
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Rockchip Image Enhancement Processor (IEP) driver
+ *
+ * Copyright (C) 2020 Alex Bee <knaerzche@gmail.com>
+ *
+ */
+#ifndef __IEP_H__
+#define __IEP_H__
+
+#include <linux/platform_device.h>
+#include <media/videobuf2-v4l2.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-device.h>
+
+#define IEP_NAME "rockchip-iep"
+
+/* Hardware limits */
+#define IEP_MIN_WIDTH 320U
+#define IEP_MAX_WIDTH 1920U
+
+#define IEP_MIN_HEIGHT 240U
+#define IEP_MAX_HEIGHT 1088U
+
+/* Hardware defaults */
+#define IEP_DEFAULT_WIDTH 320U
+#define IEP_DEFAULT_HEIGHT 240U
+
+//ns
+#define IEP_TIMEOUT 250000
+
+struct iep_fmt {
+ u32 fourcc;
+ u8 depth;
+ u8 uv_factor;
+ u8 color_swap;
+ u8 hw_format;
+};
+
+struct iep_frm_fmt {
+ struct iep_fmt *hw_fmt;
+ struct v4l2_pix_format pix;
+
+ unsigned int y_stride;
+ unsigned int uv_stride;
+};
+
+struct iep_ctx {
+ struct v4l2_fh fh;
+ struct rockchip_iep *iep;
+
+ struct iep_frm_fmt src_fmt;
+ struct iep_frm_fmt dst_fmt;
+
+ struct vb2_v4l2_buffer *prev_src_buf;
+ struct vb2_v4l2_buffer *dst0_buf;
+ struct vb2_v4l2_buffer *dst1_buf;
+
+ u32 dst_sequence;
+ u32 src_sequence;
+
+ /* bff = bottom field first */
+ bool field_order_bff;
+ bool field_bff;
+
+ unsigned int dst_buffs_done;
+
+ bool fmt_changed;
+ bool job_abort;
+};
+
+struct rockchip_iep {
+ struct v4l2_device v4l2_dev;
+ struct v4l2_m2m_dev *m2m_dev;
+ struct video_device vfd;
+
+ struct device *dev;
+
+ void __iomem *regs;
+
+ struct clk *axi_clk;
+ struct clk *ahb_clk;
+
+ /* vfd lock */
+ struct mutex mutex;
+};
+
+static inline void iep_write(struct rockchip_iep *iep, u32 reg, u32 value)
+{
+ writel(value, iep->regs + reg);
+};
+
+static inline u32 iep_read(struct rockchip_iep *iep, u32 reg)
+{
+ return readl(iep->regs + reg);
+};
+
+static inline void iep_shadow_mod(struct rockchip_iep *iep, u32 reg,
+ u32 shadow_reg, u32 mask, u32 val)
+{
+ u32 temp = iep_read(iep, shadow_reg) & ~(mask);
+
+ temp |= val & mask;
+ iep_write(iep, reg, temp);
+};
+
+static inline void iep_mod(struct rockchip_iep *iep, u32 reg, u32 mask, u32 val)
+{
+ iep_shadow_mod(iep, reg, reg, mask, val);
+};
+
+#endif
diff -rupN linux.orig/drivers/media/platform/verisilicon/rockchip_vpu_hw.c linux/drivers/media/platform/verisilicon/rockchip_vpu_hw.c
--- linux.orig/drivers/media/platform/verisilicon/rockchip_vpu_hw.c 2024-01-03 20:53:30.815326981 +0000
+++ linux/drivers/media/platform/verisilicon/rockchip_vpu_hw.c 2024-01-03 21:26:02.711011382 +0000
@@ -15,7 +15,8 @@
#include "rockchip_vpu2_regs.h"
#define RK3066_ACLK_MAX_FREQ (300 * 1000 * 1000)
-#define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000)
+#define RK3288_ACLK_MAX_FREQ (600 * 1000 * 1000)
+#define RK3399_ACLK_MAX_FREQ (400 * 1000 * 1000)
/*
* Supported formats.
@@ -346,13 +347,20 @@ static int rk3066_vpu_hw_init(struct han
return 0;
}
-static int rockchip_vpu_hw_init(struct hantro_dev *vpu)
+static int rk3288_vpu_hw_init(struct hantro_dev *vpu)
{
/* Bump ACLK to max. possible freq. to improve performance. */
clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ);
return 0;
}
+static int rockchip_vpu_hw_init(struct hantro_dev *vpu)
+{
+ /* Bump ACLK to max. possible freq. to improve performance. */
+ clk_set_rate(vpu->clocks[0].clk, RK3399_ACLK_MAX_FREQ);
+ return 0;
+}
+
static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx)
{
struct hantro_dev *vpu = ctx->dev;
@@ -592,7 +600,7 @@ const struct hantro_variant rk3288_vpu_v
.codec_ops = rk3288_vpu_codec_ops,
.irqs = rockchip_vpu1_irqs,
.num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs),
- .init = rockchip_vpu_hw_init,
+ .init = rk3288_vpu_hw_init,
.clk_names = rockchip_vpu_clk_names,
.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
};
diff -rupN linux.orig/drivers/media/v4l2-core/v4l2-common.c linux/drivers/media/v4l2-core/v4l2-common.c
--- linux.orig/drivers/media/v4l2-core/v4l2-common.c 2024-01-03 20:53:30.851327467 +0000
+++ linux/drivers/media/v4l2-core/v4l2-common.c 2024-01-03 21:03:38.389716887 +0000
@@ -268,6 +268,9 @@ const struct v4l2_format_info *v4l2_form
{ .format = V4L2_PIX_FMT_NV42, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 1, .vdiv = 1 },
{ .format = V4L2_PIX_FMT_P010, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 2, 2, 0, 0 }, .hdiv = 2, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_NV15, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .hdiv = 2, .vdiv = 2, .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } },
+ { .format = V4L2_PIX_FMT_NV20, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .hdiv = 2, .vdiv = 1, .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } },
+
{ .format = V4L2_PIX_FMT_YUV410, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 4 },
{ .format = V4L2_PIX_FMT_YVU410, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 4 },
{ .format = V4L2_PIX_FMT_YUV411P, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 1 },
@@ -338,6 +341,33 @@ static inline unsigned int v4l2_format_b
return info->block_h[plane];
}
+static inline unsigned int v4l2_format_plane_width(const struct v4l2_format_info *info, int plane,
+ unsigned int width)
+{
+ unsigned int hdiv = plane ? info->hdiv : 1;
+ unsigned int bytes = DIV_ROUND_UP(width * info->bpp[plane],
+ v4l2_format_block_width(info, plane) *
+ v4l2_format_block_height(info, plane));
+
+ return DIV_ROUND_UP(bytes, hdiv);
+}
+
+static inline unsigned int v4l2_format_plane_height(const struct v4l2_format_info *info, int plane,
+ unsigned int height)
+{
+ unsigned int vdiv = plane ? info->vdiv : 1;
+ unsigned int lines = ALIGN(height, v4l2_format_block_height(info, plane));
+
+ return DIV_ROUND_UP(lines, vdiv);
+}
+
+static inline unsigned int v4l2_format_plane_size(const struct v4l2_format_info *info, int plane,
+ unsigned int width, unsigned int height)
+{
+ return v4l2_format_plane_width(info, plane, width) *
+ v4l2_format_plane_height(info, plane, height);
+}
+
void v4l2_apply_frmsize_constraints(u32 *width, u32 *height,
const struct v4l2_frmsize_stepwise *frmsize)
{
@@ -373,37 +403,19 @@ int v4l2_fill_pixfmt_mp(struct v4l2_pix_
if (info->mem_planes == 1) {
plane = &pixfmt->plane_fmt[0];
- plane->bytesperline = ALIGN(width, v4l2_format_block_width(info, 0)) * info->bpp[0];
+ plane->bytesperline = v4l2_format_plane_width(info, 0, width);
plane->sizeimage = 0;
- for (i = 0; i < info->comp_planes; i++) {
- unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
- unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
- unsigned int aligned_width;
- unsigned int aligned_height;
-
- aligned_width = ALIGN(width, v4l2_format_block_width(info, i));
- aligned_height = ALIGN(height, v4l2_format_block_height(info, i));
-
- plane->sizeimage += info->bpp[i] *
- DIV_ROUND_UP(aligned_width, hdiv) *
- DIV_ROUND_UP(aligned_height, vdiv);
- }
+ for (i = 0; i < info->comp_planes; i++)
+ plane->sizeimage +=
+ v4l2_format_plane_size(info, i, width, height);
} else {
for (i = 0; i < info->comp_planes; i++) {
- unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
- unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
- unsigned int aligned_width;
- unsigned int aligned_height;
-
- aligned_width = ALIGN(width, v4l2_format_block_width(info, i));
- aligned_height = ALIGN(height, v4l2_format_block_height(info, i));
-
plane = &pixfmt->plane_fmt[i];
plane->bytesperline =
- info->bpp[i] * DIV_ROUND_UP(aligned_width, hdiv);
- plane->sizeimage =
- plane->bytesperline * DIV_ROUND_UP(aligned_height, vdiv);
+ v4l2_format_plane_width(info, i, width);
+ plane->sizeimage = plane->bytesperline *
+ v4l2_format_plane_height(info, i, height);
}
}
return 0;
@@ -427,22 +439,12 @@ int v4l2_fill_pixfmt(struct v4l2_pix_for
pixfmt->width = width;
pixfmt->height = height;
pixfmt->pixelformat = pixelformat;
- pixfmt->bytesperline = ALIGN(width, v4l2_format_block_width(info, 0)) * info->bpp[0];
+ pixfmt->bytesperline = v4l2_format_plane_width(info, 0, width);
pixfmt->sizeimage = 0;
- for (i = 0; i < info->comp_planes; i++) {
- unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
- unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
- unsigned int aligned_width;
- unsigned int aligned_height;
-
- aligned_width = ALIGN(width, v4l2_format_block_width(info, i));
- aligned_height = ALIGN(height, v4l2_format_block_height(info, i));
-
- pixfmt->sizeimage += info->bpp[i] *
- DIV_ROUND_UP(aligned_width, hdiv) *
- DIV_ROUND_UP(aligned_height, vdiv);
- }
+ for (i = 0; i < info->comp_planes; i++)
+ pixfmt->sizeimage +=
+ v4l2_format_plane_size(info, i, width, height);
return 0;
}
EXPORT_SYMBOL_GPL(v4l2_fill_pixfmt);
diff -rupN linux.orig/drivers/media/v4l2-core/v4l2-ioctl.c linux/drivers/media/v4l2-core/v4l2-ioctl.c
--- linux.orig/drivers/media/v4l2-core/v4l2-ioctl.c 2024-01-03 20:53:30.851327467 +0000
+++ linux/drivers/media/v4l2-core/v4l2-ioctl.c 2024-01-03 21:03:38.389716887 +0000
@@ -1354,6 +1354,8 @@ static void v4l_fill_fmtdesc(struct v4l2
case V4L2_PIX_FMT_NV24: descr = "Y/UV 4:4:4"; break;
case V4L2_PIX_FMT_NV42: descr = "Y/VU 4:4:4"; break;
case V4L2_PIX_FMT_P010: descr = "10-bit Y/UV 4:2:0"; break;
+ case V4L2_PIX_FMT_NV15: descr = "10-bit Y/UV 4:2:0 (Packed)"; break;
+ case V4L2_PIX_FMT_NV20: descr = "10-bit Y/UV 4:2:2 (Packed)"; break;
case V4L2_PIX_FMT_NV12_4L4: descr = "Y/UV 4:2:0 (4x4 Linear)"; break;
case V4L2_PIX_FMT_NV12_16L16: descr = "Y/UV 4:2:0 (16x16 Linear)"; break;
case V4L2_PIX_FMT_NV12_32L32: descr = "Y/UV 4:2:0 (32x32 Linear)"; break;
diff -rupN linux.orig/drivers/mmc/core/core.c linux/drivers/mmc/core/core.c
--- linux.orig/drivers/mmc/core/core.c 2024-01-03 20:53:30.907328224 +0000
+++ linux/drivers/mmc/core/core.c 2024-01-03 21:32:47.747235430 +0000
@@ -1369,6 +1369,14 @@ void mmc_power_off(struct mmc_host *host
if (host->ios.power_mode == MMC_POWER_OFF)
return;
+ mmc_set_initial_signal_voltage(host);
+
+ /*
+ * This delay should be sufficient to allow the power supply
+ * to reach the minimum voltage.
+ */
+ mmc_delay(host->ios.power_delay_ms);
+
mmc_pwrseq_power_off(host);
host->ios.clock = 0;
diff -rupN linux.orig/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c linux/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
--- linux.orig/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c 2024-01-03 20:53:31.235332660 +0000
+++ linux/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c 2024-01-03 21:32:47.747235430 +0000
@@ -245,6 +245,7 @@ struct inno_hdmi_phy {
struct clk_hw hw;
struct clk *phyclk;
unsigned long pixclock;
+ unsigned long tmdsclock;
};
struct pre_pll_config {
@@ -291,31 +292,179 @@ struct inno_hdmi_phy_drv_data {
};
static const struct pre_pll_config pre_pll_cfg_table[] = {
- { 27000000, 27000000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0},
- { 27000000, 33750000, 1, 90, 1, 3, 3, 10, 3, 3, 4, 0, 0},
- { 40000000, 40000000, 1, 80, 2, 2, 2, 12, 2, 2, 2, 0, 0},
- { 59341000, 59341000, 1, 98, 3, 1, 2, 1, 3, 3, 4, 0, 0xE6AE6B},
- { 59400000, 59400000, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0},
- { 59341000, 74176250, 1, 98, 0, 3, 3, 1, 3, 3, 4, 0, 0xE6AE6B},
- { 59400000, 74250000, 1, 99, 1, 2, 2, 1, 3, 3, 4, 0, 0},
- { 74176000, 74176000, 1, 98, 1, 2, 2, 1, 2, 3, 4, 0, 0xE6AE6B},
- { 74250000, 74250000, 1, 99, 1, 2, 2, 1, 2, 3, 4, 0, 0},
- { 74176000, 92720000, 4, 494, 1, 2, 2, 1, 3, 3, 4, 0, 0x816817},
- { 74250000, 92812500, 4, 495, 1, 2, 2, 1, 3, 3, 4, 0, 0},
- {148352000, 148352000, 1, 98, 1, 1, 1, 1, 2, 2, 2, 0, 0xE6AE6B},
- {148500000, 148500000, 1, 99, 1, 1, 1, 1, 2, 2, 2, 0, 0},
- {148352000, 185440000, 4, 494, 0, 2, 2, 1, 3, 2, 2, 0, 0x816817},
- {148500000, 185625000, 4, 495, 0, 2, 2, 1, 3, 2, 2, 0, 0},
- {296703000, 296703000, 1, 98, 0, 1, 1, 1, 0, 2, 2, 0, 0xE6AE6B},
- {297000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0},
- {296703000, 370878750, 4, 494, 1, 2, 0, 1, 3, 1, 1, 0, 0x816817},
- {297000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 0, 0},
- {593407000, 296703500, 1, 98, 0, 1, 1, 1, 0, 2, 1, 0, 0xE6AE6B},
- {594000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 1, 0, 0},
- {593407000, 370879375, 4, 494, 1, 2, 0, 1, 3, 1, 1, 1, 0x816817},
- {594000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 1, 0},
- {593407000, 593407000, 1, 98, 0, 2, 0, 1, 0, 1, 1, 0, 0xE6AE6B},
- {594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0},
+ { 25175000, 25175000, 3, 125, 3, 1, 1, 1, 3, 3, 4, 0, 0xe00000},
+ { 25175000, 31468750, 1, 41, 0, 3, 3, 1, 3, 3, 4, 0, 0xf5554f},
+ { 27000000, 27000000, 1, 36, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
+ { 27000000, 33750000, 1, 45, 0, 3, 3, 1, 3, 3, 4, 0, 0x0},
+ { 31500000, 31500000, 1, 42, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
+ { 31500000, 39375000, 1, 105, 1, 3, 3, 10, 0, 3, 4, 0, 0x0},
+ { 33750000, 33750000, 1, 45, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
+ { 33750000, 42187500, 1, 169, 2, 3, 3, 15, 0, 3, 4, 0, 0x0},
+ { 35500000, 35500000, 1, 71, 2, 2, 2, 6, 0, 3, 4, 0, 0x0},
+ { 35500000, 44375000, 1, 74, 3, 1, 1, 25, 0, 1, 1, 0, 0x0},
+ { 36000000, 36000000, 1, 36, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
+ { 36000000, 45000000, 1, 45, 2, 1, 1, 15, 0, 1, 1, 0, 0x0},
+ { 40000000, 40000000, 1, 40, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
+ { 40000000, 50000000, 1, 50, 2, 1, 1, 15, 0, 1, 1, 0, 0x0},
+ { 49500000, 49500000, 1, 66, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
+ { 49500000, 61875000, 1, 165, 1, 3, 3, 10, 0, 3, 4, 0, 0x0},
+ { 50000000, 50000000, 1, 50, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
+ { 50000000, 62500000, 1, 125, 2, 2, 2, 15, 0, 2, 2, 0, 0x0},
+ { 54000000, 54000000, 1, 36, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
+ { 54000000, 67500000, 1, 45, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
+ { 56250000, 56250000, 1, 75, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
+ { 56250000, 70312500, 1, 117, 3, 1, 1, 25, 0, 1, 1, 0, 0x0},
+ { 59341000, 59341000, 1, 118, 2, 2, 2, 6, 0, 3, 4, 0, 0xae978d},
+ { 59341000, 74176250, 2, 148, 2, 1, 1, 15, 0, 1, 1, 0, 0x5a3d70},
+ { 59400000, 59400000, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0x0},
+ { 59400000, 74250000, 1, 99, 0, 3, 3, 1, 3, 3, 4, 0, 0x0},
+ { 65000000, 65000000, 1, 65, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
+ { 65000000, 81250000, 3, 325, 0, 3, 3, 1, 3, 3, 4, 0, 0x0},
+ { 68250000, 68250000, 1, 91, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
+ { 68250000, 85312500, 1, 142, 3, 1, 1, 25, 0, 1, 1, 0, 0x0},
+ { 71000000, 71000000, 1, 71, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
+ { 71000000, 88750000, 3, 355, 0, 3, 3, 1, 3, 3, 4, 0, 0x0},
+ { 72000000, 72000000, 1, 36, 2, 0, 0, 1, 1, 2, 2, 0, 0x0},
+ { 72000000, 90000000, 1, 60, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
+ { 73250000, 73250000, 3, 293, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
+ { 73250000, 91562500, 1, 61, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
+ { 74176000, 74176000, 1, 37, 2, 0, 0, 1, 1, 2, 2, 0, 0x16872b},
+ { 74176000, 92720000, 2, 185, 2, 1, 1, 15, 0, 1, 1, 0, 0x70a3d7},
+ { 74250000, 74250000, 1, 99, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
+ { 74250000, 92812500, 4, 495, 0, 3, 3, 1, 3, 3, 4, 0, 0x0},
+ { 75000000, 75000000, 1, 50, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
+ { 75000000, 93750000, 1, 125, 0, 3, 3, 1, 3, 3, 4, 0, 0x0},
+ { 78750000, 78750000, 1, 105, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
+ { 78750000, 98437500, 1, 164, 3, 1, 1, 25, 0, 1, 1, 0, 0x0},
+ { 79500000, 79500000, 1, 53, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
+ { 79500000, 99375000, 1, 199, 2, 2, 2, 15, 0, 2, 2, 0, 0x0},
+ { 83500000, 83500000, 2, 167, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
+ { 83500000, 104375000, 1, 104, 2, 1, 1, 15, 0, 1, 1, 0, 0x600000},
+ { 85500000, 85500000, 1, 57, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
+ { 85500000, 106875000, 1, 178, 3, 1, 1, 25, 0, 1, 1, 0, 0x0},
+ { 85750000, 85750000, 3, 343, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
+ { 85750000, 107187500, 1, 143, 0, 3, 3, 1, 3, 3, 4, 0, 0x0},
+ { 88750000, 88750000, 3, 355, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
+ { 88750000, 110937500, 1, 110, 2, 1, 1, 15, 0, 1, 1, 0, 0xf00000},
+ { 94500000, 94500000, 1, 63, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
+ { 94500000, 118125000, 1, 197, 3, 1, 1, 25, 0, 1, 1, 0, 0x0},
+ {101000000, 101000000, 1, 101, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
+ {101000000, 126250000, 1, 42, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
+ {102250000, 102250000, 4, 409, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
+ {102250000, 127812500, 1, 128, 2, 1, 1, 15, 0, 1, 1, 0, 0x0},
+ {106500000, 106500000, 1, 71, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
+ {106500000, 133125000, 1, 133, 2, 1, 1, 15, 0, 1, 1, 0, 0x0},
+ {108000000, 108000000, 1, 36, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
+ {108000000, 135000000, 1, 45, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
+ {115500000, 115500000, 1, 77, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
+ {115500000, 144375000, 1, 48, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
+ {117500000, 117500000, 2, 235, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
+ {117500000, 146875000, 1, 49, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
+ {119000000, 119000000, 1, 119, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
+ {119000000, 148750000, 3, 148, 0, 1, 1, 1, 3, 1, 1, 0, 0xc00000},
+ {121750000, 121750000, 4, 487, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
+ {121750000, 152187500, 1, 203, 0, 3, 3, 1, 3, 3, 4, 0, 0x0},
+ {122500000, 122500000, 2, 245, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
+ {122500000, 153125000, 1, 51, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
+ {135000000, 135000000, 1, 45, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
+ {135000000, 168750000, 1, 169, 2, 1, 1, 15, 0, 1, 1, 0, 0x0},
+ {136750000, 136750000, 1, 68, 2, 0, 0, 1, 1, 2, 2, 0, 0x600000},
+ {136750000, 170937500, 1, 113, 0, 2, 2, 1, 3, 2, 2, 0, 0xf5554f},
+ {140250000, 140250000, 2, 187, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
+ {140250000, 175312500, 1, 117, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
+ {146250000, 146250000, 2, 195, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
+ {146250000, 182812500, 1, 61, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
+ {148250000, 148250000, 3, 222, 2, 0, 0, 1, 1, 2, 2, 0, 0x600000},
+ {148250000, 185312500, 1, 123, 0, 2, 2, 1, 3, 2, 2, 0, 0x8aaab0},
+ {148352000, 148352000, 2, 148, 2, 0, 0, 1, 1, 2, 2, 0, 0x5a1cac},
+ {148352000, 185440000, 3, 185, 0, 1, 1, 1, 3, 1, 1, 0, 0x70a3d7},
+ {148500000, 148500000, 1, 99, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
+ {148500000, 185625000, 4, 495, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
+ {154000000, 154000000, 1, 77, 2, 0, 0, 1, 1, 2, 2, 0, 0x0},
+ {154000000, 192500000, 1, 64, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
+ {156000000, 156000000, 1, 52, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
+ {156000000, 195000000, 1, 65, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
+ {156750000, 156750000, 2, 209, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
+ {156750000, 195937500, 1, 196, 2, 1, 1, 15, 0, 1, 1, 0, 0x0},
+ {157000000, 157000000, 2, 157, 2, 0, 0, 1, 1, 2, 2, 0, 0x0},
+ {157000000, 196250000, 1, 131, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
+ {157500000, 157500000, 1, 105, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
+ {157500000, 196875000, 1, 197, 2, 1, 1, 15, 0, 1, 1, 0, 0x0},
+ {162000000, 162000000, 1, 54, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
+ {162000000, 202500000, 2, 135, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
+ {175500000, 175500000, 1, 117, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
+ {175500000, 219375000, 1, 73, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
+ {179500000, 179500000, 3, 359, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
+ {179500000, 224375000, 1, 75, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
+ {182750000, 182750000, 1, 91, 2, 0, 0, 1, 1, 2, 2, 0, 0x600000},
+ {182750000, 228437500, 1, 152, 0, 2, 2, 1, 3, 2, 2, 0, 0x4aaab0},
+ {182750000, 228437500, 1, 152, 0, 2, 2, 1, 3, 2, 2, 0, 0x4aaab0},
+ {187000000, 187000000, 2, 187, 2, 0, 0, 1, 1, 2, 2, 0, 0x0},
+ {187000000, 233750000, 1, 39, 0, 0, 0, 1, 3, 0, 0, 1, 0x0},
+ {187250000, 187250000, 3, 280, 2, 0, 0, 1, 1, 2, 2, 0, 0xe00000},
+ {187250000, 234062500, 1, 156, 0, 2, 2, 1, 3, 2, 2, 0, 0xaaab0},
+ {189000000, 189000000, 1, 63, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
+ {189000000, 236250000, 1, 79, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
+ {193250000, 193250000, 3, 289, 2, 0, 0, 1, 1, 2, 2, 0, 0xe00000},
+ {193250000, 241562500, 1, 161, 0, 2, 2, 1, 3, 2, 2, 0, 0xaaab0},
+ {202500000, 202500000, 2, 135, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
+ {202500000, 253125000, 1, 169, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
+ {204750000, 204750000, 4, 273, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
+ {204750000, 255937500, 1, 171, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
+ {208000000, 208000000, 1, 104, 2, 0, 0, 1, 1, 2, 2, 0, 0x0},
+ {208000000, 260000000, 1, 173, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
+ {214750000, 214750000, 1, 107, 2, 0, 0, 1, 1, 2, 2, 0, 0x600000},
+ {214750000, 268437500, 1, 178, 0, 2, 2, 1, 3, 2, 2, 0, 0xf5554f},
+ {218250000, 218250000, 4, 291, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
+ {218250000, 272812500, 1, 91, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
+ {229500000, 229500000, 2, 153, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
+ {229500000, 286875000, 1, 191, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
+ {234000000, 234000000, 1, 39, 0, 0, 0, 1, 0, 1, 1, 0, 0x0},
+ {234000000, 292500000, 1, 195, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
+ {241500000, 241500000, 2, 161, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
+ {241500000, 301875000, 1, 201, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
+ {245250000, 245250000, 4, 327, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
+ {245250000, 306562500, 1, 51, 0, 0, 0, 1, 3, 0, 0, 1, 0x0},
+ {245500000, 245500000, 4, 491, 2, 0, 0, 1, 1, 2, 2, 0, 0x0},
+ {245500000, 306875000, 1, 51, 0, 0, 0, 1, 3, 0, 0, 1, 0x0},
+ {261000000, 261000000, 1, 87, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
+ {261000000, 326250000, 1, 109, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
+ {268250000, 268250000, 9, 402, 0, 0, 0, 1, 0, 1, 1, 0, 0x600000},
+ {268250000, 335312500, 1, 111, 0, 1, 1, 1, 3, 1, 1, 0, 0xc5554f},
+ {268500000, 268500000, 2, 179, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
+ {268500000, 335625000, 1, 56, 0, 0, 0, 1, 3, 0, 0, 1, 0x0},
+ {281250000, 281250000, 4, 375, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
+ {281250000, 351562500, 1, 117, 0, 3, 1, 1, 3, 1, 1, 0, 0x0},
+ {288000000, 288000000, 1, 48, 0, 0, 0, 1, 0, 1, 1, 0, 0x0},
+ {288000000, 360000000, 1, 60, 0, 2, 0, 1, 3, 0, 0, 1, 0x0},
+ {296703000, 296703000, 1, 49, 0, 0, 0, 1, 0, 1, 1, 0, 0x7353f7},
+ {296703000, 370878750, 1, 123, 0, 3, 1, 1, 3, 1, 1, 0, 0xa051eb},
+ {297000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
+ {297000000, 371250000, 4, 495, 0, 3, 1, 1, 3, 1, 1, 0, 0x0},
+ {312250000, 312250000, 9, 468, 0, 0, 0, 1, 0, 1, 1, 0, 0x600000},
+ {312250000, 390312500, 1, 130, 0, 3, 1, 1, 3, 1, 1, 0, 0x1aaab0},
+ {317000000, 317000000, 3, 317, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
+ {317000000, 396250000, 1, 66, 0, 2, 0, 1, 3, 0, 0, 1, 0x0},
+ {319750000, 319750000, 3, 159, 0, 0, 0, 1, 0, 1, 1, 0, 0xe00000},
+ {319750000, 399687500, 3, 199, 0, 2, 0, 1, 3, 0, 0, 1, 0xd80000},
+ {333250000, 333250000, 9, 499, 0, 0, 0, 1, 0, 1, 1, 0, 0xe00000},
+ {333250000, 416562500, 1, 138, 0, 3, 1, 1, 3, 1, 1, 0, 0xdaaab0},
+ {348500000, 348500000, 9, 522, 0, 2, 0, 1, 0, 1, 1, 0, 0xc00000},
+ {348500000, 435625000, 1, 145, 0, 3, 1, 1, 3, 1, 1, 0, 0x35554f},
+ {356500000, 356500000, 9, 534, 0, 2, 0, 1, 0, 1, 1, 0, 0xc00000},
+ {356500000, 445625000, 1, 148, 0, 3, 1, 1, 3, 1, 1, 0, 0x8aaab0},
+ {380500000, 380500000, 9, 570, 0, 2, 0, 1, 0, 1, 1, 0, 0xc00000},
+ {380500000, 475625000, 1, 158, 0, 3, 1, 1, 3, 1, 1, 0, 0x8aaab0},
+ {443250000, 443250000, 1, 73, 0, 2, 0, 1, 0, 1, 1, 0, 0xe00000},
+ {443250000, 554062500, 1, 92, 0, 2, 0, 1, 3, 0, 0, 1, 0x580000},
+ {505250000, 505250000, 9, 757, 0, 2, 0, 1, 0, 1, 1, 0, 0xe00000},
+ {552750000, 552750000, 3, 276, 0, 2, 0, 1, 0, 1, 1, 0, 0x600000},
+ {593407000, 296703500, 3, 296, 0, 1, 1, 1, 0, 1, 1, 0, 0xb41893},
+ {593407000, 370879375, 4, 494, 0, 3, 1, 1, 3, 0, 0, 1, 0x817e4a},
+ {593407000, 593407000, 3, 296, 0, 2, 0, 1, 0, 1, 1, 0, 0xb41893},
+ {594000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 1, 1, 0, 0x0},
+ {594000000, 371250000, 4, 495, 0, 3, 1, 1, 3, 0, 0, 1, 0x0},
+ {594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0x0},
{ /* sentinel */ }
};
@@ -485,6 +634,8 @@ static int inno_hdmi_phy_power_on(struct
dev_dbg(inno->dev, "Inno HDMI PHY Power On\n");
+ inno->plat_data->clk_ops->set_rate(&inno->hw, inno->pixclock, 24000000);
+
ret = clk_prepare_enable(inno->phyclk);
if (ret)
return ret;
@@ -509,6 +660,8 @@ static int inno_hdmi_phy_power_off(struc
clk_disable_unprepare(inno->phyclk);
+ inno->tmdsclock = 0;
+
dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n");
return 0;
@@ -628,6 +781,9 @@ static int inno_hdmi_phy_rk3228_clk_set_
dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",
__func__, rate, tmdsclock);
+ if (inno->pixclock == rate && inno->tmdsclock == tmdsclock)
+ return 0;
+
cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate);
if (IS_ERR(cfg))
return PTR_ERR(cfg);
@@ -670,6 +826,7 @@ static int inno_hdmi_phy_rk3228_clk_set_
}
inno->pixclock = rate;
+ inno->tmdsclock = tmdsclock;
return 0;
}
@@ -714,7 +871,7 @@ unsigned long inno_hdmi_phy_rk3328_clk_r
{
struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
unsigned long frac;
- u8 nd, no_a, no_b, no_c, no_d;
+ u8 nd, no_a, no_b, no_d;
u64 vco;
u16 nf;
@@ -737,9 +894,6 @@ unsigned long inno_hdmi_phy_rk3328_clk_r
no_b = inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_B_MASK;
no_b >>= RK3328_PRE_PLL_PCLK_DIV_B_SHIFT;
no_b += 2;
- no_c = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_C_MASK;
- no_c >>= RK3328_PRE_PLL_PCLK_DIV_C_SHIFT;
- no_c = 1 << no_c;
no_d = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_D_MASK;
do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2));
@@ -784,6 +938,9 @@ static int inno_hdmi_phy_rk3328_clk_set_
dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",
__func__, rate, tmdsclock);
+ if (inno->pixclock == rate && inno->tmdsclock == tmdsclock)
+ return 0;
+
cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate);
if (IS_ERR(cfg))
return PTR_ERR(cfg);
@@ -823,6 +980,7 @@ static int inno_hdmi_phy_rk3328_clk_set_
}
inno->pixclock = rate;
+ inno->tmdsclock = tmdsclock;
return 0;
}
diff -rupN linux.orig/drivers/soc/rockchip/pm_domains.c linux/drivers/soc/rockchip/pm_domains.c
--- linux.orig/drivers/soc/rockchip/pm_domains.c 2024-01-03 20:53:31.383334661 +0000
+++ linux/drivers/soc/rockchip/pm_domains.c 2024-01-03 21:26:02.707011192 +0000
@@ -338,6 +338,29 @@ static int rockchip_pmu_set_idle_request
return 0;
}
+int rockchip_pmu_idle_request(struct device *dev, bool idle)
+{
+ struct generic_pm_domain *genpd;
+ struct rockchip_pm_domain *pd;
+ int ret;
+
+ if (IS_ERR_OR_NULL(dev))
+ return -EINVAL;
+
+ if (IS_ERR_OR_NULL(dev->pm_domain))
+ return -EINVAL;
+
+ genpd = pd_to_genpd(dev->pm_domain);
+ pd = to_rockchip_pd(genpd);
+
+ mutex_lock(&pd->pmu->mutex);
+ ret = rockchip_pmu_set_idle_request(pd, idle);
+ mutex_unlock(&pd->pmu->mutex);
+
+ return ret;
+}
+EXPORT_SYMBOL(rockchip_pmu_idle_request);
+
static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
{
int i;
diff -rupN linux.orig/drivers/staging/media/rkvdec/Kconfig linux/drivers/staging/media/rkvdec/Kconfig
--- linux.orig/drivers/staging/media/rkvdec/Kconfig 2024-01-03 20:53:31.439335419 +0000
+++ linux/drivers/staging/media/rkvdec/Kconfig 2024-01-03 21:33:30.116696710 +0000
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
config VIDEO_ROCKCHIP_VDEC
tristate "Rockchip Video Decoder driver"
- depends on ARCH_ROCKCHIP || COMPILE_TEST
+ depends on ARCH_ROCKCHIP
depends on VIDEO_DEV
select MEDIA_CONTROLLER
select MEDIA_CONTROLLER_REQUEST_API
diff -rupN linux.orig/drivers/staging/media/rkvdec/Makefile linux/drivers/staging/media/rkvdec/Makefile
--- linux.orig/drivers/staging/media/rkvdec/Makefile 2024-01-03 20:53:31.439335419 +0000
+++ linux/drivers/staging/media/rkvdec/Makefile 2024-01-03 21:27:48.647744137 +0000
@@ -1,3 +1,3 @@
obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rockchip-vdec.o
-rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-vp9.o
+rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-hevc.o rkvdec-vp9.o
diff -rupN linux.orig/drivers/staging/media/rkvdec/rkvdec-h264.c linux/drivers/staging/media/rkvdec/rkvdec-h264.c
--- linux.orig/drivers/staging/media/rkvdec/rkvdec-h264.c 2024-01-03 20:53:31.439335419 +0000
+++ linux/drivers/staging/media/rkvdec/rkvdec-h264.c 2024-01-03 21:03:38.389716887 +0000
@@ -655,13 +655,14 @@ static void assemble_hw_pps(struct rkvde
#define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value)
/* write sps */
- WRITE_PPS(0xf, SEQ_PARAMETER_SET_ID);
- WRITE_PPS(0xff, PROFILE_IDC);
- WRITE_PPS(1, CONSTRAINT_SET3_FLAG);
+ WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID);
+ WRITE_PPS(sps->profile_idc, PROFILE_IDC);
+ WRITE_PPS((sps->constraint_set_flags & 1 << 3) ? 1 : 0, CONSTRAINT_SET3_FLAG);
WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC);
WRITE_PPS(sps->bit_depth_luma_minus8, BIT_DEPTH_LUMA);
WRITE_PPS(sps->bit_depth_chroma_minus8, BIT_DEPTH_CHROMA);
- WRITE_PPS(0, QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG);
+ WRITE_PPS(!!(sps->flags & V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS),
+ QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG);
WRITE_PPS(sps->log2_max_frame_num_minus4, LOG2_MAX_FRAME_NUM_MINUS4);
WRITE_PPS(sps->max_num_ref_frames, MAX_NUM_REF_FRAMES);
WRITE_PPS(sps->pic_order_cnt_type, PIC_ORDER_CNT_TYPE);
@@ -688,8 +689,8 @@ static void assemble_hw_pps(struct rkvde
DIRECT_8X8_INFERENCE_FLAG);
/* write pps */
- WRITE_PPS(0xff, PIC_PARAMETER_SET_ID);
- WRITE_PPS(0x1f, PPS_SEQ_PARAMETER_SET_ID);
+ WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID);
+ WRITE_PPS(pps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID);
WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE),
ENTROPY_CODING_MODE_FLAG);
WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT),
@@ -896,9 +897,9 @@ static void config_registers(struct rkvd
dma_addr_t rlc_addr;
dma_addr_t refer_addr;
u32 rlc_len;
- u32 hor_virstride = 0;
- u32 ver_virstride = 0;
- u32 y_virstride = 0;
+ u32 hor_virstride;
+ u32 ver_virstride;
+ u32 y_virstride;
u32 yuv_virstride = 0;
u32 offset;
dma_addr_t dst_addr;
@@ -909,8 +910,8 @@ static void config_registers(struct rkvd
f = &ctx->decoded_fmt;
dst_fmt = &f->fmt.pix_mp;
- hor_virstride = (sps->bit_depth_luma_minus8 + 8) * dst_fmt->width / 8;
- ver_virstride = round_up(dst_fmt->height, 16);
+ hor_virstride = dst_fmt->plane_fmt[0].bytesperline;
+ ver_virstride = dst_fmt->height;
y_virstride = hor_virstride * ver_virstride;
if (sps->chroma_format_idc == 0)
@@ -1031,19 +1032,14 @@ static int rkvdec_h264_validate_sps(stru
{
unsigned int width, height;
- /*
- * TODO: The hardware supports 10-bit and 4:2:2 profiles,
- * but it's currently broken in the driver.
- * Reject them for now, until it's fixed.
- */
- if (sps->chroma_format_idc > 1)
- /* Only 4:0:0 and 4:2:0 are supported */
+ if (sps->chroma_format_idc > 2)
+ /* Only 4:0:0, 4:2:0 and 4:2:2 are supported */
return -EINVAL;
if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
/* Luma and chroma bit depth mismatch */
return -EINVAL;
- if (sps->bit_depth_luma_minus8 != 0)
- /* Only 8-bit is supported */
+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
+ /* Only 8-bit and 10-bit is supported */
return -EINVAL;
width = (sps->pic_width_in_mbs_minus1 + 1) * 16;
@@ -1064,6 +1060,25 @@ static int rkvdec_h264_validate_sps(stru
return 0;
}
+static u32 rkvdec_h264_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
+{
+ const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps;
+
+ if (sps->bit_depth_luma_minus8 == 0) {
+ if (sps->chroma_format_idc == 2)
+ return V4L2_PIX_FMT_NV16;
+ else
+ return V4L2_PIX_FMT_NV12;
+ } else if (sps->bit_depth_luma_minus8 == 2) {
+ if (sps->chroma_format_idc == 2)
+ return V4L2_PIX_FMT_NV20;
+ else
+ return V4L2_PIX_FMT_NV15;
+ }
+
+ return 0;
+}
+
static int rkvdec_h264_start(struct rkvdec_ctx *ctx)
{
struct rkvdec_dev *rkvdec = ctx->dev;
@@ -1185,6 +1200,7 @@ static int rkvdec_h264_try_ctrl(struct r
const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops = {
.adjust_fmt = rkvdec_h264_adjust_fmt,
+ .valid_fmt = rkvdec_h264_valid_fmt,
.start = rkvdec_h264_start,
.stop = rkvdec_h264_stop,
.run = rkvdec_h264_run,
diff -rupN linux.orig/drivers/staging/media/rkvdec/rkvdec-hevc.c linux/drivers/staging/media/rkvdec/rkvdec-hevc.c
--- linux.orig/drivers/staging/media/rkvdec/rkvdec-hevc.c 1970-01-01 00:00:00.000000000 +0000
+++ linux/drivers/staging/media/rkvdec/rkvdec-hevc.c 2024-01-03 21:27:48.651744306 +0000
@@ -0,0 +1,2594 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Rockchip Video Decoder HEVC backend
+ *
+ * Copyright (C) 2019 Collabora, Ltd.
+ * Boris Brezillon <boris.brezillon@collabora.com>
+ *
+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd.
+ * Jeffy Chen <jeffy.chen@rock-chips.com>
+ */
+
+#include <media/v4l2-mem2mem.h>
+#include <linux/bitops.h>
+
+#include "rkvdec.h"
+#include "rkvdec-regs.h"
+
+/* Size in u8/u32 units. */
+#define RKV_CABAC_TABLE_SIZE 27456
+#define RKV_SCALING_LIST_SIZE 1360
+#define RKV_PPS_SIZE (80 / 4)
+#define RKV_PPS_LEN 64
+#define RKV_RPS_SIZE (32 / 4)
+#define RKV_RPS_LEN 600
+
+struct rkvdec_sps_pps_packet {
+ u32 info[RKV_PPS_SIZE];
+};
+
+struct rkvdec_rps_packet {
+ u32 info[RKV_RPS_SIZE];
+};
+
+struct rkvdec_ps_field {
+ u16 offset;
+ u8 len;
+};
+
+#define PS_FIELD(_offset, _len) \
+ ((struct rkvdec_ps_field){ _offset, _len })
+
+/* SPS */
+#define VIDEO_PARAMETER_SET_ID PS_FIELD(0, 4)
+#define SEQ_PARAMETER_SET_ID PS_FIELD(4, 4)
+#define CHROMA_FORMAT_IDC PS_FIELD(8, 2)
+#define PIC_WIDTH_IN_LUMA_SAMPLES PS_FIELD(10, 13)
+#define PIC_HEIGHT_IN_LUMA_SAMPLES PS_FIELD(23, 13)
+#define BIT_DEPTH_LUMA PS_FIELD(36, 4)
+#define BIT_DEPTH_CHROMA PS_FIELD(40, 4)
+#define LOG2_MAX_PIC_ORDER_CNT_LSB PS_FIELD(44, 5)
+#define LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(49, 2)
+#define LOG2_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(51, 3)
+#define LOG2_MIN_TRANSFORM_BLOCK_SIZE PS_FIELD(54, 3)
+#define LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE PS_FIELD(57, 2)
+#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTER PS_FIELD(59, 3)
+#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA PS_FIELD(62, 3)
+#define SCALING_LIST_ENABLED_FLAG PS_FIELD(65, 1)
+#define AMP_ENABLED_FLAG PS_FIELD(66, 1)
+#define SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG PS_FIELD(67, 1)
+#define PCM_ENABLED_FLAG PS_FIELD(68, 1)
+#define PCM_SAMPLE_BIT_DEPTH_LUMA PS_FIELD(69, 4)
+#define PCM_SAMPLE_BIT_DEPTH_CHROMA PS_FIELD(73, 4)
+#define PCM_LOOP_FILTER_DISABLED_FLAG PS_FIELD(77, 1)
+#define LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(78, 3)
+#define LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(81, 3)
+#define NUM_SHORT_TERM_REF_PIC_SETS PS_FIELD(84, 7)
+#define LONG_TERM_REF_PICS_PRESENT_FLAG PS_FIELD(91, 1)
+#define NUM_LONG_TERM_REF_PICS_SPS PS_FIELD(92, 6)
+#define SPS_TEMPORAL_MVP_ENABLED_FLAG PS_FIELD(98, 1)
+#define STRONG_INTRA_SMOOTHING_ENABLED_FLAG PS_FIELD(99, 1)
+/* PPS */
+#define PIC_PARAMETER_SET_ID PS_FIELD(128, 6)
+#define PPS_SEQ_PARAMETER_SET_ID PS_FIELD(134, 4)
+#define DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG PS_FIELD(138, 1)
+#define OUTPUT_FLAG_PRESENT_FLAG PS_FIELD(139, 1)
+#define NUM_EXTRA_SLICE_HEADER_BITS PS_FIELD(140, 13)
+#define SIGN_DATA_HIDING_ENABLED_FLAG PS_FIELD(153, 1)
+#define CABAC_INIT_PRESENT_FLAG PS_FIELD(154, 1)
+#define NUM_REF_IDX_L0_DEFAULT_ACTIVE PS_FIELD(155, 4)
+#define NUM_REF_IDX_L1_DEFAULT_ACTIVE PS_FIELD(159, 4)
+#define INIT_QP_MINUS26 PS_FIELD(163, 7)
+#define CONSTRAINED_INTRA_PRED_FLAG PS_FIELD(170, 1)
+#define TRANSFORM_SKIP_ENABLED_FLAG PS_FIELD(171, 1)
+#define CU_QP_DELTA_ENABLED_FLAG PS_FIELD(172, 1)
+#define LOG2_MIN_CU_QP_DELTA_SIZE PS_FIELD(173, 3)
+#define PPS_CB_QP_OFFSET PS_FIELD(176, 5)
+#define PPS_CR_QP_OFFSET PS_FIELD(181, 5)
+#define PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG PS_FIELD(186, 1)
+#define WEIGHTED_PRED_FLAG PS_FIELD(187, 1)
+#define WEIGHTED_BIPRED_FLAG PS_FIELD(188, 1)
+#define TRANSQUANT_BYPASS_ENABLED_FLAG PS_FIELD(189, 1)
+#define TILES_ENABLED_FLAG PS_FIELD(190, 1)
+#define ENTROPY_CODING_SYNC_ENABLED_FLAG PS_FIELD(191, 1)
+#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG PS_FIELD(192, 1)
+#define LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG PS_FIELD(193, 1)
+#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG PS_FIELD(194, 1)
+#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG PS_FIELD(195, 1)
+#define PPS_BETA_OFFSET_DIV2 PS_FIELD(196, 4)
+#define PPS_TC_OFFSET_DIV2 PS_FIELD(200, 4)
+#define LISTS_MODIFICATION_PRESENT_FLAG PS_FIELD(204, 1)
+#define LOG2_PARALLEL_MERGE_LEVEL PS_FIELD(205, 3)
+#define SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG PS_FIELD(208, 1)
+#define NUM_TILE_COLUMNS PS_FIELD(212, 5)
+#define NUM_TILE_ROWS PS_FIELD(217, 5)
+#define COLUMN_WIDTH(i) PS_FIELD(256 + (i * 8), 8)
+#define ROW_HEIGHT(i) PS_FIELD(416 + (i * 8), 8)
+#define SCALING_LIST_ADDRESS PS_FIELD(592, 32)
+
+/* Data structure describing auxiliary buffer format. */
+struct rkvdec_hevc_priv_tbl {
+ u8 cabac_table[RKV_CABAC_TABLE_SIZE];
+ u8 scaling_list[RKV_SCALING_LIST_SIZE];
+ struct rkvdec_sps_pps_packet param_set[RKV_PPS_LEN];
+ struct rkvdec_rps_packet rps[RKV_RPS_LEN];
+};
+
+struct rkvdec_hevc_run {
+ struct rkvdec_run base;
+ const struct v4l2_ctrl_hevc_slice_params *slices_params;
+ const struct v4l2_ctrl_hevc_decode_params *decode_params;
+ const struct v4l2_ctrl_hevc_sps *sps;
+ const struct v4l2_ctrl_hevc_pps *pps;
+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix;
+ int num_slices;
+};
+
+struct rkvdec_hevc_ctx {
+ struct rkvdec_aux_buf priv_tbl;
+ struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache;
+};
+
+// TODO: refactor scaling list code, was copied 1:1 from mpp
+
+typedef struct ScalingList {
+ /* This is a little wasteful, since sizeID 0 only needs 8 coeffs,
+ * and size ID 3 only has 2 arrays, not 6. */
+ u8 sl[4][6][64];
+ u8 sl_dc[2][6];
+} scalingList_t;
+
+typedef struct ScalingFactor_Model {
+ u8 scalingfactor0[1248];
+ u8 scalingfactor1[96]; /*4X4 TU Rotate, total 16X4*/
+ u8 scalingdc[12]; /*N1005 Vienna Meeting*/
+ u8 reserverd[4]; /*16Bytes align*/
+} scalingFactor_t;
+
+#define SCALING_LIST_SIZE_NUM 4
+
+static void
+hal_record_scaling_list(scalingFactor_t *pScalingFactor_out,
+ scalingList_t *pScalingList)
+{
+ int i;
+ u32 g_scalingListNum_model[SCALING_LIST_SIZE_NUM] = {6, 6, 6, 2}; // from C Model
+ u32 nIndex = 0;
+ u32 sizeId, matrixId, listId;
+ u8 *p = pScalingFactor_out->scalingfactor0;
+ u8 tmpBuf[8 * 8];
+
+ //output non-default scalingFactor Table (1248 BYTES)
+ for (sizeId = 0; sizeId < SCALING_LIST_SIZE_NUM; sizeId++) {
+ for (listId = 0; listId < g_scalingListNum_model[sizeId]; listId++) {
+ if (sizeId < 3) {
+ for (i = 0; i < (sizeId == 0 ? 16 : 64); i++) {
+ pScalingFactor_out->scalingfactor0[nIndex++] = (u8)pScalingList->sl[sizeId][listId][i];
+ }
+ } else {
+ for (i = 0; i < 64; i ++) {
+ pScalingFactor_out->scalingfactor0[nIndex++] = (u8)pScalingList->sl[sizeId][listId][i];
+ }
+ for (i = 0; i < 128; i ++) {
+ pScalingFactor_out->scalingfactor0[nIndex++] = 0;
+ }
+ }
+ }
+ }
+ //output non-default scalingFactor Table Rotation(96 Bytes)
+ nIndex = 0;
+ for (listId = 0; listId < g_scalingListNum_model[0]; listId++) {
+ u8 temp16[16] = {0};
+ for (i = 0; i < 16; i ++) {
+ temp16[i] = (u8)pScalingList->sl[0][listId][i];
+ }
+ for (i = 0; i < 4; i ++) {
+ pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i];
+ pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 4];
+ pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 8];
+ pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 12];
+ }
+ }
+ //output non-default ScalingList_DC_Coeff (12 BYTES)
+ nIndex = 0;
+ for (listId = 0; listId < g_scalingListNum_model[2]; listId++) { //sizeId = 2
+ pScalingFactor_out->scalingdc[nIndex++] = (u8)pScalingList->sl_dc[0][listId];// zrh warning: sl_dc differed from scalingList->getScalingListDC
+ }
+ for (listId = 0; listId < g_scalingListNum_model[3]; listId++) { //sizeId = 3
+ pScalingFactor_out->scalingdc[nIndex++] = (u8)pScalingList->sl_dc[1][listId];// zrh warning: sl_dc differed from scalingList->getScalingListDC
+ pScalingFactor_out->scalingdc[nIndex++] = 0;
+ pScalingFactor_out->scalingdc[nIndex++] = 0;
+ }
+
+ //align 16X address
+ nIndex = 0;
+ for (i = 0; i < 4; i ++) {
+ pScalingFactor_out->reserverd[nIndex++] = 0;
+ }
+
+ //----------------------All above code show the normal store way in HM--------------------------
+ //--------from now on, the scalingfactor0 is rotated 90', the scalingfactor1 is also rotated 90'
+
+ //sizeId == 0
+ for (matrixId = 0; matrixId < 6; matrixId++) {
+ p = pScalingFactor_out->scalingfactor0 + matrixId * 16;
+
+ for (i = 0; i < 4; i++) {
+ tmpBuf[4 * 0 + i] = p[i * 4 + 0];
+ tmpBuf[4 * 1 + i] = p[i * 4 + 1];
+ tmpBuf[4 * 2 + i] = p[i * 4 + 2];
+ tmpBuf[4 * 3 + i] = p[i * 4 + 3];
+ }
+ memcpy(p, tmpBuf, 4 * 4 * sizeof(u8));
+ }
+ //sizeId == 1
+ for (matrixId = 0; matrixId < 6; matrixId++) {
+ p = pScalingFactor_out->scalingfactor0 + 6 * 16 + matrixId * 64;
+
+ for (i = 0; i < 8; i++) {
+ tmpBuf[8 * 0 + i] = p[i * 8 + 0];
+ tmpBuf[8 * 1 + i] = p[i * 8 + 1];
+ tmpBuf[8 * 2 + i] = p[i * 8 + 2];
+ tmpBuf[8 * 3 + i] = p[i * 8 + 3];
+ tmpBuf[8 * 4 + i] = p[i * 8 + 4];
+ tmpBuf[8 * 5 + i] = p[i * 8 + 5];
+ tmpBuf[8 * 6 + i] = p[i * 8 + 6];
+ tmpBuf[8 * 7 + i] = p[i * 8 + 7];
+ }
+ memcpy(p, tmpBuf, 8 * 8 * sizeof(u8));
+ }
+ //sizeId == 2
+ for (matrixId = 0; matrixId < 6; matrixId++) {
+ p = pScalingFactor_out->scalingfactor0 + 6 * 16 + 6 * 64 + matrixId * 64;
+
+ for (i = 0; i < 8; i++) {
+ tmpBuf[8 * 0 + i] = p[i * 8 + 0];
+ tmpBuf[8 * 1 + i] = p[i * 8 + 1];
+ tmpBuf[8 * 2 + i] = p[i * 8 + 2];
+ tmpBuf[8 * 3 + i] = p[i * 8 + 3];
+ tmpBuf[8 * 4 + i] = p[i * 8 + 4];
+ tmpBuf[8 * 5 + i] = p[i * 8 + 5];
+ tmpBuf[8 * 6 + i] = p[i * 8 + 6];
+ tmpBuf[8 * 7 + i] = p[i * 8 + 7];
+ }
+ memcpy(p, tmpBuf, 8 * 8 * sizeof(u8));
+ }
+ //sizeId == 3
+ for (matrixId = 0; matrixId < 6; matrixId++) {
+ p = pScalingFactor_out->scalingfactor0 + 6 * 16 + 6 * 64 + 6 * 64 + matrixId * 64;
+
+ for (i = 0; i < 8; i++) {
+ tmpBuf[8 * 0 + i] = p[i * 8 + 0];
+ tmpBuf[8 * 1 + i] = p[i * 8 + 1];
+ tmpBuf[8 * 2 + i] = p[i * 8 + 2];
+ tmpBuf[8 * 3 + i] = p[i * 8 + 3];
+ tmpBuf[8 * 4 + i] = p[i * 8 + 4];
+ tmpBuf[8 * 5 + i] = p[i * 8 + 5];
+ tmpBuf[8 * 6 + i] = p[i * 8 + 6];
+ tmpBuf[8 * 7 + i] = p[i * 8 + 7];
+ }
+ memcpy(p, tmpBuf, 8 * 8 * sizeof(u8));
+ }
+
+ //sizeId == 0
+ for (matrixId = 0; matrixId < 6; matrixId++) {
+ p = pScalingFactor_out->scalingfactor1 + matrixId * 16;
+
+ for (i = 0; i < 4; i++) {
+ tmpBuf[4 * 0 + i] = p[i * 4 + 0];
+ tmpBuf[4 * 1 + i] = p[i * 4 + 1];
+ tmpBuf[4 * 2 + i] = p[i * 4 + 2];
+ tmpBuf[4 * 3 + i] = p[i * 4 + 3];
+ }
+ memcpy(p, tmpBuf, 4 * 4 * sizeof(u8));
+ }
+}
+
+static const u8 rkvdec_hevc_cabac_table[RKV_CABAC_TABLE_SIZE] = {
+ 0x07, 0x0f, 0x48, 0x58, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, 0x68,
+ 0x48, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40, 0x40, 0x68,
+ 0x58, 0x60, 0x40, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x60, 0x60, 0x50, 0x58,
+ 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50, 0x48, 0x68, 0x60, 0x60,
+ 0x50, 0x58, 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50, 0x48, 0x68,
+ 0x48, 0x48, 0x1f, 0x58, 0x68, 0x68, 0x58, 0x60, 0x60, 0x60, 0x50, 0x50, 0x50, 0x48, 0x58, 0x58,
+ 0x37, 0x07, 0x58, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x50,
+ 0x48, 0x1f, 0x1f, 0x0f, 0x0f, 0x0f, 0x0f, 0x07, 0x0f, 0x48, 0x68, 0x0f, 0x48, 0x68, 0x40, 0x40,
+ 0x50, 0x50, 0x07, 0x40, 0x50, 0x0f, 0x40, 0x48, 0x07, 0x40, 0x27, 0x50, 0x48, 0x48, 0x40, 0x0f,
+ 0x50, 0x37, 0x1f, 0x1f, 0x50, 0x37, 0x40, 0x27, 0x40, 0x07, 0x0f, 0x17, 0x0f, 0x0f, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x07, 0x0f, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, 0x66,
+ 0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x67,
+ 0x57, 0x5e, 0x00, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5f, 0x5f, 0x4f, 0x57,
+ 0x4f, 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x66, 0x5f, 0x5f,
+ 0x4f, 0x57, 0x4f, 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x66,
+ 0x46, 0x48, 0x20, 0x57, 0x67, 0x67, 0x57, 0x5f, 0x5f, 0x5e, 0x4f, 0x4f, 0x4f, 0x47, 0x57, 0x57,
+ 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37, 0x07, 0x57, 0x4f,
+ 0x47, 0x1f, 0x1f, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x67, 0x10, 0x47, 0x67, 0x40, 0x40,
+ 0x4f, 0x4e, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x01, 0x27, 0x4e, 0x47, 0x47, 0x00, 0x0f,
+ 0x4f, 0x37, 0x1f, 0x1f, 0x4f, 0x36, 0x00, 0x27, 0x00, 0x07, 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x07, 0x0e, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0e, 0x40, 0x40, 0x40, 0x0e, 0x64,
+ 0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x66,
+ 0x57, 0x5d, 0x00, 0x1e, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5e, 0x5e, 0x4e, 0x56,
+ 0x4f, 0x07, 0x56, 0x66, 0x4f, 0x56, 0x66, 0x67, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x64, 0x5e, 0x5e,
+ 0x4e, 0x56, 0x4f, 0x07, 0x56, 0x66, 0x4f, 0x56, 0x66, 0x67, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x64,
+ 0x45, 0x48, 0x20, 0x57, 0x66, 0x66, 0x56, 0x5e, 0x5e, 0x5d, 0x4e, 0x4e, 0x4e, 0x46, 0x56, 0x57,
+ 0x36, 0x07, 0x56, 0x46, 0x56, 0x57, 0x36, 0x07, 0x56, 0x46, 0x56, 0x57, 0x36, 0x07, 0x56, 0x4f,
+ 0x47, 0x1e, 0x1e, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x66, 0x10, 0x47, 0x66, 0x40, 0x40,
+ 0x4f, 0x4d, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x03, 0x27, 0x4d, 0x47, 0x46, 0x01, 0x0f,
+ 0x4f, 0x36, 0x1f, 0x1e, 0x4f, 0x34, 0x01, 0x26, 0x00, 0x07, 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x07, 0x0d, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0e, 0x40, 0x40, 0x40, 0x0e, 0x62,
+ 0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x65,
+ 0x57, 0x5c, 0x00, 0x1e, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5d, 0x5d, 0x4e, 0x56,
+ 0x4f, 0x07, 0x56, 0x66, 0x4f, 0x55, 0x65, 0x67, 0x66, 0x65, 0x63, 0x4d, 0x46, 0x62, 0x5d, 0x5d,
+ 0x4e, 0x56, 0x4f, 0x07, 0x56, 0x66, 0x4f, 0x55, 0x65, 0x67, 0x66, 0x65, 0x63, 0x4d, 0x46, 0x62,
+ 0x44, 0x48, 0x20, 0x57, 0x65, 0x65, 0x56, 0x5d, 0x5d, 0x5c, 0x4e, 0x4d, 0x4e, 0x45, 0x56, 0x57,
+ 0x36, 0x07, 0x56, 0x45, 0x56, 0x57, 0x36, 0x07, 0x56, 0x45, 0x56, 0x57, 0x36, 0x07, 0x56, 0x4f,
+ 0x47, 0x1e, 0x1e, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x65, 0x10, 0x47, 0x65, 0x40, 0x40,
+ 0x4f, 0x4c, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x04, 0x27, 0x4c, 0x47, 0x45, 0x01, 0x0f,
+ 0x4f, 0x36, 0x1f, 0x1e, 0x4f, 0x33, 0x01, 0x25, 0x00, 0x07, 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x07, 0x0c, 0x46, 0x56, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0d, 0x40, 0x40, 0x40, 0x0d, 0x60,
+ 0x46, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x01, 0x01, 0x64,
+ 0x56, 0x5b, 0x01, 0x1d, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x46, 0x46, 0x5c, 0x5c, 0x4d, 0x55,
+ 0x4e, 0x07, 0x55, 0x65, 0x4e, 0x54, 0x64, 0x66, 0x65, 0x64, 0x61, 0x4c, 0x45, 0x60, 0x5c, 0x5c,
+ 0x4d, 0x55, 0x4e, 0x07, 0x55, 0x65, 0x4e, 0x54, 0x64, 0x66, 0x65, 0x64, 0x61, 0x4c, 0x45, 0x60,
+ 0x43, 0x49, 0x21, 0x56, 0x64, 0x64, 0x55, 0x5c, 0x5c, 0x5b, 0x4d, 0x4c, 0x4d, 0x44, 0x55, 0x56,
+ 0x35, 0x07, 0x55, 0x44, 0x55, 0x56, 0x35, 0x07, 0x55, 0x44, 0x55, 0x56, 0x35, 0x07, 0x55, 0x4e,
+ 0x46, 0x1d, 0x1d, 0x0f, 0x11, 0x0f, 0x11, 0x07, 0x11, 0x46, 0x64, 0x11, 0x46, 0x64, 0x40, 0x40,
+ 0x4e, 0x4b, 0x09, 0x01, 0x4e, 0x0f, 0x01, 0x46, 0x07, 0x06, 0x27, 0x4b, 0x46, 0x44, 0x02, 0x0f,
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+ 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x4e,
+ 0x07, 0x0e, 0x0e, 0x1c, 0x24, 0x1c, 0x24, 0x09, 0x17, 0x44, 0x41, 0x17, 0x44, 0x41, 0x40, 0x40,
+ 0x40, 0x05, 0x09, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x03, 0x2e, 0x27, 0x1e, 0x07, 0x24, 0x1e, 0x1c,
+ 0x46, 0x17, 0x11, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x22, 0x09, 0x30, 0x22, 0x22, 0x09, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x07, 0x3e, 0x23, 0x06, 0x43, 0x40, 0x43, 0x54, 0x63, 0x2e, 0x40, 0x06, 0x40, 0x40, 0x44, 0x0f,
+ 0x06, 0x1f, 0x40, 0x16, 0x11, 0x1f, 0x2e, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x08, 0x09, 0x1c, 0x07,
+ 0x03, 0x27, 0x29, 0x09, 0x40, 0x46, 0x4b, 0x40, 0x40, 0x40, 0x06, 0x06, 0x04, 0x0b, 0x0c, 0x0b,
+ 0x11, 0x19, 0x04, 0x03, 0x03, 0x1f, 0x04, 0x43, 0x03, 0x03, 0x1f, 0x1b, 0x14, 0x21, 0x04, 0x0b,
+ 0x0c, 0x0b, 0x11, 0x19, 0x04, 0x03, 0x03, 0x1f, 0x04, 0x43, 0x03, 0x03, 0x1f, 0x1b, 0x14, 0x21,
+ 0x24, 0x41, 0x3e, 0x40, 0x4e, 0x40, 0x06, 0x07, 0x06, 0x14, 0x14, 0x2e, 0x0c, 0x11, 0x44, 0x41,
+ 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x4e,
+ 0x07, 0x0e, 0x0e, 0x1c, 0x24, 0x1c, 0x24, 0x09, 0x17, 0x44, 0x41, 0x17, 0x44, 0x41, 0x40, 0x40,
+ 0x40, 0x04, 0x09, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x03, 0x2e, 0x27, 0x1e, 0x07, 0x24, 0x1e, 0x1c,
+ 0x46, 0x16, 0x11, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x23, 0x09, 0x31, 0x23, 0x23, 0x09, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x07, 0x3e, 0x24, 0x06, 0x42, 0x40, 0x44, 0x55, 0x64, 0x2e, 0x40, 0x06, 0x40, 0x40, 0x45, 0x0f,
+ 0x06, 0x21, 0x40, 0x16, 0x12, 0x21, 0x30, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x06, 0x09, 0x1d, 0x07,
+ 0x04, 0x27, 0x2a, 0x09, 0x40, 0x46, 0x4c, 0x40, 0x40, 0x40, 0x06, 0x06, 0x05, 0x0c, 0x0d, 0x0c,
+ 0x12, 0x1a, 0x05, 0x04, 0x04, 0x21, 0x05, 0x42, 0x04, 0x04, 0x21, 0x1c, 0x15, 0x22, 0x05, 0x0c,
+ 0x0d, 0x0c, 0x12, 0x1a, 0x05, 0x04, 0x04, 0x21, 0x05, 0x42, 0x04, 0x04, 0x21, 0x1c, 0x15, 0x22,
+ 0x25, 0x41, 0x3e, 0x40, 0x4e, 0x40, 0x06, 0x07, 0x06, 0x15, 0x15, 0x30, 0x0d, 0x11, 0x45, 0x41,
+ 0x1e, 0x07, 0x40, 0x11, 0x45, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x45, 0x41, 0x1e, 0x07, 0x40, 0x4e,
+ 0x07, 0x0e, 0x0e, 0x1d, 0x25, 0x1d, 0x25, 0x09, 0x17, 0x45, 0x41, 0x17, 0x45, 0x41, 0x40, 0x40,
+ 0x40, 0x03, 0x09, 0x09, 0x40, 0x0f, 0x09, 0x02, 0x02, 0x2e, 0x27, 0x1e, 0x07, 0x25, 0x1e, 0x1d,
+ 0x46, 0x15, 0x11, 0x09, 0x40, 0x0f, 0x09, 0x02, 0x24, 0x09, 0x32, 0x24, 0x24, 0x09, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x07, 0x3e, 0x24, 0x06, 0x42, 0x40, 0x45, 0x56, 0x65, 0x2e, 0x40, 0x06, 0x40, 0x40, 0x46, 0x0f,
+ 0x06, 0x22, 0x40, 0x16, 0x13, 0x22, 0x31, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x04, 0x08, 0x1d, 0x07,
+ 0x04, 0x27, 0x2b, 0x08, 0x40, 0x47, 0x4d, 0x40, 0x40, 0x40, 0x06, 0x06, 0x05, 0x0c, 0x0d, 0x0c,
+ 0x13, 0x1b, 0x05, 0x04, 0x04, 0x22, 0x05, 0x42, 0x04, 0x04, 0x22, 0x1c, 0x15, 0x23, 0x05, 0x0c,
+ 0x0d, 0x0c, 0x13, 0x1b, 0x05, 0x04, 0x04, 0x22, 0x05, 0x42, 0x04, 0x04, 0x22, 0x1c, 0x15, 0x23,
+ 0x25, 0x41, 0x3e, 0x40, 0x4f, 0x40, 0x06, 0x07, 0x06, 0x15, 0x15, 0x31, 0x0d, 0x10, 0x46, 0x41,
+ 0x1e, 0x07, 0x40, 0x10, 0x46, 0x41, 0x1e, 0x07, 0x40, 0x10, 0x46, 0x41, 0x1e, 0x07, 0x40, 0x4f,
+ 0x07, 0x0e, 0x0e, 0x1d, 0x25, 0x1d, 0x25, 0x08, 0x17, 0x46, 0x41, 0x17, 0x46, 0x41, 0x40, 0x40,
+ 0x40, 0x02, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x01, 0x2e, 0x27, 0x1e, 0x07, 0x25, 0x1e, 0x1d,
+ 0x47, 0x13, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x24, 0x08, 0x33, 0x24, 0x24, 0x08, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x07, 0x3e, 0x25, 0x07, 0x41, 0x40, 0x45, 0x56, 0x65, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x46, 0x0f,
+ 0x07, 0x24, 0x40, 0x17, 0x15, 0x24, 0x33, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x03, 0x08, 0x1e, 0x07,
+ 0x05, 0x27, 0x2d, 0x08, 0x40, 0x47, 0x4d, 0x40, 0x40, 0x40, 0x07, 0x07, 0x06, 0x0d, 0x0e, 0x0d,
+ 0x15, 0x1d, 0x06, 0x05, 0x05, 0x24, 0x06, 0x41, 0x05, 0x05, 0x24, 0x1d, 0x16, 0x25, 0x06, 0x0d,
+ 0x0e, 0x0d, 0x15, 0x1d, 0x06, 0x05, 0x05, 0x24, 0x06, 0x41, 0x05, 0x05, 0x24, 0x1d, 0x16, 0x25,
+ 0x26, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x16, 0x16, 0x33, 0x0e, 0x10, 0x46, 0x40,
+ 0x1f, 0x07, 0x40, 0x10, 0x46, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x46, 0x40, 0x1f, 0x07, 0x40, 0x4f,
+ 0x07, 0x0f, 0x0f, 0x1e, 0x26, 0x1e, 0x26, 0x08, 0x17, 0x46, 0x40, 0x17, 0x46, 0x40, 0x40, 0x40,
+ 0x40, 0x02, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x01, 0x2f, 0x27, 0x1f, 0x07, 0x26, 0x1f, 0x1e,
+ 0x47, 0x12, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x25, 0x08, 0x35, 0x25, 0x25, 0x08, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x07, 0x3e, 0x26, 0x07, 0x40, 0x40, 0x46, 0x57, 0x66, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x47, 0x0f,
+ 0x07, 0x26, 0x40, 0x17, 0x16, 0x26, 0x35, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x01, 0x08, 0x1f, 0x07,
+ 0x06, 0x27, 0x2e, 0x08, 0x40, 0x47, 0x4e, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0e, 0x0f, 0x0e,
+ 0x16, 0x1e, 0x07, 0x06, 0x06, 0x26, 0x07, 0x40, 0x06, 0x06, 0x26, 0x1e, 0x17, 0x26, 0x07, 0x0e,
+ 0x0f, 0x0e, 0x16, 0x1e, 0x07, 0x06, 0x06, 0x26, 0x07, 0x40, 0x06, 0x06, 0x26, 0x1e, 0x17, 0x26,
+ 0x27, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x35, 0x0f, 0x10, 0x47, 0x40,
+ 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x4f,
+ 0x07, 0x0f, 0x0f, 0x1f, 0x27, 0x1f, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, 0x40,
+ 0x40, 0x01, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x1f,
+ 0x47, 0x11, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x26, 0x08, 0x36, 0x26, 0x26, 0x08, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x07, 0x3e, 0x27, 0x07, 0x40, 0x40, 0x47, 0x57, 0x67, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x47, 0x0f,
+ 0x07, 0x27, 0x40, 0x17, 0x17, 0x27, 0x37, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x00, 0x08, 0x1f, 0x07,
+ 0x07, 0x27, 0x2f, 0x08, 0x40, 0x47, 0x4f, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0f, 0x0f, 0x0f,
+ 0x17, 0x1f, 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27, 0x07, 0x0f,
+ 0x0f, 0x0f, 0x17, 0x1f, 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27,
+ 0x27, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x37, 0x0f, 0x10, 0x47, 0x40,
+ 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x4f,
+ 0x07, 0x0f, 0x0f, 0x1f, 0x27, 0x1f, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, 0x40,
+ 0x40, 0x00, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x1f,
+ 0x47, 0x10, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x27, 0x08, 0x37, 0x27, 0x27, 0x08, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
+
+static void set_ps_field(u32 *buf, struct rkvdec_ps_field field, u32 value)
+{
+ u8 bit = field.offset % 32, word = field.offset / 32;
+ u64 mask = GENMASK_ULL(bit + field.len - 1, bit);
+ u64 val = ((u64)value << bit) & mask;
+
+ buf[word] &= ~mask;
+ buf[word] |= val;
+ if (bit + field.len > 32) {
+ buf[word + 1] &= ~(mask >> 32);
+ buf[word + 1] |= val >> 32;
+ }
+}
+
+static void assemble_hw_pps(struct rkvdec_ctx *ctx,
+ struct rkvdec_hevc_run *run)
+{
+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
+ const struct v4l2_ctrl_hevc_sps *sps = run->sps;
+ const struct v4l2_ctrl_hevc_pps *pps = run->pps;
+ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu;
+ struct rkvdec_sps_pps_packet *hw_ps;
+ u32 min_cb_log2_size_y, ctb_log2_size_y, ctb_size_y;
+ u32 log2_min_cu_qp_delta_size;
+ dma_addr_t scaling_list_address;
+ u32 scaling_distance;
+ int i;
+
+ /*
+ * HW read the SPS/PPS information from PPS packet index by PPS id.
+ * offset from the base can be calculated by PPS_id * 80 (size per PPS
+ * packet unit). so the driver copy SPS/PPS information to the exact PPS
+ * packet unit for HW accessing.
+ */
+ hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id];
+ memset(hw_ps, 0, sizeof(*hw_ps));
+
+ min_cb_log2_size_y = sps->log2_min_luma_coding_block_size_minus3 + 3;
+ ctb_log2_size_y = min_cb_log2_size_y +
+ sps->log2_diff_max_min_luma_coding_block_size;
+ ctb_size_y = 1 << ctb_log2_size_y;
+
+#define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value)
+ /* write sps */
+ WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID);
+ WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID);
+ WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC);
+ WRITE_PPS(sps->pic_width_in_luma_samples, PIC_WIDTH_IN_LUMA_SAMPLES);
+ WRITE_PPS(sps->pic_height_in_luma_samples, PIC_HEIGHT_IN_LUMA_SAMPLES);
+ WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA);
+ WRITE_PPS(sps->bit_depth_chroma_minus8 + 8, BIT_DEPTH_CHROMA);
+ WRITE_PPS(sps->log2_max_pic_order_cnt_lsb_minus4 + 4,
+ LOG2_MAX_PIC_ORDER_CNT_LSB);
+ WRITE_PPS(sps->log2_diff_max_min_luma_coding_block_size,
+ LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE);
+ WRITE_PPS(sps->log2_min_luma_coding_block_size_minus3 + 3,
+ LOG2_MIN_LUMA_CODING_BLOCK_SIZE);
+ WRITE_PPS(sps->log2_min_luma_transform_block_size_minus2 + 2,
+ LOG2_MIN_TRANSFORM_BLOCK_SIZE);
+ WRITE_PPS(sps->log2_diff_max_min_luma_transform_block_size,
+ LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE);
+ WRITE_PPS(sps->max_transform_hierarchy_depth_inter,
+ MAX_TRANSFORM_HIERARCHY_DEPTH_INTER);
+ WRITE_PPS(sps->max_transform_hierarchy_depth_intra,
+ MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED),
+ SCALING_LIST_ENABLED_FLAG);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED),
+ AMP_ENABLED_FLAG);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET),
+ SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG);
+ if (sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED) {
+ WRITE_PPS(1, PCM_ENABLED_FLAG);
+ WRITE_PPS(sps->pcm_sample_bit_depth_luma_minus1 + 1,
+ PCM_SAMPLE_BIT_DEPTH_LUMA);
+ WRITE_PPS(sps->pcm_sample_bit_depth_chroma_minus1 + 1,
+ PCM_SAMPLE_BIT_DEPTH_CHROMA);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED),
+ PCM_LOOP_FILTER_DISABLED_FLAG);
+ WRITE_PPS(sps->log2_diff_max_min_pcm_luma_coding_block_size,
+ LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE);
+ WRITE_PPS(sps->log2_min_pcm_luma_coding_block_size_minus3 + 3,
+ LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE);
+ }
+ WRITE_PPS(sps->num_short_term_ref_pic_sets, NUM_SHORT_TERM_REF_PIC_SETS);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT),
+ LONG_TERM_REF_PICS_PRESENT_FLAG);
+ WRITE_PPS(sps->num_long_term_ref_pics_sps, NUM_LONG_TERM_REF_PICS_SPS);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED),
+ SPS_TEMPORAL_MVP_ENABLED_FLAG);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED),
+ STRONG_INTRA_SMOOTHING_ENABLED_FLAG);
+
+ /* write pps */
+ WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID);
+ WRITE_PPS(sps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED),
+ DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT),
+ OUTPUT_FLAG_PRESENT_FLAG);
+ WRITE_PPS(pps->num_extra_slice_header_bits, NUM_EXTRA_SLICE_HEADER_BITS);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED),
+ SIGN_DATA_HIDING_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT),
+ CABAC_INIT_PRESENT_FLAG);
+ WRITE_PPS(pps->num_ref_idx_l0_default_active_minus1 + 1,
+ NUM_REF_IDX_L0_DEFAULT_ACTIVE);
+ WRITE_PPS(pps->num_ref_idx_l1_default_active_minus1 + 1,
+ NUM_REF_IDX_L1_DEFAULT_ACTIVE);
+ WRITE_PPS(pps->init_qp_minus26, INIT_QP_MINUS26);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED),
+ CONSTRAINED_INTRA_PRED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED),
+ TRANSFORM_SKIP_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED),
+ CU_QP_DELTA_ENABLED_FLAG);
+
+ log2_min_cu_qp_delta_size = ctb_log2_size_y - pps->diff_cu_qp_delta_depth;
+ WRITE_PPS(log2_min_cu_qp_delta_size, LOG2_MIN_CU_QP_DELTA_SIZE);
+
+ WRITE_PPS(pps->pps_cb_qp_offset, PPS_CB_QP_OFFSET);
+ WRITE_PPS(pps->pps_cr_qp_offset, PPS_CR_QP_OFFSET);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT),
+ PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED),
+ WEIGHTED_PRED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED),
+ WEIGHTED_BIPRED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED),
+ TRANSQUANT_BYPASS_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED),
+ TILES_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED),
+ ENTROPY_CODING_SYNC_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED),
+ PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED),
+ LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED),
+ DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER),
+ PPS_DEBLOCKING_FILTER_DISABLED_FLAG);
+ WRITE_PPS(pps->pps_beta_offset_div2, PPS_BETA_OFFSET_DIV2);
+ WRITE_PPS(pps->pps_tc_offset_div2, PPS_TC_OFFSET_DIV2);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT),
+ LISTS_MODIFICATION_PRESENT_FLAG);
+ WRITE_PPS(pps->log2_parallel_merge_level_minus2 + 2, LOG2_PARALLEL_MERGE_LEVEL);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT),
+ SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG);
+ WRITE_PPS(pps->num_tile_columns_minus1 + 1, NUM_TILE_COLUMNS);
+ WRITE_PPS(pps->num_tile_rows_minus1 + 1, NUM_TILE_ROWS);
+
+ if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) {
+ for (i = 0; i <= pps->num_tile_columns_minus1; i++)
+ WRITE_PPS(pps->column_width_minus1[i], COLUMN_WIDTH(i));
+ for (i = 0; i <= pps->num_tile_rows_minus1; i++)
+ WRITE_PPS(pps->row_height_minus1[i], ROW_HEIGHT(i));
+ } else {
+ WRITE_PPS(((sps->pic_width_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1,
+ COLUMN_WIDTH(0));
+ WRITE_PPS(((sps->pic_height_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1,
+ ROW_HEIGHT(0));
+ }
+
+ scaling_distance = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list);
+ scaling_list_address = hevc_ctx->priv_tbl.dma + scaling_distance;
+ WRITE_PPS(scaling_list_address, SCALING_LIST_ADDRESS);
+}
+
+static void assemble_hw_rps(struct rkvdec_ctx *ctx,
+ struct rkvdec_hevc_run *run)
+{
+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
+ const struct v4l2_ctrl_hevc_sps *sps = run->sps;
+ const struct v4l2_ctrl_hevc_slice_params *sl_params;
+ const struct v4l2_hevc_dpb_entry *dpb;
+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
+ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu;
+ struct rkvdec_rps_packet *hw_ps;
+ int i, j;
+ unsigned int lowdelay;
+
+#define WRITE_RPS(value, field) set_ps_field(hw_ps->info, field, value)
+
+#define REF_PIC_LONG_TERM_L0(i) PS_FIELD(i * 5, 1)
+#define REF_PIC_IDX_L0(i) PS_FIELD(1 + (i * 5), 4)
+#define REF_PIC_LONG_TERM_L1(i) PS_FIELD((i < 5 ? 75 : 132) + (i * 5), 1)
+#define REF_PIC_IDX_L1(i) PS_FIELD((i < 4 ? 76 : 128) + (i * 5), 4)
+
+#define LOWDELAY PS_FIELD(182, 1)
+#define LONG_TERM_RPS_BIT_OFFSET PS_FIELD(183, 10)
+#define SHORT_TERM_RPS_BIT_OFFSET PS_FIELD(193, 9)
+#define NUM_RPS_POC PS_FIELD(202, 4)
+
+ for (j = 0; j < run->num_slices; j++) {
+ uint st_bit_offset = 0;
+ uint num_l0_refs = 0;
+ uint num_l1_refs = 0;
+
+ sl_params = &run->slices_params[j];
+ dpb = decode_params->dpb;
+
+ if (sl_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) {
+ num_l0_refs = sl_params->num_ref_idx_l0_active_minus1 + 1;
+
+ if (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_B)
+ num_l1_refs = sl_params->num_ref_idx_l1_active_minus1 + 1;
+
+ lowdelay = 1;
+ } else {
+ lowdelay = 0;
+ }
+
+ hw_ps = &priv_tbl->rps[j];
+ memset(hw_ps, 0, sizeof(*hw_ps));
+
+ for (i = 0; i < num_l0_refs; i++) {
+ WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE),
+ REF_PIC_LONG_TERM_L0(i));
+ WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i));
+
+ if (dpb[sl_params->ref_idx_l0[i]].pic_order_cnt_val > sl_params->slice_pic_order_cnt)
+ lowdelay = 0;
+
+ }
+
+ for (i = 0; i < num_l1_refs; i++) {
+ WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE),
+ REF_PIC_LONG_TERM_L1(i));
+ WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i));
+
+ if (dpb[sl_params->ref_idx_l1[i]].pic_order_cnt_val > sl_params->slice_pic_order_cnt)
+ lowdelay = 0;
+ }
+
+ WRITE_RPS(lowdelay, LOWDELAY);
+
+ if (!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC)) {
+ if (sl_params->short_term_ref_pic_set_size)
+ st_bit_offset = sl_params->short_term_ref_pic_set_size;
+ else if (sps->num_short_term_ref_pic_sets > 1)
+ st_bit_offset = fls(sps->num_short_term_ref_pic_sets - 1);
+ }
+
+ WRITE_RPS(st_bit_offset + sl_params->long_term_ref_pic_set_size,
+ LONG_TERM_RPS_BIT_OFFSET);
+ WRITE_RPS(sl_params->short_term_ref_pic_set_size,
+ SHORT_TERM_RPS_BIT_OFFSET);
+
+ WRITE_RPS(decode_params->num_poc_st_curr_before +
+ decode_params->num_poc_st_curr_after +
+ decode_params->num_poc_lt_curr,
+ NUM_RPS_POC);
+ }
+}
+
+static void assemble_hw_scaling_list(struct rkvdec_ctx *ctx,
+ struct rkvdec_hevc_run *run)
+{
+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling = run->scaling_matrix;
+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
+ struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu;
+ u8 *dst;
+ scalingList_t sl;
+ int i, j;
+
+ if (!memcmp((void*)&hevc_ctx->scaling_matrix_cache, scaling,
+ sizeof(struct v4l2_ctrl_hevc_scaling_matrix)))
+ return;
+
+ memset(&sl, 0, sizeof(scalingList_t));
+
+ for (i = 0; i < 6; i++) {
+ for (j = 0; j < 16; j++)
+ sl.sl[0][i][j] = scaling->scaling_list_4x4[i][j];
+ for (j = 0; j < 64; j++) {
+ sl.sl[1][i][j] = scaling->scaling_list_8x8[i][j];
+ sl.sl[2][i][j] = scaling->scaling_list_16x16[i][j];
+ if (i < 2)
+ sl.sl[3][i][j] = scaling->scaling_list_32x32[i][j];
+ }
+ sl.sl_dc[0][i] = scaling->scaling_list_dc_coef_16x16[i];
+ if (i < 2)
+ sl.sl_dc[1][i] = scaling->scaling_list_dc_coef_32x32[i];
+ }
+
+ dst = tbl->scaling_list;
+ hal_record_scaling_list((scalingFactor_t *)dst, &sl);
+
+ memcpy((void*)&hevc_ctx->scaling_matrix_cache, scaling,
+ sizeof(struct v4l2_ctrl_hevc_scaling_matrix));
+}
+
+static struct vb2_buffer *
+get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run,
+ unsigned int dpb_idx)
+{
+ struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx;
+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb;
+ struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q;
+ struct vb2_buffer *vb2_buf = NULL;
+
+ if (dpb_idx < decode_params->num_active_dpb_entries)
+ vb2_buf = vb2_find_buffer(cap_q, dpb[dpb_idx].timestamp);
+
+ /*
+ * If a DPB entry is unused or invalid, address of current destination
+ * buffer is returned.
+ */
+ if (!vb2_buf)
+ return &run->base.bufs.dst->vb2_buf;
+
+ return vb2_buf;
+}
+
+static void config_registers(struct rkvdec_ctx *ctx,
+ struct rkvdec_hevc_run *run)
+{
+ struct rkvdec_dev *rkvdec = ctx->dev;
+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
+ const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0];
+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb;
+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
+ dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma;
+ const struct v4l2_pix_format_mplane *dst_fmt;
+ struct vb2_v4l2_buffer *src_buf = run->base.bufs.src;
+ struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst;
+ const struct v4l2_format *f;
+ dma_addr_t rlc_addr;
+ dma_addr_t refer_addr;
+ u32 rlc_len;
+ u32 hor_virstride;
+ u32 ver_virstride;
+ u32 y_virstride;
+ u32 uv_virstride;
+ u32 yuv_virstride;
+ u32 offset;
+ dma_addr_t dst_addr;
+ u32 reg, i;
+
+ reg = RKVDEC_MODE(RKVDEC_MODE_HEVC);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_SYSCTRL);
+
+ f = &ctx->decoded_fmt;
+ dst_fmt = &f->fmt.pix_mp;
+ hor_virstride = dst_fmt->plane_fmt[0].bytesperline;
+ ver_virstride = dst_fmt->height;
+ y_virstride = hor_virstride * ver_virstride;
+ uv_virstride = y_virstride / 2;
+ yuv_virstride = y_virstride + uv_virstride;
+
+ reg = RKVDEC_Y_HOR_VIRSTRIDE(hor_virstride / 16) |
+ RKVDEC_UV_HOR_VIRSTRIDE(hor_virstride / 16) |
+ RKVDEC_SLICE_NUM_LOWBITS(run->num_slices);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_PICPAR);
+
+ /* config rlc base address */
+ rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
+ writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE);
+
+ rlc_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
+ reg = RKVDEC_STRM_LEN(round_up(rlc_len, 16) + 64);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_STRM_LEN);
+
+ /* config cabac table */
+ offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table);
+ writel_relaxed(priv_start_addr + offset,
+ rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE);
+
+ /* config output base address */
+ dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
+ writel_relaxed(dst_addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE);
+
+ reg = RKVDEC_Y_VIRSTRIDE(y_virstride / 16);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE);
+
+ reg = RKVDEC_YUV_VIRSTRIDE(yuv_virstride / 16);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE);
+
+ /* config ref pic address */
+ for (i = 0; i < 15; i++) {
+ struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i);
+
+ if (i < 4 && decode_params->num_active_dpb_entries) {
+ reg = GENMASK(decode_params->num_active_dpb_entries - 1, 0);
+ reg = (reg >> (i * 4)) & 0xf;
+ } else
+ reg = 0;
+
+ refer_addr = vb2_dma_contig_plane_dma_addr(vb_buf, 0);
+ writel_relaxed(refer_addr | reg,
+ rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i));
+
+ reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ? dpb[i].pic_order_cnt_val : 0);
+ writel_relaxed(reg,
+ rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i));
+ }
+
+ reg = RKVDEC_CUR_POC(sl_params->slice_pic_order_cnt);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0);
+
+ /* config hw pps address */
+ offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set);
+ writel_relaxed(priv_start_addr + offset,
+ rkvdec->regs + RKVDEC_REG_PPS_BASE);
+
+ /* config hw rps address */
+ offset = offsetof(struct rkvdec_hevc_priv_tbl, rps);
+ writel_relaxed(priv_start_addr + offset,
+ rkvdec->regs + RKVDEC_REG_RPS_BASE);
+
+ reg = RKVDEC_AXI_DDR_RDATA(0);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_RDATA);
+
+ reg = RKVDEC_AXI_DDR_WDATA(0);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_WDATA);
+}
+
+#define RKVDEC_HEVC_MAX_DEPTH_IN_BYTES 2
+
+static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx,
+ struct v4l2_format *f)
+{
+ struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp;
+
+ fmt->num_planes = 1;
+ if (!fmt->plane_fmt[0].sizeimage)
+ fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height *
+ RKVDEC_HEVC_MAX_DEPTH_IN_BYTES;
+ return 0;
+}
+
+static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx,
+ const struct v4l2_ctrl_hevc_sps *sps)
+{
+ if (sps->chroma_format_idc > 1)
+ /* Only 4:0:0 and 4:2:0 are supported */
+ return -EINVAL;
+ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
+ /* Luma and chroma bit depth mismatch */
+ return -EINVAL;
+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
+ /* Only 8-bit and 10-bit is supported */
+ return -EINVAL;
+
+ if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width ||
+ sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height)
+ return -EINVAL;
+
+ return 0;
+}
+
+static u32 rkvdec_hevc_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
+{
+ const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps;
+
+ if (sps->bit_depth_luma_minus8 == 2)
+ return V4L2_PIX_FMT_NV15;
+ else
+ return V4L2_PIX_FMT_NV12;
+}
+
+static int rkvdec_hevc_start(struct rkvdec_ctx *ctx)
+{
+ struct rkvdec_dev *rkvdec = ctx->dev;
+ struct rkvdec_hevc_priv_tbl *priv_tbl;
+ struct rkvdec_hevc_ctx *hevc_ctx;
+ struct v4l2_ctrl *ctrl;
+ int ret;
+
+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
+ V4L2_CID_STATELESS_HEVC_SPS);
+ if (!ctrl)
+ return -EINVAL;
+
+ ret = rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps);
+ if (ret)
+ return ret;
+
+ hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL);
+ if (!hevc_ctx)
+ return -ENOMEM;
+
+
+ priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl),
+ &hevc_ctx->priv_tbl.dma, GFP_KERNEL);
+ if (!priv_tbl) {
+ ret = -ENOMEM;
+ goto err_free_ctx;
+ }
+
+ hevc_ctx->priv_tbl.size = sizeof(*priv_tbl);
+ hevc_ctx->priv_tbl.cpu = priv_tbl;
+ memset(priv_tbl, 0, sizeof(*priv_tbl));
+ memcpy(priv_tbl->cabac_table, rkvdec_hevc_cabac_table,
+ sizeof(rkvdec_hevc_cabac_table));
+
+ ctx->priv = hevc_ctx;
+ return 0;
+
+err_free_ctx:
+ kfree(hevc_ctx);
+ return ret;
+}
+
+static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx)
+{
+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
+ struct rkvdec_dev *rkvdec = ctx->dev;
+
+ dma_free_coherent(rkvdec->dev, hevc_ctx->priv_tbl.size,
+ hevc_ctx->priv_tbl.cpu, hevc_ctx->priv_tbl.dma);
+ kfree(hevc_ctx);
+}
+
+static void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx,
+ struct rkvdec_hevc_run *run)
+{
+ struct v4l2_ctrl *ctrl;
+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
+ V4L2_CID_STATELESS_HEVC_DECODE_PARAMS);
+ run->decode_params = ctrl ? ctrl->p_cur.p : NULL;
+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
+ V4L2_CID_STATELESS_HEVC_SLICE_PARAMS);
+ run->slices_params = ctrl ? ctrl->p_cur.p : NULL;
+ run->num_slices = ctrl->new_elems;
+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
+ V4L2_CID_STATELESS_HEVC_SPS);
+ run->sps = ctrl ? ctrl->p_cur.p : NULL;
+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
+ V4L2_CID_STATELESS_HEVC_PPS);
+ run->pps = ctrl ? ctrl->p_cur.p : NULL;
+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
+ V4L2_CID_STATELESS_HEVC_SCALING_MATRIX);
+ run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL;
+
+ rkvdec_run_preamble(ctx, &run->base);
+}
+
+static int rkvdec_hevc_run(struct rkvdec_ctx *ctx)
+{
+ struct rkvdec_dev *rkvdec = ctx->dev;
+ struct rkvdec_hevc_run run;
+
+ rkvdec_hevc_run_preamble(ctx, &run);
+
+ assemble_hw_scaling_list(ctx, &run);
+ assemble_hw_pps(ctx, &run);
+ assemble_hw_rps(ctx, &run);
+ config_registers(ctx, &run);
+
+ rkvdec_run_postamble(ctx, &run.base);
+
+ // sw_cabac_error_e - cabac error enable
+ writel_relaxed(0xfdfffffd, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN);
+ // slice end error enable = BIT(28)
+ // frame end error enable = BIT(29)
+ writel_relaxed(0x30000000, rkvdec->regs + RKVDEC_REG_H264_ERR_E);
+
+ schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000));
+
+ writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND);
+ writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND);
+
+ /* Start decoding! */
+ writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E |
+ RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E,
+ rkvdec->regs + RKVDEC_REG_INTERRUPT);
+
+ return 0;
+}
+
+static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
+{
+ if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS)
+ return rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps);
+
+ return 0;
+}
+
+const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = {
+ .adjust_fmt = rkvdec_hevc_adjust_fmt,
+ .start = rkvdec_hevc_start,
+ .stop = rkvdec_hevc_stop,
+ .run = rkvdec_hevc_run,
+ .try_ctrl = rkvdec_hevc_try_ctrl,
+ .valid_fmt = rkvdec_hevc_valid_fmt,
+};
diff -rupN linux.orig/drivers/staging/media/rkvdec/rkvdec-regs.h linux/drivers/staging/media/rkvdec/rkvdec-regs.h
--- linux.orig/drivers/staging/media/rkvdec/rkvdec-regs.h 2024-01-03 20:53:31.439335419 +0000
+++ linux/drivers/staging/media/rkvdec/rkvdec-regs.h 2024-01-03 21:27:48.651744306 +0000
@@ -28,6 +28,11 @@
#define RKVDEC_SOFTRST_EN_P BIT(20)
#define RKVDEC_FORCE_SOFTRESET_VALID BIT(21)
#define RKVDEC_SOFTRESET_RDY BIT(22)
+#define RKVDEC_ERR_MASK (RKVDEC_BUS_STA \
+ | RKVDEC_ERR_STA \
+ | RKVDEC_TIMEOUT_STA \
+ | RKVDEC_BUF_EMPTY_STA \
+ | RKVDEC_COLMV_REF_ERR_STA )
#define RKVDEC_REG_SYSCTRL 0x008
#define RKVDEC_IN_ENDIAN BIT(0)
@@ -43,6 +48,7 @@
#define RKVDEC_RLC_MODE BIT(11)
#define RKVDEC_STRM_START_BIT(x) (((x) & 0x7f) << 12)
#define RKVDEC_MODE(x) (((x) & 0x03) << 20)
+#define RKVDEC_MODE_HEVC 0
#define RKVDEC_MODE_H264 1
#define RKVDEC_MODE_VP9 2
#define RKVDEC_RPS_MODE BIT(24)
@@ -217,6 +223,8 @@
#define RKVDEC_REG_H264_ERR_E 0x134
#define RKVDEC_H264_ERR_EN_HIGHBITS(x) ((x) & 0x3fffffff)
+#define RKVDEC_QOS_CTRL 0x18C
+
#define RKVDEC_REG_PREF_LUMA_CACHE_COMMAND 0x410
#define RKVDEC_REG_PREF_CHR_CACHE_COMMAND 0x450
diff -rupN linux.orig/drivers/staging/media/rkvdec/rkvdec-vp9.c linux/drivers/staging/media/rkvdec/rkvdec-vp9.c
--- linux.orig/drivers/staging/media/rkvdec/rkvdec-vp9.c 2024-01-03 20:53:31.439335419 +0000
+++ linux/drivers/staging/media/rkvdec/rkvdec-vp9.c 2024-01-03 21:26:02.711011382 +0000
@@ -804,6 +804,7 @@ static int rkvdec_vp9_run(struct rkvdec_
struct rkvdec_dev *rkvdec = ctx->dev;
struct rkvdec_vp9_run run = { };
int ret;
+ u32 reg;
ret = rkvdec_vp9_run_preamble(ctx, &run);
if (ret) {
@@ -825,6 +826,13 @@ static int rkvdec_vp9_run(struct rkvdec_
writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND);
writel(0xe, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN);
+
+ /* disable QOS for RK3328 - no effect on other SoCs */
+ reg = readl(rkvdec->regs + RKVDEC_QOS_CTRL);
+ reg |= 0xFFFF;
+ reg &= (~BIT(12));
+ writel(reg, rkvdec->regs + RKVDEC_QOS_CTRL);
+
/* Start decoding! */
writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E |
RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E,
diff -rupN linux.orig/drivers/staging/media/rkvdec/rkvdec.c linux/drivers/staging/media/rkvdec/rkvdec.c
--- linux.orig/drivers/staging/media/rkvdec/rkvdec.c 2024-01-03 20:53:31.439335419 +0000
+++ linux/drivers/staging/media/rkvdec/rkvdec.c 2024-01-03 21:31:44.568991334 +0000
@@ -10,12 +10,16 @@
*/
#include <linux/clk.h>
+#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <linux/rockchip_pmu.h>
#include <linux/slab.h>
#include <linux/videodev2.h>
#include <linux/workqueue.h>
@@ -27,19 +31,67 @@
#include "rkvdec.h"
#include "rkvdec-regs.h"
+static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx,
+ struct v4l2_pix_format_mplane *pix_mp)
+{
+ v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat,
+ ALIGN(pix_mp->width, 64), pix_mp->height);
+ pix_mp->plane_fmt[0].sizeimage += 128 *
+ DIV_ROUND_UP(pix_mp->width, 16) *
+ DIV_ROUND_UP(pix_mp->height, 16);
+ pix_mp->field = V4L2_FIELD_NONE;
+}
+
+static u32 rkvdec_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
+{
+ const struct rkvdec_coded_fmt_desc *coded_desc = ctx->coded_fmt_desc;
+
+ if (coded_desc->ops->valid_fmt)
+ return coded_desc->ops->valid_fmt(ctx, ctrl);
+
+ return ctx->valid_fmt;
+}
+
static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
{
struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
const struct rkvdec_coded_fmt_desc *desc = ctx->coded_fmt_desc;
- if (desc->ops->try_ctrl)
- return desc->ops->try_ctrl(ctx, ctrl);
+ if (desc->ops->try_ctrl) {
+ int ret;
+ ret = desc->ops->try_ctrl(ctx, ctrl);
+ if (ret)
+ return ret;
+ }
+
+ if (ctx->valid_fmt && ctx->valid_fmt != rkvdec_valid_fmt(ctx, ctrl))
+ /* Only current valid format */
+ return -EINVAL;
+
+ return 0;
+}
+
+static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl)
+{
+ struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
+
+ if (!ctx->valid_fmt) {
+ ctx->valid_fmt = rkvdec_valid_fmt(ctx, ctrl);
+ if (ctx->valid_fmt) {
+ struct v4l2_pix_format_mplane *pix_mp;
+
+ pix_mp = &ctx->decoded_fmt.fmt.pix_mp;
+ pix_mp->pixelformat = ctx->valid_fmt;
+ rkvdec_fill_decoded_pixfmt(ctx, pix_mp);
+ }
+ }
return 0;
}
static const struct v4l2_ctrl_ops rkvdec_ctrl_ops = {
.try_ctrl = rkvdec_try_ctrl,
+ .s_ctrl = rkvdec_s_ctrl,
};
static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = {
@@ -83,13 +135,72 @@ static const struct rkvdec_ctrl_desc rkv
},
};
+static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = {
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_SLICE_PARAMS,
+ .cfg.flags = V4L2_CTRL_FLAG_DYNAMIC_ARRAY,
+ .cfg.type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS,
+ .cfg.dims = { 600 },
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_SPS,
+ .cfg.ops = &rkvdec_ctrl_ops,
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_PPS,
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX,
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS,
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE,
+ .cfg.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
+ .cfg.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
+ .cfg.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_START_CODE,
+ .cfg.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
+ .cfg.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
+ .cfg.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
+ },
+ {
+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
+ .cfg.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
+ },
+ {
+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1,
+ },
+};
+
+static const struct rkvdec_ctrls rkvdec_hevc_ctrls = {
+ .ctrls = rkvdec_hevc_ctrl_descs,
+ .num_ctrls = ARRAY_SIZE(rkvdec_hevc_ctrl_descs),
+};
+
+static const u32 rkvdec_hevc_decoded_fmts[] = {
+ V4L2_PIX_FMT_NV12,
+ V4L2_PIX_FMT_NV15,
+};
+
+
static const struct rkvdec_ctrls rkvdec_h264_ctrls = {
.ctrls = rkvdec_h264_ctrl_descs,
.num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs),
};
-static const u32 rkvdec_h264_vp9_decoded_fmts[] = {
+static const u32 rkvdec_h264_decoded_fmts[] = {
V4L2_PIX_FMT_NV12,
+ V4L2_PIX_FMT_NV15,
+ V4L2_PIX_FMT_NV16,
+ V4L2_PIX_FMT_NV20,
};
static const struct rkvdec_ctrl_desc rkvdec_vp9_ctrl_descs[] = {
@@ -112,8 +223,28 @@ static const struct rkvdec_ctrls rkvdec_
.num_ctrls = ARRAY_SIZE(rkvdec_vp9_ctrl_descs),
};
+static const u32 rkvdec_vp9_decoded_fmts[] = {
+ V4L2_PIX_FMT_NV12,
+};
+
static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
{
+ .fourcc = V4L2_PIX_FMT_HEVC_SLICE,
+ .frmsize = {
+ .min_width = 64,
+ .max_width = 4096,
+ .step_width = 64,
+ .min_height = 64,
+ .max_height = 2304,
+ .step_height = 16,
+ },
+ .ctrls = &rkvdec_hevc_ctrls,
+ .ops = &rkvdec_hevc_fmt_ops,
+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts),
+ .decoded_fmts = rkvdec_hevc_decoded_fmts,
+ .capability = RKVDEC_CAPABILITY_HEVC,
+ },
+ {
.fourcc = V4L2_PIX_FMT_H264_SLICE,
.frmsize = {
.min_width = 48,
@@ -125,9 +256,10 @@ static const struct rkvdec_coded_fmt_des
},
.ctrls = &rkvdec_h264_ctrls,
.ops = &rkvdec_h264_fmt_ops,
- .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_vp9_decoded_fmts),
- .decoded_fmts = rkvdec_h264_vp9_decoded_fmts,
+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts),
+ .decoded_fmts = rkvdec_h264_decoded_fmts,
.subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF,
+ .capability = RKVDEC_CAPABILITY_H264,
},
{
.fourcc = V4L2_PIX_FMT_VP9_FRAME,
@@ -141,18 +273,33 @@ static const struct rkvdec_coded_fmt_des
},
.ctrls = &rkvdec_vp9_ctrls,
.ops = &rkvdec_vp9_fmt_ops,
- .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_vp9_decoded_fmts),
- .decoded_fmts = rkvdec_h264_vp9_decoded_fmts,
- }
+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts),
+ .decoded_fmts = rkvdec_vp9_decoded_fmts,
+ .capability = RKVDEC_CAPABILITY_VP9,
+ },
};
static const struct rkvdec_coded_fmt_desc *
-rkvdec_find_coded_fmt_desc(u32 fourcc)
+rkvdec_default_coded_fmt_desc(unsigned int capabilities)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) {
+ if (rkvdec_coded_fmts[i].capability & capabilities)
+ return &rkvdec_coded_fmts[i];
+ }
+
+ return NULL;
+}
+
+static const struct rkvdec_coded_fmt_desc *
+rkvdec_find_coded_fmt_desc(u32 fourcc, unsigned int capabilities)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) {
- if (rkvdec_coded_fmts[i].fourcc == fourcc)
+ if (rkvdec_coded_fmts[i].fourcc == fourcc &&
+ (rkvdec_coded_fmts[i].capability & capabilities))
return &rkvdec_coded_fmts[i];
}
@@ -175,7 +322,7 @@ static void rkvdec_reset_coded_fmt(struc
{
struct v4l2_format *f = &ctx->coded_fmt;
- ctx->coded_fmt_desc = &rkvdec_coded_fmts[0];
+ ctx->coded_fmt_desc = rkvdec_default_coded_fmt_desc(ctx->dev->capabilities);
rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->fourcc);
f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
@@ -190,26 +337,25 @@ static void rkvdec_reset_decoded_fmt(str
{
struct v4l2_format *f = &ctx->decoded_fmt;
+ ctx->valid_fmt = 0;
rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]);
f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
- v4l2_fill_pixfmt_mp(&f->fmt.pix_mp,
- ctx->coded_fmt_desc->decoded_fmts[0],
- ctx->coded_fmt.fmt.pix_mp.width,
- ctx->coded_fmt.fmt.pix_mp.height);
- f->fmt.pix_mp.plane_fmt[0].sizeimage += 128 *
- DIV_ROUND_UP(f->fmt.pix_mp.width, 16) *
- DIV_ROUND_UP(f->fmt.pix_mp.height, 16);
+ f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width;
+ f->fmt.pix_mp.height = ctx->coded_fmt.fmt.pix_mp.height;
+ rkvdec_fill_decoded_pixfmt(ctx, &f->fmt.pix_mp);
}
static int rkvdec_enum_framesizes(struct file *file, void *priv,
struct v4l2_frmsizeenum *fsize)
{
const struct rkvdec_coded_fmt_desc *fmt;
+ struct rkvdec_dev *rkvdec = video_drvdata(file);
if (fsize->index != 0)
return -EINVAL;
- fmt = rkvdec_find_coded_fmt_desc(fsize->pixel_format);
+ fmt = rkvdec_find_coded_fmt_desc(fsize->pixel_format,
+ rkvdec->capabilities);
if (!fmt)
return -EINVAL;
@@ -249,13 +395,17 @@ static int rkvdec_try_capture_fmt(struct
if (WARN_ON(!coded_desc))
return -EINVAL;
- for (i = 0; i < coded_desc->num_decoded_fmts; i++) {
- if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat)
- break;
- }
+ if (ctx->valid_fmt) {
+ pix_mp->pixelformat = ctx->valid_fmt;
+ } else {
+ for (i = 0; i < coded_desc->num_decoded_fmts; i++) {
+ if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat)
+ break;
+ }
- if (i == coded_desc->num_decoded_fmts)
- pix_mp->pixelformat = coded_desc->decoded_fmts[0];
+ if (i == coded_desc->num_decoded_fmts)
+ pix_mp->pixelformat = coded_desc->decoded_fmts[0];
+ }
/* Always apply the frmsize constraint of the coded end. */
pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width);
@@ -264,13 +414,7 @@ static int rkvdec_try_capture_fmt(struct
&pix_mp->height,
&coded_desc->frmsize);
- v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat,
- pix_mp->width, pix_mp->height);
- pix_mp->plane_fmt[0].sizeimage +=
- 128 *
- DIV_ROUND_UP(pix_mp->width, 16) *
- DIV_ROUND_UP(pix_mp->height, 16);
- pix_mp->field = V4L2_FIELD_NONE;
+ rkvdec_fill_decoded_pixfmt(ctx, pix_mp);
return 0;
}
@@ -282,10 +426,11 @@ static int rkvdec_try_output_fmt(struct
struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv);
const struct rkvdec_coded_fmt_desc *desc;
- desc = rkvdec_find_coded_fmt_desc(pix_mp->pixelformat);
+ desc = rkvdec_find_coded_fmt_desc(pix_mp->pixelformat,
+ ctx->dev->capabilities);
if (!desc) {
- pix_mp->pixelformat = rkvdec_coded_fmts[0].fourcc;
- desc = &rkvdec_coded_fmts[0];
+ desc = rkvdec_default_coded_fmt_desc(ctx->dev->capabilities);
+ pix_mp->pixelformat = desc->fourcc;
}
v4l2_apply_frmsize_constraints(&pix_mp->width,
@@ -325,6 +470,7 @@ static int rkvdec_s_capture_fmt(struct f
return ret;
ctx->decoded_fmt = *f;
+ ctx->valid_fmt = f->fmt.pix_mp.pixelformat;
return 0;
}
@@ -362,7 +508,8 @@ static int rkvdec_s_output_fmt(struct fi
if (ret)
return ret;
- desc = rkvdec_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat);
+ desc = rkvdec_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat,
+ ctx->dev->capabilities);
if (!desc)
return -EINVAL;
ctx->coded_fmt_desc = desc;
@@ -413,7 +560,10 @@ static int rkvdec_g_capture_fmt(struct f
static int rkvdec_enum_output_fmt(struct file *file, void *priv,
struct v4l2_fmtdesc *f)
{
- if (f->index >= ARRAY_SIZE(rkvdec_coded_fmts))
+ struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv);
+
+ if (f->index >= ARRAY_SIZE(rkvdec_coded_fmts) ||
+ !(ctx->dev->capabilities & rkvdec_coded_fmts[f->index].capability))
return -EINVAL;
f->pixelformat = rkvdec_coded_fmts[f->index].fourcc;
@@ -428,6 +578,14 @@ static int rkvdec_enum_capture_fmt(struc
if (WARN_ON(!ctx->coded_fmt_desc))
return -EINVAL;
+ if (ctx->valid_fmt) {
+ if (f->index)
+ return -EINVAL;
+
+ f->pixelformat = ctx->valid_fmt;
+ return 0;
+ }
+
if (f->index >= ctx->coded_fmt_desc->num_decoded_fmts)
return -EINVAL;
@@ -658,6 +816,11 @@ static void rkvdec_job_finish(struct rkv
pm_runtime_mark_last_busy(rkvdec->dev);
pm_runtime_put_autosuspend(rkvdec->dev);
+
+ if (result == VB2_BUF_STATE_ERROR &&
+ rkvdec->reset_mask == RESET_NONE)
+ rkvdec->reset_mask |= RESET_SOFT;
+
rkvdec_job_finish_no_pm(ctx, result);
}
@@ -695,6 +858,33 @@ static void rkvdec_device_run(void *priv
if (WARN_ON(!desc))
return;
+ if (rkvdec->reset_mask != RESET_NONE) {
+
+ if (rkvdec->reset_mask & RESET_SOFT) {
+ writel(RKVDEC_SOFTRST_EN_P,
+ rkvdec->regs + RKVDEC_REG_INTERRUPT);
+ udelay(RKVDEC_RESET_DELAY);
+ if (readl(rkvdec->regs + RKVDEC_REG_INTERRUPT)
+ & RKVDEC_SOFTRESET_RDY)
+ dev_info_ratelimited(rkvdec->dev,
+ "softreset failed\n");
+ }
+
+ if (rkvdec->reset_mask & RESET_HARD) {
+ rockchip_pmu_idle_request(rkvdec->dev, true);
+ ret = reset_control_assert(rkvdec->rstc);
+ if (!ret) {
+ udelay(RKVDEC_RESET_DELAY);
+ ret = reset_control_deassert(rkvdec->rstc);
+ }
+ rockchip_pmu_idle_request(rkvdec->dev, false);
+ if (ret)
+ dev_notice_ratelimited(rkvdec->dev,
+ "hardreset failed\n");
+ }
+ rkvdec->reset_mask = RESET_NONE;
+ pm_runtime_suspend(rkvdec->dev);
+ }
ret = pm_runtime_resume_and_get(rkvdec->dev);
if (ret < 0) {
@@ -781,14 +971,17 @@ static int rkvdec_init_ctrls(struct rkvd
int ret;
for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++)
- nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls;
+ if (rkvdec_coded_fmts[i].capability & ctx->dev->capabilities)
+ nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls;
v4l2_ctrl_handler_init(&ctx->ctrl_hdl, nctrls);
for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) {
- ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls);
- if (ret)
- goto err_free_handler;
+ if (rkvdec_coded_fmts[i].capability & ctx->dev->capabilities) {
+ ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls);
+ if (ret)
+ goto err_free_handler;
+ }
}
ret = v4l2_ctrl_handler_setup(&ctx->ctrl_hdl);
@@ -961,6 +1154,11 @@ static irqreturn_t rkvdec_irq_handler(in
if (cancel_delayed_work(&rkvdec->watchdog_work)) {
struct rkvdec_ctx *ctx;
+ if (state == VB2_BUF_STATE_ERROR) {
+ rkvdec->reset_mask |= (status & RKVDEC_ERR_MASK) ?
+ RESET_HARD : RESET_SOFT;
+ }
+
ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev);
rkvdec_job_finish(ctx, state);
}
@@ -978,14 +1176,32 @@ static void rkvdec_watchdog_func(struct
ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev);
if (ctx) {
dev_err(rkvdec->dev, "Frame processing timed out!\n");
+ rkvdec->reset_mask |= RESET_HARD;
writel(RKVDEC_IRQ_DIS, rkvdec->regs + RKVDEC_REG_INTERRUPT);
writel(0, rkvdec->regs + RKVDEC_REG_SYSCTRL);
rkvdec_job_finish(ctx, VB2_BUF_STATE_ERROR);
}
}
+static const struct rkvdec_variant rk3399_rkvdec_variant = {
+ .capabilities = RKVDEC_CAPABILITY_H264 |
+ RKVDEC_CAPABILITY_HEVC |
+ RKVDEC_CAPABILITY_VP9
+};
+
+static const struct rkvdec_variant rk3288_hevc_variant = {
+ .capabilities = RKVDEC_CAPABILITY_HEVC
+};
+
static const struct of_device_id of_rkvdec_match[] = {
- { .compatible = "rockchip,rk3399-vdec" },
+ {
+ .compatible = "rockchip,rk3399-vdec",
+ .data = &rk3399_rkvdec_variant,
+ },
+ {
+ .compatible = "rockchip,rk3288-hevc",
+ .data = &rk3288_hevc_variant,
+ },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_rkvdec_match);
@@ -997,6 +1213,7 @@ static const char * const rkvdec_clk_nam
static int rkvdec_probe(struct platform_device *pdev)
{
struct rkvdec_dev *rkvdec;
+ const struct rkvdec_variant *variant;
unsigned int i;
int ret, irq;
@@ -1022,6 +1239,13 @@ static int rkvdec_probe(struct platform_
if (ret)
return ret;
+ variant = of_device_get_match_data(rkvdec->dev);
+ if (!variant)
+ return -EINVAL;
+
+ rkvdec->capabilities = variant->capabilities;
+
+
rkvdec->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(rkvdec->regs))
return PTR_ERR(rkvdec->regs);
@@ -1046,6 +1270,18 @@ static int rkvdec_probe(struct platform_
return ret;
}
+
+ rkvdec->rstc = devm_reset_control_array_get(&pdev->dev, false, true);
+ if (IS_ERR(rkvdec->rstc)) {
+ dev_err(&pdev->dev,
+ "get resets failed %ld\n", PTR_ERR(rkvdec->rstc));
+ return PTR_ERR(rkvdec->rstc);
+ } else {
+ dev_dbg(&pdev->dev,
+ "requested %d resets\n",
+ reset_control_get_count(&pdev->dev));
+ }
+
pm_runtime_set_autosuspend_delay(&pdev->dev, 100);
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_enable(&pdev->dev);
@@ -1068,9 +1304,9 @@ static int rkvdec_remove(struct platform
cancel_delayed_work_sync(&rkvdec->watchdog_work);
- rkvdec_v4l2_cleanup(rkvdec);
- pm_runtime_disable(&pdev->dev);
pm_runtime_dont_use_autosuspend(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+ rkvdec_v4l2_cleanup(rkvdec);
return 0;
}
diff -rupN linux.orig/drivers/staging/media/rkvdec/rkvdec.h linux/drivers/staging/media/rkvdec/rkvdec.h
--- linux.orig/drivers/staging/media/rkvdec/rkvdec.h 2024-01-03 20:53:31.439335419 +0000
+++ linux/drivers/staging/media/rkvdec/rkvdec.h 2024-01-03 21:27:48.651744306 +0000
@@ -11,10 +11,11 @@
#ifndef RKVDEC_H_
#define RKVDEC_H_
+#include <linux/clk.h>
#include <linux/platform_device.h>
+#include <linux/reset.h>
#include <linux/videodev2.h>
#include <linux/wait.h>
-#include <linux/clk.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
@@ -22,6 +23,16 @@
#include <media/videobuf2-core.h>
#include <media/videobuf2-dma-contig.h>
+#define RESET_NONE 0
+#define RESET_SOFT BIT(0)
+#define RESET_HARD BIT(1)
+
+#define RKVDEC_RESET_DELAY 5
+
+#define RKVDEC_CAPABILITY_H264 BIT(0)
+#define RKVDEC_CAPABILITY_HEVC BIT(1)
+#define RKVDEC_CAPABILITY_VP9 BIT(2)
+
struct rkvdec_ctx;
struct rkvdec_ctrl_desc {
@@ -63,9 +74,14 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buf
base.vb.vb2_buf);
}
+struct rkvdec_variant {
+ unsigned int capabilities;
+};
+
struct rkvdec_coded_fmt_ops {
int (*adjust_fmt)(struct rkvdec_ctx *ctx,
struct v4l2_format *f);
+ u32 (*valid_fmt)(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl);
int (*start)(struct rkvdec_ctx *ctx);
void (*stop)(struct rkvdec_ctx *ctx);
int (*run)(struct rkvdec_ctx *ctx);
@@ -83,6 +99,7 @@ struct rkvdec_coded_fmt_desc {
unsigned int num_decoded_fmts;
const u32 *decoded_fmts;
u32 subsystem_flags;
+ unsigned int capability;
};
struct rkvdec_dev {
@@ -95,12 +112,16 @@ struct rkvdec_dev {
void __iomem *regs;
struct mutex vdev_lock; /* serializes ioctls */
struct delayed_work watchdog_work;
+ struct reset_control *rstc;
+ u8 reset_mask;
+ unsigned int capabilities;
};
struct rkvdec_ctx {
struct v4l2_fh fh;
struct v4l2_format coded_fmt;
struct v4l2_format decoded_fmt;
+ u32 valid_fmt;
const struct rkvdec_coded_fmt_desc *coded_fmt_desc;
struct v4l2_ctrl_handler ctrl_hdl;
struct rkvdec_dev *dev;
@@ -122,6 +143,7 @@ void rkvdec_run_preamble(struct rkvdec_c
void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run);
extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops;
+extern const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops;
extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops;
#endif /* RKVDEC_H_ */
diff -rupN linux.orig/include/drm/bridge/dw_hdmi.h linux/include/drm/bridge/dw_hdmi.h
--- linux.orig/include/drm/bridge/dw_hdmi.h 2024-01-03 20:53:31.683338719 +0000
+++ linux/include/drm/bridge/dw_hdmi.h 2024-01-03 21:17:09.402615966 +0000
@@ -156,10 +156,12 @@ struct dw_hdmi_plat_data {
/* Synopsys PHY support */
const struct dw_hdmi_mpll_config *mpll_cfg;
+ const struct dw_hdmi_mpll_config *mpll_cfg_420;
const struct dw_hdmi_curr_ctrl *cur_ctr;
const struct dw_hdmi_phy_config *phy_config;
int (*configure_phy)(struct dw_hdmi *hdmi, void *data,
- unsigned long mpixelclock);
+ unsigned long mpixelclock,
+ unsigned long mtmdsclock);
unsigned int disable_cec : 1;
};
diff -rupN linux.orig/include/linux/rockchip_pmu.h linux/include/linux/rockchip_pmu.h
--- linux.orig/include/linux/rockchip_pmu.h 1970-01-01 00:00:00.000000000 +0000
+++ linux/include/linux/rockchip_pmu.h 2024-01-03 21:26:02.707011192 +0000
@@ -0,0 +1,15 @@
+/*
+ * pm_domain.h - Definitions and headers related to device power domains.
+ *
+ * Copyright (C) 2017 Randy Li <ayaka@soulik.info>.
+ *
+ * This file is released under the GPLv2.
+ */
+
+#ifndef _LINUX_ROCKCHIP_PM_H
+#define _LINUX_ROCKCHIP_PM_H
+#include <linux/device.h>
+
+int rockchip_pmu_idle_request(struct device *dev, bool idle);
+
+#endif /* _LINUX_ROCKCHIP_PM_H */
diff -rupN linux.orig/include/media/cec.h linux/include/media/cec.h
--- linux.orig/include/media/cec.h 2024-01-03 20:53:31.811340450 +0000
+++ linux/include/media/cec.h 2024-01-03 21:17:09.402615966 +0000
@@ -239,6 +239,8 @@ struct cec_adapter {
struct task_struct *kthread;
wait_queue_head_t kthread_waitq;
+ struct delayed_work debounce_work;
+
const struct cec_adap_ops *ops;
void *priv;
u32 capabilities;
diff -rupN linux.orig/include/soc/rockchip/pm_domains.h linux/include/soc/rockchip/pm_domains.h
--- linux.orig/include/soc/rockchip/pm_domains.h 2024-01-03 20:53:31.831340722 +0000
+++ linux/include/soc/rockchip/pm_domains.h 2024-01-03 21:26:02.707011192 +0000
@@ -10,6 +10,7 @@
int rockchip_pmu_block(void);
void rockchip_pmu_unblock(void);
+int rockchip_pmu_idle_request(struct device *dev, bool idle);
#else /* CONFIG_ROCKCHIP_PM_DOMAINS */
@@ -20,6 +21,11 @@ static inline int rockchip_pmu_block(voi
static inline void rockchip_pmu_unblock(void) { }
+static inline int rockchip_pmu_idle_request(struct device *dev, bool idle)
+{
+ return -ENOTSUPP;
+}
+
#endif /* CONFIG_ROCKCHIP_PM_DOMAINS */
#endif /* __SOC_ROCKCHIP_PM_DOMAINS_H__ */
diff -rupN linux.orig/include/uapi/drm/drm_fourcc.h linux/include/uapi/drm/drm_fourcc.h
--- linux.orig/include/uapi/drm/drm_fourcc.h 2024-01-03 20:53:31.843340883 +0000
+++ linux/include/uapi/drm/drm_fourcc.h 2024-01-03 21:08:52.940067739 +0000
@@ -311,6 +311,8 @@ extern "C" {
* index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
*/
#define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
+#define DRM_FORMAT_NV20 fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */
+#define DRM_FORMAT_NV30 fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
/*
* 2 plane YCbCr MSB aligned
diff -rupN linux.orig/include/uapi/linux/videodev2.h linux/include/uapi/linux/videodev2.h
--- linux.orig/include/uapi/linux/videodev2.h 2024-01-03 20:53:31.871341262 +0000
+++ linux/include/uapi/linux/videodev2.h 2024-01-03 21:03:19.317345475 +0000
@@ -627,6 +627,9 @@ struct v4l2_pix_format {
#define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/CrCb 4:4:4 */
#define V4L2_PIX_FMT_P010 v4l2_fourcc('P', '0', '1', '0') /* 24 Y/CbCr 4:2:0 10-bit per component */
+#define V4L2_PIX_FMT_NV15 v4l2_fourcc('N', 'V', '1', '5') /* 15 Y/UV 4:2:0 10-bit packed */
+#define V4L2_PIX_FMT_NV20 v4l2_fourcc('N', 'V', '2', '0') /* 20 Y/UV 4:2:2 10-bit packed */
+
/* two non contiguous planes - one Y, one Cr + Cb interleaved */
#define V4L2_PIX_FMT_NV12M v4l2_fourcc('N', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 */
#define V4L2_PIX_FMT_NV21M v4l2_fourcc('N', 'M', '2', '1') /* 21 Y/CrCb 4:2:0 */
diff -rupN linux.orig/sound/soc/codecs/hdmi-codec.c linux/sound/soc/codecs/hdmi-codec.c
--- linux.orig/sound/soc/codecs/hdmi-codec.c 2024-01-03 20:53:32.111344512 +0000
+++ linux/sound/soc/codecs/hdmi-codec.c 2024-01-03 21:27:13.822235237 +0000
@@ -190,78 +190,69 @@ static const struct snd_pcm_chmap_elem h
*/
static const struct hdmi_codec_cea_spk_alloc hdmi_codec_channel_alloc[] = {
{ .ca_id = 0x00, .n_ch = 2,
- .mask = FL | FR},
- /* 2.1 */
- { .ca_id = 0x01, .n_ch = 4,
- .mask = FL | FR | LFE},
- /* Dolby Surround */
+ .mask = FL | FR },
+ { .ca_id = 0x03, .n_ch = 4,
+ .mask = FL | FR | LFE | FC },
{ .ca_id = 0x02, .n_ch = 4,
.mask = FL | FR | FC },
- /* surround51 */
+ { .ca_id = 0x01, .n_ch = 4,
+ .mask = FL | FR | LFE },
{ .ca_id = 0x0b, .n_ch = 6,
- .mask = FL | FR | LFE | FC | RL | RR},
- /* surround40 */
- { .ca_id = 0x08, .n_ch = 6,
- .mask = FL | FR | RL | RR },
- /* surround41 */
- { .ca_id = 0x09, .n_ch = 6,
- .mask = FL | FR | LFE | RL | RR },
- /* surround50 */
+ .mask = FL | FR | LFE | FC | RL | RR },
{ .ca_id = 0x0a, .n_ch = 6,
.mask = FL | FR | FC | RL | RR },
- /* 6.1 */
- { .ca_id = 0x0f, .n_ch = 8,
- .mask = FL | FR | LFE | FC | RL | RR | RC },
- /* surround71 */
+ { .ca_id = 0x09, .n_ch = 6,
+ .mask = FL | FR | LFE | RL | RR },
+ { .ca_id = 0x08, .n_ch = 6,
+ .mask = FL | FR | RL | RR },
+ { .ca_id = 0x07, .n_ch = 6,
+ .mask = FL | FR | LFE | FC | RC },
+ { .ca_id = 0x06, .n_ch = 6,
+ .mask = FL | FR | FC | RC },
+ { .ca_id = 0x05, .n_ch = 6,
+ .mask = FL | FR | LFE | RC },
+ { .ca_id = 0x04, .n_ch = 6,
+ .mask = FL | FR | RC },
{ .ca_id = 0x13, .n_ch = 8,
.mask = FL | FR | LFE | FC | RL | RR | RLC | RRC },
- /* others */
- { .ca_id = 0x03, .n_ch = 8,
- .mask = FL | FR | LFE | FC },
- { .ca_id = 0x04, .n_ch = 8,
- .mask = FL | FR | RC},
- { .ca_id = 0x05, .n_ch = 8,
- .mask = FL | FR | LFE | RC },
- { .ca_id = 0x06, .n_ch = 8,
- .mask = FL | FR | FC | RC },
- { .ca_id = 0x07, .n_ch = 8,
- .mask = FL | FR | LFE | FC | RC },
- { .ca_id = 0x0c, .n_ch = 8,
- .mask = FL | FR | RC | RL | RR },
- { .ca_id = 0x0d, .n_ch = 8,
- .mask = FL | FR | LFE | RL | RR | RC },
- { .ca_id = 0x0e, .n_ch = 8,
- .mask = FL | FR | FC | RL | RR | RC },
- { .ca_id = 0x10, .n_ch = 8,
- .mask = FL | FR | RL | RR | RLC | RRC },
- { .ca_id = 0x11, .n_ch = 8,
- .mask = FL | FR | LFE | RL | RR | RLC | RRC },
+ { .ca_id = 0x1f, .n_ch = 8,
+ .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC },
{ .ca_id = 0x12, .n_ch = 8,
.mask = FL | FR | FC | RL | RR | RLC | RRC },
- { .ca_id = 0x14, .n_ch = 8,
- .mask = FL | FR | FLC | FRC },
- { .ca_id = 0x15, .n_ch = 8,
- .mask = FL | FR | LFE | FLC | FRC },
- { .ca_id = 0x16, .n_ch = 8,
- .mask = FL | FR | FC | FLC | FRC },
- { .ca_id = 0x17, .n_ch = 8,
- .mask = FL | FR | LFE | FC | FLC | FRC },
- { .ca_id = 0x18, .n_ch = 8,
- .mask = FL | FR | RC | FLC | FRC },
- { .ca_id = 0x19, .n_ch = 8,
- .mask = FL | FR | LFE | RC | FLC | FRC },
- { .ca_id = 0x1a, .n_ch = 8,
- .mask = FL | FR | RC | FC | FLC | FRC },
- { .ca_id = 0x1b, .n_ch = 8,
- .mask = FL | FR | LFE | RC | FC | FLC | FRC },
- { .ca_id = 0x1c, .n_ch = 8,
- .mask = FL | FR | RL | RR | FLC | FRC },
- { .ca_id = 0x1d, .n_ch = 8,
- .mask = FL | FR | LFE | RL | RR | FLC | FRC },
{ .ca_id = 0x1e, .n_ch = 8,
.mask = FL | FR | FC | RL | RR | FLC | FRC },
- { .ca_id = 0x1f, .n_ch = 8,
- .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC },
+ { .ca_id = 0x11, .n_ch = 8,
+ .mask = FL | FR | LFE | RL | RR | RLC | RRC },
+ { .ca_id = 0x1d, .n_ch = 8,
+ .mask = FL | FR | LFE | RL | RR | FLC | FRC },
+ { .ca_id = 0x10, .n_ch = 8,
+ .mask = FL | FR | RL | RR | RLC | RRC },
+ { .ca_id = 0x1c, .n_ch = 8,
+ .mask = FL | FR | RL | RR | FLC | FRC },
+ { .ca_id = 0x0f, .n_ch = 8,
+ .mask = FL | FR | LFE | FC | RL | RR | RC },
+ { .ca_id = 0x1b, .n_ch = 8,
+ .mask = FL | FR | LFE | RC | FC | FLC | FRC },
+ { .ca_id = 0x0e, .n_ch = 8,
+ .mask = FL | FR | FC | RL | RR | RC },
+ { .ca_id = 0x1a, .n_ch = 8,
+ .mask = FL | FR | RC | FC | FLC | FRC },
+ { .ca_id = 0x0d, .n_ch = 8,
+ .mask = FL | FR | LFE | RL | RR | RC },
+ { .ca_id = 0x19, .n_ch = 8,
+ .mask = FL | FR | LFE | RC | FLC | FRC },
+ { .ca_id = 0x0c, .n_ch = 8,
+ .mask = FL | FR | RC | RL | RR },
+ { .ca_id = 0x18, .n_ch = 8,
+ .mask = FL | FR | RC | FLC | FRC },
+ { .ca_id = 0x17, .n_ch = 8,
+ .mask = FL | FR | LFE | FC | FLC | FRC },
+ { .ca_id = 0x16, .n_ch = 8,
+ .mask = FL | FR | FC | FLC | FRC },
+ { .ca_id = 0x15, .n_ch = 8,
+ .mask = FL | FR | LFE | FLC | FRC },
+ { .ca_id = 0x14, .n_ch = 8,
+ .mask = FL | FR | FLC | FRC },
};
struct hdmi_codec_priv {
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