4746 lines
126 KiB
Diff
4746 lines
126 KiB
Diff
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
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index b6af76d1a..0c1ae6c98 100644
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--- a/arch/arm64/boot/dts/rockchip/Makefile
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+++ b/arch/arm64/boot/dts/rockchip/Makefile
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@@ -79,8 +79,9 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb2-lp4x-v10-eink.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb2-lp4x-v10-i2s-mic-array.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb2-lp4x-v10-linux.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566.dtb
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-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rg503-linux.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk2023-linux.dtb
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+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-x55-linux.dtb
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+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rg503-linux.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rg353m-linux.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rg353p-linux.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rg353v-linux.dtb
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diff --git a/arch/arm64/boot/dts/rockchip/lcd/lcd_HX8394F_720x1280_mipi_dsi0.dtsi b/arch/arm64/boot/dts/rockchip/lcd/lcd_HX8394F_720x1280_mipi_dsi0.dtsi
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new file mode 100755
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index 000000000..5eb492203
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/lcd/lcd_HX8394F_720x1280_mipi_dsi0.dtsi
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@@ -0,0 +1,101 @@
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+#include <dt-bindings/display/drm_mipi_dsi.h>
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+
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+
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+
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+&dsi0 {
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+ status = "okay";
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+ // rockchip,dual-channel = <&dsi1>;
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+
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+ //rockchip,lane-rate = <1000>;
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+ dsi0_panel: panel@0 {
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+ compatible ="simple-panel-dsi";
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+ reg = <0>;
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+ reset-delay-ms = <60>;
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+ enable-delay-ms = <120>;
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+ prepare-delay-ms = <60>;
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+ init-delay-ms = <60>;
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+ unprepare-delay-ms = <60>;
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+ disable-delay-ms = <60>;
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+
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+
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+ dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
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+ MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
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+ dsi,format = <MIPI_DSI_FMT_RGB888>;
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+ dsi,lanes = <4>;
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+ panel-init-sequence = [
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+ 39 00 04 B9 FF 83 94
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+ 39 00 07 BA 63 03 68 6B B2 C0
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+ 39 00 0B B1 48 12 72 09 32 54 71 71 57 47
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+ 39 00 07 B2 00 80 64 0C 0D 2F
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+ 39 00 16 B4 73 74 73 74 73 74 01 0C 86 75 00 3F 73 74 73 74 73 74 01 0C 86
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+ 39 00 03 B6 6E 6E
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+ 39 00 22 D3 00 00 07 07 40 07 0C 00 08 10 08 00 08 54 15 0A 05 0A 02 15 06 05 06 47 44 0A 0A 4B 10 07 07 0C 40
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+ 39 00 2D D5 1C 1C 1D 1D 00 01 02 03 04 05 06 07 08 09 0A 0B 24 25 18 18 26 27 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 20 21 18 18 18 18
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+ 39 00 2D D6 1C 1C 1D 1D 07 06 05 04 03 02 01 00 0B 0A 09 08 21 20 18 18 27 26 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 25 24 18 18 18 18
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+ 39 00 3B E0 00 0A 15 1B 1E 21 24 22 47 56 65 66 6E 82 88 8B 9A 9D 98 A8 B9 5D 5C 61 66 6A 6F 7F 7F 00 0A 15 1B 1E 21 24 22 47 56 65 65 6E 81 87 8B 98 9D 99 A8 BA 5D 5D 62 67 6B 72 7F 7F
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+ 39 00 03 C0 1F 31
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+ 15 00 02 CC 0B
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+ 15 00 02 D4 02
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+ 15 00 02 BD 02
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+ 39 00 0D D8 FF FF FF FF FF FF FF FF FF FF FF FF
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+ 15 00 02 BD 00
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+ 15 00 02 BD 01
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+ 15 00 02 B1 00
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+ 15 00 02 BD 00
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+ 39 00 08 BF 40 81 50 00 1A FC 01
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+ 15 00 02 C6 ED
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+
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+ 05 78 01 11
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+ 05 14 01 29
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+ ];
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+
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+ panel-exit-sequence = [
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+ 05 00 01 28
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+ 05 00 01 10
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+ ];
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+
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+ disp_timings0: display-timings {
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+ native-mode = <&dsi0_timing0>;
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+ dsi0_timing0: timing0 {
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+ clock-frequency = <60000000>;
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+ hactive = <720>;
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+ vactive = <1280>;
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+ hback-porch = <20>;
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+ hfront-porch = <24>;
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+ vback-porch = <8>;
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+ vfront-porch = <8>;
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+ hsync-len = <4>;
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+ vsync-len = <4>;
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+ hsync-active = <0>;
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+ vsync-active = <0>;
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+ de-active = <0>;
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+ pixelclk-active = <0>;
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+ };
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+ };
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ port@0 {
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+ reg = <0>;
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+ panel_in_dsi: endpoint {
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+ remote-endpoint = <&dsi_out_panel>;
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+ };
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+ };
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+ };
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+ };
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ port@1 {
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+ reg = <1>;
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+ dsi_out_panel: endpoint {
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+ remote-endpoint = <&panel_in_dsi>;
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+ };
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+ };
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+ };
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+
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+};
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diff --git a/arch/arm64/boot/dts/rockchip/rk3566-x55-linux.dts b/arch/arm64/boot/dts/rockchip/rk3566-x55-linux.dts
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new file mode 100755
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index 000000000..657b9a07b
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/rk3566-x55-linux.dts
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@@ -0,0 +1,1056 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
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+ *
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+ */
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+
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+/dts-v1/;
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+
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+#include <dt-bindings/gpio/gpio.h>
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+#include <dt-bindings/display/media-bus-format.h>
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+#include <dt-bindings/pinctrl/rockchip.h>
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+
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+/* #include <dt-bindings/gpio/gpio.h>
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+#include <dt-bindings/pinctrl/rockchip.h>
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+#include <dt-bindings/input/rk-input.h>
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+#include <dt-bindings/sensor-dev.h>
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+#include <dt-bindings/display/drm_mipi_dsi.h>
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+#include <dt-bindings/display/rockchip_vop.h>
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+*/
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+
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+#include "rk3568-evb-x55.dtsi"
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+#include "lcd/lcd_HX8394F_720x1280_mipi_dsi0.dtsi"
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+
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+/ {
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+ model = "Powkiddy x55";
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+ compatible = "rockchip,rk3566-rk817-tablet", "rockchip,rk3566";
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+
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+ backlight: backlight {
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+ compatible = "pwm-backlight";
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+ pwms = <&pwm4 0 25000 0>;
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+ brightness-levels = <
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+ 0 20 20 21 21 22 22 23
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+ 23 24 24 25 25 26 26 27
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+ 27 28 28 29 29 30 30 31
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+ 31 32 32 33 33 34 34 35
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+ 35 36 36 37 37 38 38 39
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+ 40 41 42 43 44 45 46 47
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+ 48 49 50 50 51 52 53 54
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+ 55 55 56 57 58 59 60 61
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+ 62 63 64 64 65 65 66 67
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+ 68 69 70 71 71 72 73 74
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+ 75 76 77 78 79 79 80 81
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+ 82 83 84 85 86 86 87 88
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+ 89 90 91 92 93 94 94 95
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+ 96 97 98 99 100 101 101 102
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+ 103 104 105 106 107 107 108 109
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+ 110 111 112 113 114 115 115 116
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+ 117 118 119 120 121 122 123 123
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+ 124 125 126 127 128 129 130 130
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+ 131 132 133 134 135 136 136 137
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+ 138 139 140 141 142 143 143 144
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+ 145 146 147 147 148 149 150 151
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+ 152 153 154 155 156 156 157 158
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+ 159 157 158 159 160 161 162 162
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+ 163 164 165 166 167 168 169 169
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+ 170 171 172 173 174 175 175 176
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+ 177 178 179 180 181 182 182 183
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+ 184 185 186 187 188 189 190 190
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+ 191 192 193 194 195 196 197 197
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+ 198 199 200 201 202 203 204 204
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+ 205 206 207 208 209 209 210 211
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+ 212 213 213 214 214 215 215 216
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+ 216 217 217 218 218 219 219 220
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+ >;
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+ default-brightness-level = <200>;
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+ };
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+
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+ charge-animation {
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+ compatible = "rockchip,uboot-charge";
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+ rockchip,uboot-charge-on = <1>;
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+ rockchip,android-charge-on = <0>;
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+ rockchip,uboot-low-power-voltage = <3350>;
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+ rockchip,screen-on-voltage = <3400>;
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+ status = "okay";
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+ };
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+
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+ flash_rgb13h: flash-rgb13h {
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+ status = "okay";
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+ compatible = "led,rgb13h";
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+ label = "gpio-flash";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&flash_led_gpios>;
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+ led-max-microamp = <20000>;
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+ flash-max-microamp = <20000>;
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+ flash-max-timeout-us = <1000000>;
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+ enable-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>;
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+ rockchip,camera-module-index = <0>;
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+ rockchip,camera-module-facing = "back";
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+ };
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+
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+ vcc5v0_otg: vcc5v0-otg-regulator {
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+ compatible = "regulator-fixed";
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+ enable-active-high;
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+ gpio = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&vcc5v0_otg_en>;
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+ regulator-name = "vcc5v0_otg";
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+ };
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+
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+ vcc5v0_host: vcc5v0-host-regulator {
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+ compatible = "regulator-fixed";
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+ enable-active-high;
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+ gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&vcc5v0_host_en>;
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+ regulator-name = "vcc5v0_host";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ };
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+
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+ rk817-sound {
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+ compatible = "simple-audio-card";
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+ simple-audio-card,format = "i2s";
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+ simple-audio-card,name = "rockchip,rk817-codec";
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+ simple-audio-card,mclk-fs = <256>;
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+
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+ simple-audio-card,cpu {
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+ sound-dai = <&i2s1_8ch>;
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+ };
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+ simple-audio-card,codec {
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+ sound-dai = <&rk817_codec>;
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+ };
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+ };
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+
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+ hdmi_sound: hdmi-sound {
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+ compatible = "simple-audio-card";
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+ simple-audio-card,format = "i2s";
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+ simple-audio-card,mclk-fs = <128>;
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+ simple-audio-card,name = "rockchip,hdmi";
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+ status = "disabled";
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+
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+ simple-audio-card,cpu {
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+ sound-dai = <&i2s0_8ch>;
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+ };
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+ simple-audio-card,codec {
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+ sound-dai = <&hdmi>;
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+ };
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+ };
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+
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+ vccsys: vccsys {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc3v8_sys";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <3800000>;
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+ regulator-max-microvolt = <3800000>;
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+ };
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+/*
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+ vcc_camera: vcc-camera-regulator {
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+ compatible = "regulator-fixed";
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+ gpio = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&camera_rst>;
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+ regulator-name = "vcc_camera";
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+ enable-active-high;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ };
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+*/
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+
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+ rk_headset: rk-headset {
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+ status = "okay";
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+ compatible = "rockchip_headset";
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+ headset_gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&hp_det>;
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+ // io-channels = <&saradc 2>;
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+ };
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+
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+ sdio_pwrseq: sdio-pwrseq {
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+ compatible = "mmc-pwrseq-simple";
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+ // clocks = <&rk817 1>;
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+ // clock-names = "ext_clock";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&wifi_enable_h>;
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+
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+ /*
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+ * On the module itself this is one of these (depending
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+ * on the actual card populated):
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+ * - SDIO_RESET_L_WL_REG_ON
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+ * - PDN (power down when low)
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+ */
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+ post-power-on-delay-ms = <200>;
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+ reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>,<&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
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+ };
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+
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+ vcc_sd: vcc-sd {
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+ compatible = "regulator-gpio";
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+ enable-active-low;
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+ enable-gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&vcc_sd_h>;
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+ regulator-name = "vcc_sd";
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+ states = <3300000 0x0
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+ 3300000 0x1>;
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+ };
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+
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+ wireless-wlan {
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+ compatible = "wlan-platdata";
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+ rockchip,grf = <&grf>;
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+ wifi_chip_type = "rtl8821cs";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&wifi_host_wake_irq>;
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+ WIFI,host_wake_irq = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
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+ status = "okay";
|
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+ };
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+
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+ wireless-bluetooth {
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+ compatible = "bluetooth-platdata";
|
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+ //clocks = <&rk817 1>;
|
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+ //clock-names = "ext_clock";
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+ //wifi-bt-power-toggle;
|
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+ uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
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+ pinctrl-names = "default", "rts_gpio";
|
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+ pinctrl-0 = <&uart1m0_rtsn>;
|
|
+ pinctrl-1 = <&uart1_gpios>;
|
|
+ BT,reset_gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
|
|
+ BT,wake_gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
|
|
+ BT,wake_host_irq = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
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+
|
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+&cpu0 {
|
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+ cpu-supply = <&vdd_cpu>;
|
|
+};
|
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+
|
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+&csi2_dphy_hw {
|
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+ status = "disabled";
|
|
+};
|
|
+
|
|
+&csi2_dphy0 {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
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+&dfi {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&dmc {
|
|
+ center-supply = <&vdd_logic>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+
|
|
+&edp_phy{
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&edp {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&edp_in_vp0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&edp_in_vp1 {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
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+&dsi0 {
|
|
+ status = "okay";
|
|
+ dsi0_panel: panel@0 {
|
|
+ backlight = <&backlight>;
|
|
+ // power_vsx-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
|
|
+ enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
|
|
+ reset-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>;
|
|
+ // pinctrl-names = "default";
|
|
+ // pinctrl-0 = <&lcd0_rst_gpio>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&dsi0_in_vp0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&dsi0_in_vp1 {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&dsi1 {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&dsi1_in_vp0 {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&dsi1_in_vp1 {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&video_phy0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&video_phy1 {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&hdmi {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&hdmi_in_vp0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&hdmi_in_vp1 {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&hdmi_sound {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&route_dsi0 {
|
|
+ status = "okay";
|
|
+ connect = <&vp0_out_dsi0>;
|
|
+};
|
|
+
|
|
+&route_hdmi {
|
|
+ status = "okay";
|
|
+ connect = <&vp0_out_hdmi>;
|
|
+};
|
|
+
|
|
+&route_edp {
|
|
+ status = "disabled";
|
|
+ connect = <&vp0_out_edp>;
|
|
+};
|
|
+
|
|
+&gpu {
|
|
+ mali-supply = <&vdd_gpu>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&i2c0 {
|
|
+ status = "okay";
|
|
+
|
|
+ vdd_cpu: tcs4525@1c {
|
|
+ compatible = "tcs,tcs452x";
|
|
+ reg = <0x1c>;
|
|
+ vin-supply = <&vccsys>;
|
|
+ regulator-compatible = "fan53555-reg";
|
|
+ regulator-name = "vdd_cpu";
|
|
+ regulator-min-microvolt = <712500>;
|
|
+ regulator-max-microvolt = <1390000>;
|
|
+ regulator-init-microvolt = <900000>;
|
|
+ regulator-ramp-delay = <2300>;
|
|
+ fcs,suspend-voltage-selector = <1>;
|
|
+ regulator-boot-on;
|
|
+ regulator-always-on;
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ rk817: pmic@20 {
|
|
+ compatible = "rockchip,rk817";
|
|
+ reg = <0x20>;
|
|
+ interrupt-parent = <&gpio0>;
|
|
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
|
|
+
|
|
+ pinctrl-names = "default", "pmic-sleep",
|
|
+ "pmic-power-off", "pmic-reset";
|
|
+ pinctrl-0 = <&pmic_int>;
|
|
+ pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
|
|
+ pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
|
|
+ pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
|
|
+ rockchip,system-power-controller;
|
|
+ wakeup-source;
|
|
+ #clock-cells = <1>;
|
|
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
|
|
+ //fb-inner-reg-idxs = <2>;
|
|
+ /* 1: rst regs (default in codes), 0: rst the pmic */
|
|
+ pmic-reset-func = <0>;
|
|
+ /* not save the PMIC_POWER_EN register in uboot */
|
|
+ not-save-power-en = <1>;
|
|
+
|
|
+ vcc1-supply = <&vccsys>;
|
|
+ vcc2-supply = <&vccsys>;
|
|
+ vcc3-supply = <&vccsys>;
|
|
+ vcc4-supply = <&vccsys>;
|
|
+ vcc5-supply = <&vccsys>;
|
|
+ vcc6-supply = <&vccsys>;
|
|
+ vcc7-supply = <&vccsys>;
|
|
+ vcc8-supply = <&vccsys>;
|
|
+ vcc9-supply = <&dcdc_boost>;
|
|
+
|
|
+ pwrkey {
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
+ pinctrl_rk8xx: pinctrl_rk8xx {
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+
|
|
+ rk817_slppin_null: rk817_slppin_null {
|
|
+ pins = "gpio_slp";
|
|
+ function = "pin_fun0";
|
|
+ };
|
|
+
|
|
+ rk817_slppin_slp: rk817_slppin_slp {
|
|
+ pins = "gpio_slp";
|
|
+ function = "pin_fun1";
|
|
+ };
|
|
+
|
|
+ rk817_slppin_pwrdn: rk817_slppin_pwrdn {
|
|
+ pins = "gpio_slp";
|
|
+ function = "pin_fun2";
|
|
+ };
|
|
+
|
|
+ rk817_slppin_rst: rk817_slppin_rst {
|
|
+ pins = "gpio_slp";
|
|
+ function = "pin_fun3";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ regulators {
|
|
+ vdd_logic: DCDC_REG1 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <500000>;
|
|
+ regulator-max-microvolt = <1350000>;
|
|
+ regulator-init-microvolt = <900000>;
|
|
+ regulator-ramp-delay = <6001>;
|
|
+ regulator-initial-mode = <0x2>;
|
|
+ regulator-name = "vdd_logic";
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <900000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vdd_gpu: DCDC_REG2 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <500000>;
|
|
+ regulator-max-microvolt = <1350000>;
|
|
+ regulator-init-microvolt = <900000>;
|
|
+ regulator-ramp-delay = <6001>;
|
|
+ regulator-initial-mode = <0x2>;
|
|
+ regulator-name = "vdd_gpu";
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc_ddr: DCDC_REG3 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-initial-mode = <0x2>;
|
|
+ regulator-name = "vcc_ddr";
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc_3v3: DCDC_REG4 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-initial-mode = <0x2>;
|
|
+ regulator-name = "vcc_3v3";
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ //regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcca1v8_pmu: LDO_REG1 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ regulator-name = "vcca1v8_pmu";
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <1800000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vdda_0v9: LDO_REG2 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <900000>;
|
|
+ regulator-max-microvolt = <900000>;
|
|
+ regulator-name = "vdda_0v9";
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vdda0v9_pmu: LDO_REG3 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <900000>;
|
|
+ regulator-max-microvolt = <900000>;
|
|
+ regulator-name = "vdda0v9_pmu";
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <900000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vccio_acodec: LDO_REG4 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-name = "vccio_acodec";
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vccio_sd: LDO_REG5 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-name = "vccio_sd";
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc3v3_pmu: LDO_REG6 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-name = "vcc3v3_pmu";
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <3000000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc_1v8: LDO_REG7 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ regulator-name = "vcc_1v8";
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc1v8_dvp: LDO_REG8 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ regulator-name = "vcc1v8_dvp";
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc2v8_dvp: LDO_REG9 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-name = "vcc2v8_dvp";
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dcdc_boost: BOOST {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <4700000>;
|
|
+ regulator-max-microvolt = <5400000>;
|
|
+ regulator-name = "boost";
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ otg_switch: OTG_SWITCH {
|
|
+ regulator-name = "otg_switch";
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ battery {
|
|
+ compatible = "rk817,battery";
|
|
+ ocv_table = <3400 3553 3621 3688 3735 3768 3801
|
|
+ 3826 3843 3857 3878 3904 3934 3972
|
|
+ 4006 4020 4030 4044 4059 4083 4138>;
|
|
+ design_capacity = <3527>;
|
|
+ design_qmax = <3880>;
|
|
+ bat_res = <91>;
|
|
+ sleep_enter_current = <150>;
|
|
+ sleep_exit_current = <180>;
|
|
+ sleep_filter_current = <100>;
|
|
+ power_off_thresd = <3350>;
|
|
+ zero_algorithm_vol = <3300>;
|
|
+ max_soc_offset = <60>;
|
|
+ monitor_sec = <5>;
|
|
+ sample_res = <10>;
|
|
+ virtual_power = <0>;
|
|
+ // dc_det_gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>;//uboot使用
|
|
+ charge_red_gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;//充电指示灯 红
|
|
+ charge_green_gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;//充电指示灯 绿
|
|
+ charge_yellow_gpio = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;//充电指示灯 黄
|
|
+ };
|
|
+
|
|
+ charger {
|
|
+ compatible = "rk817,charger";
|
|
+ min_input_voltage = <4500>;
|
|
+ max_input_current = <2000>;
|
|
+ max_chrg_current = <2000>;
|
|
+ max_chrg_voltage = <4300>;
|
|
+ chrg_term_mode = <0>;
|
|
+ chrg_finish_cur = <300>;
|
|
+ virtual_power = <0>;
|
|
+ dc_det_adc = <0>;
|
|
+ // dc_det_gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>;
|
|
+ charge_red_gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;//充电指示灯 红
|
|
+ charge_green_gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;//充电指示灯 绿
|
|
+ charge_yellow_gpio = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;//充电指示灯 黄
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&charge_led_gpio>;
|
|
+ extcon = <&usb2phy0>;
|
|
+ gate_function_disable = <1>;
|
|
+ };
|
|
+
|
|
+ rk817_codec: codec {
|
|
+ #sound-dai-cells = <0>;
|
|
+ compatible = "rockchip,rk817-codec";
|
|
+ clocks = <&cru I2S1_MCLKOUT>;
|
|
+ clock-names = "mclk";
|
|
+ assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>;
|
|
+ assigned-clock-rates = <12288000>;
|
|
+ assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2s1m0_mclk>;
|
|
+ hp-volume = <3>;
|
|
+ spk-volume = <3>;
|
|
+ //out-l2spk-r2hp;
|
|
+ use-ext-amplifier;
|
|
+ spk-ctl-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2c2 {
|
|
+ status = "disabled";
|
|
+ pinctrl-0 = <&i2c2m1_xfer>;
|
|
+};
|
|
+
|
|
+&i2c3 {
|
|
+ status = "disabled";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c3m1_xfer>;
|
|
+ clock-frequency = <400000>;
|
|
+ i2c-scl-rising-time-ns = <138>;
|
|
+ i2c-scl-falling-time-ns = <4>;
|
|
+
|
|
+};
|
|
+
|
|
+&i2c5 {
|
|
+ status = "disabled";
|
|
+ clock-frequency = <400000>;
|
|
+ i2c-scl-rising-time-ns = <144>;
|
|
+ i2c-scl-falling-time-ns = <4>;
|
|
+
|
|
+};
|
|
+
|
|
+&i2s0_8ch {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&i2s1_8ch {
|
|
+ status = "okay";
|
|
+ rockchip,clk-trcm = <1>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2s1m0_sclktx
|
|
+ &i2s1m0_lrcktx
|
|
+ &i2s1m0_sdi0
|
|
+ &i2s1m0_sdo0>;
|
|
+};
|
|
+
|
|
+&jpegd {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&jpegd_mmu {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&video_phy0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&mpp_srv {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&nandc0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pinctrl {
|
|
+ cam {
|
|
+ cam_clkout0: cam-clkout0 {
|
|
+ rockchip,pins =
|
|
+ /* cam_clkout0 */
|
|
+ <4 RK_PA7 1 &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ cam_sleep: cam-sleep {
|
|
+ rockchip,pins =
|
|
+ /* cam_sleep */
|
|
+ <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ camera_rst: camera-rst {
|
|
+ rockchip,pins =
|
|
+ /* front camera reset */
|
|
+ <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>,
|
|
+ /* back camra reset */
|
|
+ <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ flash_led_gpios: flash-led {
|
|
+ rockchip,pins =
|
|
+ /* flash led enable */
|
|
+ <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ tp {
|
|
+ tp_gpio: tp-gpio {
|
|
+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>,
|
|
+ <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ headphone {
|
|
+ hp_det: hp-det {
|
|
+ rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ lcd {
|
|
+ lcd_rst_gpio: lcd-rst-gpio {
|
|
+ rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ lcd_enable_gpio: lcd-enable-gpio {
|
|
+ rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ lcd_stanby_gpio: lcd-stanby-gpio {
|
|
+ rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pmic {
|
|
+ pmic_int: pmic_int {
|
|
+ rockchip,pins =
|
|
+ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
+ };
|
|
+
|
|
+ soc_slppin_gpio: soc_slppin_gpio {
|
|
+ rockchip,pins =
|
|
+ <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>;
|
|
+ };
|
|
+
|
|
+ soc_slppin_slp: soc_slppin_slp {
|
|
+ rockchip,pins =
|
|
+ <0 RK_PA2 1 &pcfg_pull_up>;
|
|
+ };
|
|
+
|
|
+ soc_slppin_rst: soc_slppin_rst {
|
|
+ rockchip,pins =
|
|
+ <0 RK_PA2 2 &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sensor {
|
|
+ sensor_gpio: sensor-gpio {
|
|
+ rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdio-pwrseq {
|
|
+ wifi_enable_h: wifi-enable-h {
|
|
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>,
|
|
+ <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc_sd {
|
|
+ vcc_sd_h: vcc-sd-h {
|
|
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ wireless-wlan {
|
|
+ wifi_host_wake_irq: wifi-host-wake-irq {
|
|
+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ wireless-bluetooth {
|
|
+ uart1_gpios: uart1-gpios {
|
|
+ rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+ usb {
|
|
+ vcc5v0_host_en: vcc5v0-host-en {
|
|
+ rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
+ };
|
|
+
|
|
+ vcc5v0_otg_en: vcc5v0-otg-en {
|
|
+ rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
+ };
|
|
+ };
|
|
+ led {
|
|
+ charge_led_gpio:charge-led-gpio{
|
|
+ rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>,
|
|
+ <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>,
|
|
+ <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ };
|
|
+ buttons {
|
|
+ gpio_key_pin: gpio-key-pin {
|
|
+ rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>,
|
|
+ <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>,
|
|
+ <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>,
|
|
+ <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>,
|
|
+ <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>,
|
|
+ <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>,
|
|
+ <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>,
|
|
+ <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>,
|
|
+ <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>,
|
|
+ <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up>,
|
|
+ <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>,
|
|
+ <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>,
|
|
+ <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
|
|
+ <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
|
|
+ <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
|
|
+ <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
|
|
+ <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
|
|
+ <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&pmu_io_domains {
|
|
+ status = "okay";
|
|
+ pmuio1-supply = <&vcc3v3_pmu>;
|
|
+ pmuio2-supply = <&vcca1v8_pmu>;
|
|
+ vccio1-supply = <&vccio_acodec>;
|
|
+ vccio3-supply = <&vccio_sd>;
|
|
+ vccio4-supply = <&vcca1v8_pmu>;
|
|
+ vccio5-supply = <&vcc2v8_dvp>;
|
|
+ vccio6-supply = <&vcc1v8_dvp>;
|
|
+ vccio7-supply = <&vcc_3v3>;
|
|
+};
|
|
+
|
|
+&pwm4 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&rk_rga {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&rkisp {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&rkisp_mmu {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&rkisp_vir0 {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&rkvdec {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&rkvdec_mmu {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&rkvenc {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&rkvenc_mmu {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&route_dsi0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&route_hdmi {
|
|
+ status = "okay";
|
|
+ connect = <&vp0_out_hdmi>;
|
|
+};
|
|
+
|
|
+&saradc {
|
|
+ status = "okay";
|
|
+ vref-supply = <&vcc_1v8>;
|
|
+};
|
|
+
|
|
+&sdhci {
|
|
+ bus-width = <8>;
|
|
+ supports-emmc;
|
|
+ non-removable;
|
|
+ max-frequency = <200000000>;
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&sdmmc0 {
|
|
+ max-frequency = <150000000>;
|
|
+ supports-sd;
|
|
+ bus-width = <4>;
|
|
+ cap-mmc-highspeed;
|
|
+ cap-sd-highspeed;
|
|
+ disable-wp;
|
|
+ sd-uhs-sdr104;
|
|
+ vmmc-supply = <&vcc_sd>;
|
|
+ vqmmc-supply = <&vccio_sd>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&sdmmc1 {
|
|
+ max-frequency = <150000000>;
|
|
+ supports-sdio;
|
|
+ bus-width = <4>;
|
|
+ disable-wp;
|
|
+ cap-sd-highspeed;
|
|
+ cap-sdio-irq;
|
|
+ keep-power-in-suspend;
|
|
+ mmc-pwrseq = <&sdio_pwrseq>;
|
|
+ non-removable;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
|
|
+ sd-uhs-sdr104;
|
|
+ rockchip,default-sample-phase = <90>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&sdmmc2 {
|
|
+ max-frequency = <150000000>;
|
|
+ supports-sd;
|
|
+ bus-width = <4>;
|
|
+ cap-mmc-highspeed;
|
|
+ cap-sd-highspeed;
|
|
+ disable-wp;
|
|
+ sd-uhs-sdr104;
|
|
+ //vqmmc-supply = <&vcc_1v8>;
|
|
+ //vqmmc-supply = <&vccio_sd>;
|
|
+ vqmmc-supply = <&vcc2v8_dvp>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&sdmmc2m1_bus4 &sdmmc2m1_cmd &sdmmc2m1_clk &sdmmc2m1_det>;
|
|
+ //rockchip,default-sample-phase = <180>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&tsadc {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart1 {
|
|
+ status = "okay";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
|
|
+};
|
|
+
|
|
+
|
|
+
|
|
+/**************************3.0 otg***********************************/
|
|
+&usbdrd30 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbdrd_dwc3 {
|
|
+ status = "okay";
|
|
+};
|
|
+/**************************3.0 host***********************************/
|
|
+&usbhost30 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbhost_dwc3 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+/**************************usbphy***********************************/
|
|
+&usb2phy0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&u2phy0_otg {
|
|
+ vbus-supply = <&vcc5v0_otg>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&u2phy0_host {
|
|
+ status = "okay";
|
|
+ phy-supply = <&vcc5v0_host>;
|
|
+};
|
|
+
|
|
+&combphy1_usq {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+
|
|
+/*************************************************************/
|
|
+&vdpu {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&vdpu_mmu {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&vepu {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&vepu_mmu {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&vop {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&vop_mmu {
|
|
+ status = "okay";
|
|
+};
|
|
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb-x55.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-evb-x55.dtsi
|
|
new file mode 100644
|
|
index 000000000..b272f3db0
|
|
--- /dev/null
|
|
+++ b/arch/arm64/boot/dts/rockchip/rk3568-evb-x55.dtsi
|
|
@@ -0,0 +1,53 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
+/*
|
|
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
|
|
+ */
|
|
+
|
|
+#include "rk3568-x55.dtsi"
|
|
+
|
|
+/ {
|
|
+ aliases {
|
|
+ /delete-property/ ethernet0;
|
|
+ };
|
|
+};
|
|
+
|
|
+&cpu0_opp_table {
|
|
+ /delete-node/ opp-1992000000;
|
|
+};
|
|
+
|
|
+&power {
|
|
+ pd_pipe@RK3568_PD_PIPE {
|
|
+ reg = <RK3568_PD_PIPE>;
|
|
+ clocks = <&cru PCLK_PIPE>;
|
|
+ pm_qos = <&qos_pcie2x1>,
|
|
+ <&qos_sata1>,
|
|
+ <&qos_sata2>,
|
|
+ <&qos_usb3_0>,
|
|
+ <&qos_usb3_1>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&rkisp {
|
|
+ rockchip,iq-feature = /bits/ 64 <0x3FBF7FE67FF>;
|
|
+};
|
|
+
|
|
+&usbdrd_dwc3 {
|
|
+ phys = <&u2phy0_otg>;
|
|
+ phy-names = "usb2-phy";
|
|
+ extcon = <&usb2phy0>;
|
|
+ maximum-speed = "high-speed";
|
|
+ snps,dis_u2_susphy_quirk;
|
|
+};
|
|
+
|
|
+/delete-node/ &combphy0_us;
|
|
+/delete-node/ &gmac0_clkin;
|
|
+/delete-node/ &gmac0_xpcsclk;
|
|
+/delete-node/ &gmac0;
|
|
+/delete-node/ &pcie30_phy_grf;
|
|
+/delete-node/ &pcie30phy;
|
|
+/delete-node/ &pcie3x1;
|
|
+/delete-node/ &pcie3x2;
|
|
+/delete-node/ &qos_pcie3x1;
|
|
+/delete-node/ &qos_pcie3x2;
|
|
+/delete-node/ &qos_sata0;
|
|
+/delete-node/ &sata0;
|
|
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-x55.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-x55.dtsi
|
|
new file mode 100644
|
|
index 000000000..58735dcd2
|
|
--- /dev/null
|
|
+++ b/arch/arm64/boot/dts/rockchip/rk3568-x55.dtsi
|
|
@@ -0,0 +1,3497 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
+/*
|
|
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
|
|
+ */
|
|
+
|
|
+#include <dt-bindings/clock/rk3568-cru.h>
|
|
+#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
+#include <dt-bindings/interrupt-controller/irq.h>
|
|
+#include <dt-bindings/pinctrl/rockchip.h>
|
|
+#include <dt-bindings/soc/rockchip,boot-mode.h>
|
|
+#include <dt-bindings/phy/phy.h>
|
|
+#include <dt-bindings/power/rk3568-power.h>
|
|
+#include <dt-bindings/soc/rockchip-system-status.h>
|
|
+#include <dt-bindings/suspend/rockchip-rk3568.h>
|
|
+#include <dt-bindings/thermal/thermal.h>
|
|
+#include "rk3568-dram-default-timing.dtsi"
|
|
+
|
|
+/ {
|
|
+ compatible = "rockchip,rk3568";
|
|
+
|
|
+ interrupt-parent = <&gic>;
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <2>;
|
|
+
|
|
+ aliases {
|
|
+ csi2dphy0 = &csi2_dphy0;
|
|
+ csi2dphy1 = &csi2_dphy1;
|
|
+ csi2dphy2 = &csi2_dphy2;
|
|
+ dsi0 = &dsi0;
|
|
+ dsi1 = &dsi1;
|
|
+ ethernet0 = &gmac0;
|
|
+ ethernet1 = &gmac1;
|
|
+ gpio0 = &gpio0;
|
|
+ gpio1 = &gpio1;
|
|
+ gpio2 = &gpio2;
|
|
+ gpio3 = &gpio3;
|
|
+ gpio4 = &gpio4;
|
|
+ i2c0 = &i2c0;
|
|
+ i2c1 = &i2c1;
|
|
+ i2c2 = &i2c2;
|
|
+ i2c3 = &i2c3;
|
|
+ i2c4 = &i2c4;
|
|
+ i2c5 = &i2c5;
|
|
+ mmc0 = &sdhci;
|
|
+ mmc1 = &sdmmc0;
|
|
+ mmc2 = &sdmmc1;
|
|
+ mmc3 = &sdmmc2;
|
|
+ serial0 = &uart0;
|
|
+ serial1 = &uart1;
|
|
+ serial2 = &uart2;
|
|
+ serial3 = &uart3;
|
|
+ serial4 = &uart4;
|
|
+ serial5 = &uart5;
|
|
+ serial6 = &uart6;
|
|
+ serial7 = &uart7;
|
|
+ serial8 = &uart8;
|
|
+ serial9 = &uart9;
|
|
+ spi0 = &spi0;
|
|
+ spi1 = &spi1;
|
|
+ spi2 = &spi2;
|
|
+ spi3 = &spi3;
|
|
+ spi4 = &sfc; // for U-Boot
|
|
+ };
|
|
+
|
|
+ cpus {
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ cpu0: cpu@0 {
|
|
+ device_type = "cpu";
|
|
+ compatible = "arm,cortex-a55";
|
|
+ reg = <0x0 0x0>;
|
|
+ enable-method = "psci";
|
|
+ clocks = <&scmi_clk 0>;
|
|
+ operating-points-v2 = <&cpu0_opp_table>;
|
|
+ cpu-idle-states = <&CPU_SLEEP>;
|
|
+ #cooling-cells = <2>;
|
|
+ dynamic-power-coefficient = <187>;
|
|
+ };
|
|
+
|
|
+ cpu1: cpu@100 {
|
|
+ device_type = "cpu";
|
|
+ compatible = "arm,cortex-a55";
|
|
+ reg = <0x0 0x100>;
|
|
+ enable-method = "psci";
|
|
+ clocks = <&scmi_clk 0>;
|
|
+ operating-points-v2 = <&cpu0_opp_table>;
|
|
+ cpu-idle-states = <&CPU_SLEEP>;
|
|
+ };
|
|
+
|
|
+ cpu2: cpu@200 {
|
|
+ device_type = "cpu";
|
|
+ compatible = "arm,cortex-a55";
|
|
+ reg = <0x0 0x200>;
|
|
+ enable-method = "psci";
|
|
+ clocks = <&scmi_clk 0>;
|
|
+ operating-points-v2 = <&cpu0_opp_table>;
|
|
+ cpu-idle-states = <&CPU_SLEEP>;
|
|
+ };
|
|
+
|
|
+ cpu3: cpu@300 {
|
|
+ device_type = "cpu";
|
|
+ compatible = "arm,cortex-a55";
|
|
+ reg = <0x0 0x300>;
|
|
+ enable-method = "psci";
|
|
+ clocks = <&scmi_clk 0>;
|
|
+ operating-points-v2 = <&cpu0_opp_table>;
|
|
+ cpu-idle-states = <&CPU_SLEEP>;
|
|
+ };
|
|
+
|
|
+ idle-states {
|
|
+ entry-method = "psci";
|
|
+ CPU_SLEEP: cpu-sleep {
|
|
+ compatible = "arm,idle-state";
|
|
+ local-timer-stop;
|
|
+ arm,psci-suspend-param = <0x0010000>;
|
|
+ entry-latency-us = <100>;
|
|
+ exit-latency-us = <120>;
|
|
+ min-residency-us = <1000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ cpu0_opp_table: cpu0-opp-table {
|
|
+ compatible = "operating-points-v2";
|
|
+ opp-shared;
|
|
+
|
|
+ mbist-vmin = <825000 900000 950000>;
|
|
+ nvmem-cells = <&cpu_leakage>, <&core_pvtm>, <&mbist_vmin>;
|
|
+ nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
|
|
+ rockchip,pvtm-voltage-sel = <
|
|
+ 0 82000 0
|
|
+ 82001 93000 1
|
|
+ 93001 100000 2
|
|
+ >;
|
|
+ rockchip,pvtm-freq = <408000>;
|
|
+ rockchip,pvtm-volt = <900000>;
|
|
+ rockchip,pvtm-ch = <0 5>;
|
|
+ rockchip,pvtm-sample-time = <1000>;
|
|
+ rockchip,pvtm-number = <10>;
|
|
+ rockchip,pvtm-error = <1000>;
|
|
+ rockchip,pvtm-ref-temp = <40>;
|
|
+ rockchip,pvtm-temp-prop = <26 26>;
|
|
+ rockchip,thermal-zone = "soc-thermal";
|
|
+ rockchip,temp-hysteresis = <5000>;
|
|
+ rockchip,low-temp = <0>;
|
|
+ rockchip,low-temp-adjust-volt = <
|
|
+ /* MHz MHz uV */
|
|
+ 0 1608 75000
|
|
+ >;
|
|
+
|
|
+ opp-408000000 {
|
|
+ opp-hz = /bits/ 64 <408000000>;
|
|
+ opp-microvolt = <825000 825000 1150000>;
|
|
+ clock-latency-ns = <40000>;
|
|
+ };
|
|
+ opp-600000000 {
|
|
+ opp-hz = /bits/ 64 <600000000>;
|
|
+ opp-microvolt = <825000 825000 1150000>;
|
|
+ clock-latency-ns = <40000>;
|
|
+ };
|
|
+ opp-816000000 {
|
|
+ opp-hz = /bits/ 64 <816000000>;
|
|
+ opp-microvolt = <825000 825000 1150000>;
|
|
+ clock-latency-ns = <40000>;
|
|
+ opp-suspend;
|
|
+ };
|
|
+ opp-1104000000 {
|
|
+ opp-hz = /bits/ 64 <1104000000>;
|
|
+ opp-microvolt = <825000 825000 1150000>;
|
|
+ clock-latency-ns = <40000>;
|
|
+ };
|
|
+ opp-1416000000 {
|
|
+ opp-hz = /bits/ 64 <1416000000>;
|
|
+ opp-microvolt = <925000 925000 1150000>;
|
|
+ clock-latency-ns = <40000>;
|
|
+ };
|
|
+ opp-1608000000 {
|
|
+ opp-hz = /bits/ 64 <1608000000>;
|
|
+ opp-microvolt = <1000000 1000000 1150000>;
|
|
+ clock-latency-ns = <40000>;
|
|
+ };
|
|
+ opp-1800000000 {
|
|
+ opp-hz = /bits/ 64 <1800000000>;
|
|
+ opp-microvolt = <1050000 1050000 1150000>;
|
|
+ clock-latency-ns = <40000>;
|
|
+ };
|
|
+ opp-1992000000 {
|
|
+ opp-hz = /bits/ 64 <1992000000>;
|
|
+ opp-microvolt = <1150000 1150000 1150000>;
|
|
+ clock-latency-ns = <40000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ arm-pmu {
|
|
+ compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3";
|
|
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
|
|
+ };
|
|
+
|
|
+ cpuinfo {
|
|
+ compatible = "rockchip,cpuinfo";
|
|
+ nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>;
|
|
+ nvmem-cell-names = "id", "cpu-version", "cpu-code";
|
|
+ };
|
|
+
|
|
+ display_subsystem: display-subsystem {
|
|
+ compatible = "rockchip,display-subsystem";
|
|
+ memory-region = <&drm_logo>, <&drm_cubic_lut>;
|
|
+ memory-region-names = "drm-logo", "drm-cubic-lut";
|
|
+ ports = <&vop_out>;
|
|
+ devfreq = <&dmc>;
|
|
+
|
|
+ route {
|
|
+ route_dsi0: route-dsi0 {
|
|
+ status = "disabled";
|
|
+ logo,uboot = "logo.bmp";
|
|
+ logo,kernel = "logo_kernel.bmp";
|
|
+ logo,mode = "center";
|
|
+ charge_logo,mode = "center";
|
|
+ connect = <&vp0_out_dsi0>;
|
|
+ };
|
|
+ route_dsi1: route-dsi1 {
|
|
+ status = "disabled";
|
|
+ logo,uboot = "logo.bmp";
|
|
+ logo,kernel = "logo_kernel.bmp";
|
|
+ logo,mode = "center";
|
|
+ charge_logo,mode = "center";
|
|
+ connect = <&vp0_out_dsi1>;
|
|
+ };
|
|
+ route_edp: route-edp {
|
|
+ status = "disabled";
|
|
+ logo,uboot = "logo.bmp";
|
|
+ logo,kernel = "logo_kernel.bmp";
|
|
+ logo,mode = "center";
|
|
+ charge_logo,mode = "center";
|
|
+ connect = <&vp0_out_edp>;
|
|
+ };
|
|
+ route_hdmi: route-hdmi {
|
|
+ status = "disabled";
|
|
+ logo,uboot = "logo.bmp";
|
|
+ logo,kernel = "logo_kernel.bmp";
|
|
+ logo,mode = "center";
|
|
+ charge_logo,mode = "center";
|
|
+ connect = <&vp1_out_hdmi>;
|
|
+ };
|
|
+ route_lvds: route-lvds {
|
|
+ status = "disabled";
|
|
+ logo,uboot = "logo.bmp";
|
|
+ logo,kernel = "logo_kernel.bmp";
|
|
+ logo,mode = "center";
|
|
+ charge_logo,mode = "center";
|
|
+ connect = <&vp1_out_lvds>;
|
|
+ };
|
|
+ route_rgb: route-rgb {
|
|
+ status = "disabled";
|
|
+ logo,uboot = "logo.bmp";
|
|
+ logo,kernel = "logo_kernel.bmp";
|
|
+ logo,mode = "center";
|
|
+ charge_logo,mode = "center";
|
|
+ connect = <&vp2_out_rgb>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ firmware {
|
|
+ optee: optee {
|
|
+ compatible = "linaro,optee-tz";
|
|
+ method = "smc";
|
|
+ };
|
|
+
|
|
+ scmi: scmi {
|
|
+ compatible = "arm,scmi-smc";
|
|
+ shmem = <&scmi_shmem>;
|
|
+ arm,smc-id = <0x82000010>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ scmi_clk: protocol@14 {
|
|
+ reg = <0x14>;
|
|
+ #clock-cells = <1>;
|
|
+
|
|
+ rockchip,clk-init = <1416000000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdei: sdei {
|
|
+ compatible = "arm,sdei-1.0";
|
|
+ method = "smc";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ mpp_srv: mpp-srv {
|
|
+ compatible = "rockchip,mpp-service";
|
|
+ rockchip,taskqueue-count = <6>;
|
|
+ rockchip,resetgroup-count = <6>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ psci {
|
|
+ compatible = "arm,psci-1.0";
|
|
+ method = "smc";
|
|
+ };
|
|
+
|
|
+ reserved_memory: reserved-memory {
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <2>;
|
|
+ ranges;
|
|
+
|
|
+ drm_logo: drm-logo@00000000 {
|
|
+ compatible = "rockchip,drm-logo";
|
|
+ reg = <0x0 0x0 0x0 0x0>;
|
|
+ };
|
|
+
|
|
+ drm_cubic_lut: drm-cubic-lut@00000000 {
|
|
+ compatible = "rockchip,drm-cubic-lut";
|
|
+ reg = <0x0 0x0 0x0 0x0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ rockchip_suspend: rockchip-suspend {
|
|
+ compatible = "rockchip,pm-rk3568";
|
|
+ status = "disabled";
|
|
+ rockchip,sleep-debug-en = <1>;
|
|
+ rockchip,sleep-mode-config = <
|
|
+ (0
|
|
+ | RKPM_SLP_ARMOFF_LOGOFF
|
|
+ | RKPM_SLP_CENTER_OFF
|
|
+ | RKPM_SLP_HW_PLLS_OFF
|
|
+ | RKPM_SLP_PMUALIVE_32K
|
|
+ | RKPM_SLP_OSC_DIS
|
|
+ | RKPM_SLP_PMIC_LP
|
|
+ | RKPM_SLP_32K_PVTM
|
|
+ )
|
|
+ >;
|
|
+ rockchip,wakeup-config = <
|
|
+ (0
|
|
+ | RKPM_GPIO_WKUP_EN
|
|
+ )
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ rockchip_system_monitor: rockchip-system-monitor {
|
|
+ compatible = "rockchip,system-monitor";
|
|
+
|
|
+ rockchip,thermal-zone = "soc-thermal";
|
|
+ };
|
|
+
|
|
+ thermal_zones: thermal-zones {
|
|
+ soc_thermal: soc-thermal {
|
|
+ polling-delay-passive = <20>; /* milliseconds */
|
|
+ polling-delay = <1000>; /* milliseconds */
|
|
+ sustainable-power = <905>; /* milliwatts */
|
|
+
|
|
+ thermal-sensors = <&tsadc 0>;
|
|
+ trips {
|
|
+ threshold: trip-point-0 {
|
|
+ temperature = <75000>;
|
|
+ hysteresis = <2000>;
|
|
+ type = "passive";
|
|
+ };
|
|
+ target: trip-point-1 {
|
|
+ temperature = <85000>;
|
|
+ hysteresis = <2000>;
|
|
+ type = "passive";
|
|
+ };
|
|
+ soc_crit: soc-crit {
|
|
+ /* millicelsius */
|
|
+ temperature = <115000>;
|
|
+ /* millicelsius */
|
|
+ hysteresis = <2000>;
|
|
+ type = "critical";
|
|
+ };
|
|
+ };
|
|
+ cooling-maps {
|
|
+ map0 {
|
|
+ trip = <&target>;
|
|
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
+ contribution = <1024>;
|
|
+ };
|
|
+ map1 {
|
|
+ trip = <&target>;
|
|
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
+ contribution = <1024>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ gpu_thermal: gpu-thermal {
|
|
+ polling-delay-passive = <20>; /* milliseconds */
|
|
+ polling-delay = <1000>; /* milliseconds */
|
|
+
|
|
+ thermal-sensors = <&tsadc 1>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ timer {
|
|
+ compatible = "arm,armv8-timer";
|
|
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
|
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
|
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
|
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
+ arm,no-tick-in-suspend;
|
|
+ };
|
|
+
|
|
+ gmac0_clkin: external-gmac0-clock {
|
|
+ compatible = "fixed-clock";
|
|
+ clock-frequency = <125000000>;
|
|
+ clock-output-names = "gmac0_clkin";
|
|
+ #clock-cells = <0>;
|
|
+ };
|
|
+
|
|
+ gmac1_clkin: external-gmac1-clock {
|
|
+ compatible = "fixed-clock";
|
|
+ clock-frequency = <125000000>;
|
|
+ clock-output-names = "gmac1_clkin";
|
|
+ #clock-cells = <0>;
|
|
+ };
|
|
+
|
|
+ gmac0_xpcsclk: xpcs-gmac0-clock {
|
|
+ compatible = "fixed-clock";
|
|
+ clock-frequency = <125000000>;
|
|
+ clock-output-names = "clk_gmac0_xpcs_mii";
|
|
+ #clock-cells = <0>;
|
|
+ };
|
|
+
|
|
+ gmac1_xpcsclk: xpcs-gmac1-clock {
|
|
+ compatible = "fixed-clock";
|
|
+ clock-frequency = <125000000>;
|
|
+ clock-output-names = "clk_gmac1_xpcs_mii";
|
|
+ #clock-cells = <0>;
|
|
+ };
|
|
+
|
|
+ i2s1_mclkin_rx: i2s1-mclkin-rx {
|
|
+ compatible = "fixed-clock";
|
|
+ #clock-cells = <0>;
|
|
+ clock-frequency = <12288000>;
|
|
+ clock-output-names = "i2s1_mclkin_rx";
|
|
+ };
|
|
+
|
|
+ i2s1_mclkin_tx: i2s1-mclkin-tx {
|
|
+ compatible = "fixed-clock";
|
|
+ #clock-cells = <0>;
|
|
+ clock-frequency = <12288000>;
|
|
+ clock-output-names = "i2s1_mclkin_tx";
|
|
+ };
|
|
+
|
|
+ i2s2_mclkin: i2s2-mclkin {
|
|
+ compatible = "fixed-clock";
|
|
+ #clock-cells = <0>;
|
|
+ clock-frequency = <12288000>;
|
|
+ clock-output-names = "i2s2_mclkin";
|
|
+ };
|
|
+
|
|
+ i2s3_mclkin: i2s3-mclkin {
|
|
+ compatible = "fixed-clock";
|
|
+ #clock-cells = <0>;
|
|
+ clock-frequency = <12288000>;
|
|
+ clock-output-names = "i2s3_mclkin";
|
|
+ };
|
|
+
|
|
+ mpll: mpll {
|
|
+ compatible = "fixed-clock";
|
|
+ #clock-cells = <0>;
|
|
+ clock-frequency = <800000000>;
|
|
+ clock-output-names = "mpll";
|
|
+ };
|
|
+
|
|
+ xin24m: xin24m {
|
|
+ compatible = "fixed-clock";
|
|
+ #clock-cells = <0>;
|
|
+ clock-frequency = <24000000>;
|
|
+ clock-output-names = "xin24m";
|
|
+ };
|
|
+
|
|
+ xin32k: xin32k {
|
|
+ compatible = "fixed-clock";
|
|
+ clock-frequency = <32768>;
|
|
+ clock-output-names = "xin32k";
|
|
+ #clock-cells = <0>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&clk32k_out0>;
|
|
+ };
|
|
+
|
|
+ scmi_shmem: scmi-shmem@10f000 {
|
|
+ compatible = "arm,scmi-shmem";
|
|
+ reg = <0x0 0x0010f000 0x0 0x100>;
|
|
+ };
|
|
+
|
|
+ sata0: sata@fc000000 {
|
|
+ compatible = "snps,dwc-ahci";
|
|
+ reg = <0 0xfc000000 0 0x1000>;
|
|
+ clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
|
|
+ <&cru CLK_SATA0_RXOOB>;
|
|
+ clock-names = "sata", "pmalive", "rxoob";
|
|
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "hostc";
|
|
+ phys = <&combphy0_us PHY_TYPE_SATA>;
|
|
+ phy-names = "sata-phy";
|
|
+ ports-implemented = <0x1>;
|
|
+ power-domains = <&power RK3568_PD_PIPE>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ sata1: sata@fc400000 {
|
|
+ compatible = "snps,dwc-ahci";
|
|
+ reg = <0 0xfc400000 0 0x1000>;
|
|
+ clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
|
|
+ <&cru CLK_SATA1_RXOOB>;
|
|
+ clock-names = "sata", "pmalive", "rxoob";
|
|
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "hostc";
|
|
+ phys = <&combphy1_usq PHY_TYPE_SATA>;
|
|
+ phy-names = "sata-phy";
|
|
+ ports-implemented = <0x1>;
|
|
+ power-domains = <&power RK3568_PD_PIPE>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ sata2: sata@fc800000 {
|
|
+ compatible = "snps,dwc-ahci";
|
|
+ reg = <0 0xfc800000 0 0x1000>;
|
|
+ clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
|
|
+ <&cru CLK_SATA2_RXOOB>;
|
|
+ clock-names = "sata", "pmalive", "rxoob";
|
|
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "hostc";
|
|
+ phys = <&combphy2_psq PHY_TYPE_SATA>;
|
|
+ phy-names = "sata-phy";
|
|
+ ports-implemented = <0x1>;
|
|
+ power-domains = <&power RK3568_PD_PIPE>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usbdrd30: usbdrd {
|
|
+ compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
|
|
+ clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
|
|
+ <&cru ACLK_USB3OTG0>, <&cru PCLK_PIPE>;
|
|
+ clock-names = "ref_clk", "suspend_clk",
|
|
+ "bus_clk", "pipe_clk";
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <2>;
|
|
+ ranges;
|
|
+ status = "disabled";
|
|
+
|
|
+ usbdrd_dwc3: dwc3@fcc00000 {
|
|
+ compatible = "snps,dwc3";
|
|
+ reg = <0x0 0xfcc00000 0x0 0x400000>;
|
|
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ dr_mode = "otg";
|
|
+ phys = <&u2phy0_otg>, <&combphy0_us PHY_TYPE_USB3>;
|
|
+ phy-names = "usb2-phy", "usb3-phy";
|
|
+ phy_type = "utmi_wide";
|
|
+ power-domains = <&power RK3568_PD_PIPE>;
|
|
+ resets = <&cru SRST_USB3OTG0>;
|
|
+ reset-names = "usb3-otg";
|
|
+ snps,dis_enblslpm_quirk;
|
|
+ snps,dis-u1u2-quirk;
|
|
+ snps,dis-u2-freeclk-exists-quirk;
|
|
+ snps,dis-del-phy-power-chg-quirk;
|
|
+ snps,dis-tx-ipgap-linecheck-quirk;
|
|
+ snps,dis_rxdet_inp3_quirk;
|
|
+ snps,xhci-trb-ent-quirk;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usbhost30: usbhost {
|
|
+ compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
|
|
+ clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
|
|
+ <&cru ACLK_USB3OTG1>, <&cru PCLK_PIPE>;
|
|
+ clock-names = "ref_clk", "suspend_clk",
|
|
+ "bus_clk", "pipe_clk";
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <2>;
|
|
+ ranges;
|
|
+ status = "disabled";
|
|
+
|
|
+ usbhost_dwc3: dwc3@fd000000 {
|
|
+ compatible = "snps,dwc3";
|
|
+ reg = <0x0 0xfd000000 0x0 0x400000>;
|
|
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ dr_mode = "host";
|
|
+ phys = <&u2phy0_host>, <&combphy1_usq PHY_TYPE_USB3>;
|
|
+ phy-names = "usb2-phy", "usb3-phy";
|
|
+ phy_type = "utmi_wide";
|
|
+ power-domains = <&power RK3568_PD_PIPE>;
|
|
+ resets = <&cru SRST_USB3OTG1>;
|
|
+ reset-names = "usb3-host";
|
|
+ snps,dis_enblslpm_quirk;
|
|
+ snps,dis-u2-freeclk-exists-quirk;
|
|
+ snps,dis-del-phy-power-chg-quirk;
|
|
+ snps,dis-tx-ipgap-linecheck-quirk;
|
|
+ snps,dis_rxdet_inp3_quirk;
|
|
+ snps,xhci-trb-ent-quirk;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ gic: interrupt-controller@fd400000 {
|
|
+ compatible = "arm,gic-v3";
|
|
+ #interrupt-cells = <3>;
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <2>;
|
|
+ ranges;
|
|
+ interrupt-controller;
|
|
+
|
|
+ reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
|
|
+ <0x0 0xfd460000 0 0xc0000>; /* GICR */
|
|
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ its: interrupt-controller@fd440000 {
|
|
+ compatible = "arm,gic-v3-its";
|
|
+ msi-controller;
|
|
+ #msi-cells = <1>;
|
|
+ reg = <0x0 0xfd440000 0x0 0x20000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usb_host0_ehci: usb@fd800000 {
|
|
+ compatible = "generic-ehci";
|
|
+ reg = <0x0 0xfd800000 0x0 0x40000>;
|
|
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
|
|
+ <&cru PCLK_USB>, <&usb2phy1>;
|
|
+ clock-names = "usbhost", "arbiter", "pclk", "utmi";
|
|
+ phys = <&u2phy1_otg>;
|
|
+ phy-names = "usb2-phy";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb_host0_ohci: usb@fd840000 {
|
|
+ compatible = "generic-ohci";
|
|
+ reg = <0x0 0xfd840000 0x0 0x40000>;
|
|
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
|
|
+ <&cru PCLK_USB>, <&usb2phy1>;
|
|
+ clock-names = "usbhost", "arbiter", "pclk", "utmi";
|
|
+ phys = <&u2phy1_otg>;
|
|
+ phy-names = "usb2-phy";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb_host1_ehci: usb@fd880000 {
|
|
+ compatible = "generic-ehci";
|
|
+ reg = <0x0 0xfd880000 0x0 0x40000>;
|
|
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
|
|
+ <&cru PCLK_USB>, <&usb2phy1>;
|
|
+ clock-names = "usbhost", "arbiter", "pclk", "utmi";
|
|
+ phys = <&u2phy1_host>;
|
|
+ phy-names = "usb2-phy";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb_host1_ohci: usb@fd8c0000 {
|
|
+ compatible = "generic-ohci";
|
|
+ reg = <0x0 0xfd8c0000 0x0 0x40000>;
|
|
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
|
|
+ <&cru PCLK_USB>, <&usb2phy1>;
|
|
+ clock-names = "usbhost", "arbiter", "pclk", "utmi";
|
|
+ phys = <&u2phy1_host>;
|
|
+ phy-names = "usb2-phy";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ xpcs: syscon@fda00000 {
|
|
+ compatible = "rockchip,rk3568-xpcs", "syscon";
|
|
+ reg = <0x0 0xfda00000 0x0 0x200000>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pmugrf: syscon@fdc20000 {
|
|
+ compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
|
|
+ reg = <0x0 0xfdc20000 0x0 0x10000>;
|
|
+
|
|
+ pmu_io_domains: io-domains {
|
|
+ compatible = "rockchip,rk3568-pmu-io-voltage-domain";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ reboot_mode: reboot-mode {
|
|
+ compatible = "syscon-reboot-mode";
|
|
+ offset = <0x200>;
|
|
+ mode-bootloader = <BOOT_BL_DOWNLOAD>;
|
|
+ mode-charge = <BOOT_CHARGING>;
|
|
+ mode-fastboot = <BOOT_FASTBOOT>;
|
|
+ mode-loader = <BOOT_BL_DOWNLOAD>;
|
|
+ mode-normal = <BOOT_NORMAL>;
|
|
+ mode-recovery = <BOOT_RECOVERY>;
|
|
+ mode-ums = <BOOT_UMS>;
|
|
+ mode-panic = <BOOT_PANIC>;
|
|
+ mode-watchdog = <BOOT_WATCHDOG>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pipegrf: syscon@fdc50000 {
|
|
+ compatible = "rockchip,rk3568-pipegrf", "syscon";
|
|
+ reg = <0x0 0xfdc50000 0x0 0x1000>;
|
|
+ };
|
|
+
|
|
+ grf: syscon@fdc60000 {
|
|
+ compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
|
|
+ reg = <0x0 0xfdc60000 0x0 0x10000>;
|
|
+
|
|
+ io_domains: io-domains {
|
|
+ compatible = "rockchip,rk3568-io-voltage-domain";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ lvds: lvds {
|
|
+ compatible = "rockchip,rk3568-lvds";
|
|
+ phys = <&video_phy0>;
|
|
+ phy-names = "phy";
|
|
+ status = "disabled";
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ port@0 {
|
|
+ reg = <0>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ lvds_in_vp1: endpoint@1 {
|
|
+ reg = <1>;
|
|
+ remote-endpoint = <&vp1_out_lvds>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ lvds_in_vp2: endpoint@2 {
|
|
+ reg = <2>;
|
|
+ remote-endpoint = <&vp2_out_lvds>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ rgb: rgb {
|
|
+ compatible = "rockchip,rk3568-rgb";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&lcdc_ctl>;
|
|
+ status = "disabled";
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ port@0 {
|
|
+ reg = <0>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ rgb_in_vp2: endpoint@2 {
|
|
+ reg = <2>;
|
|
+ remote-endpoint = <&vp2_out_rgb>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ };
|
|
+
|
|
+ pipe_phy_grf0: syscon@fdc70000 {
|
|
+ compatible = "rockchip,pipe-phy-grf", "syscon";
|
|
+ reg = <0x0 0xfdc70000 0x0 0x1000>;
|
|
+ };
|
|
+
|
|
+ pipe_phy_grf1: syscon@fdc80000 {
|
|
+ compatible = "rockchip,pipe-phy-grf", "syscon";
|
|
+ reg = <0x0 0xfdc80000 0x0 0x1000>;
|
|
+ };
|
|
+
|
|
+ pipe_phy_grf2: syscon@fdc90000 {
|
|
+ compatible = "rockchip,pipe-phy-grf", "syscon";
|
|
+ reg = <0x0 0xfdc90000 0x0 0x1000>;
|
|
+ };
|
|
+
|
|
+ usb2phy0_grf: syscon@fdca0000 {
|
|
+ compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
|
|
+ reg = <0x0 0xfdca0000 0x0 0x8000>;
|
|
+ };
|
|
+
|
|
+ usb2phy1_grf: syscon@fdca8000 {
|
|
+ compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
|
|
+ reg = <0x0 0xfdca8000 0x0 0x8000>;
|
|
+ };
|
|
+
|
|
+ edp_phy: edp-phy@fdcb0000 {
|
|
+ compatible = "rockchip,rk3568-edp-phy";
|
|
+ reg = <0x0 0xfdcb0000 0x0 0x8000>;
|
|
+ clocks = <&pmucru XIN_OSC0_EDPPHY_G>, <&cru PCLK_EDPPHY_GRF>;
|
|
+ clock-names = "refclk", "pclk";
|
|
+ resets = <&cru SRST_P_EDPPHY_GRF>;
|
|
+ reset-names = "apb";
|
|
+ #phy-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pcie30_phy_grf: syscon@fdcb8000 {
|
|
+ compatible = "rockchip,pcie30-phy-grf", "syscon";
|
|
+ reg = <0x0 0xfdcb8000 0x0 0x10000>;
|
|
+ };
|
|
+
|
|
+ sram: sram@fdcc0000 {
|
|
+ compatible = "mmio-sram";
|
|
+ reg = <0x0 0xfdcc0000 0x0 0xb000>;
|
|
+
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ ranges = <0x0 0x0 0xfdcc0000 0xb000>;
|
|
+
|
|
+ /* start address and size should be 4k algin */
|
|
+ rkvdec_sram: rkvdec-sram@0 {
|
|
+ reg = <0x0 0xb000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pmucru: clock-controller@fdd00000 {
|
|
+ compatible = "rockchip,rk3568-pmucru";
|
|
+ reg = <0x0 0xfdd00000 0x0 0x1000>;
|
|
+ rockchip,grf = <&grf>;
|
|
+ rockchip,pmugrf = <&pmugrf>;
|
|
+ #clock-cells = <1>;
|
|
+ #reset-cells = <1>;
|
|
+
|
|
+ assigned-clocks = <&pmucru SCLK_32K_IOE>;
|
|
+ assigned-clock-parents = <&pmucru CLK_RTC_32K>;
|
|
+ };
|
|
+
|
|
+ cru: clock-controller@fdd20000 {
|
|
+ compatible = "rockchip,rk3568-cru";
|
|
+ reg = <0x0 0xfdd20000 0x0 0x1000>;
|
|
+ rockchip,grf = <&grf>;
|
|
+ #clock-cells = <1>;
|
|
+ #reset-cells = <1>;
|
|
+
|
|
+ assigned-clocks =
|
|
+ <&pmucru CLK_RTC_32K>, <&cru ACLK_RKVDEC_PRE>,
|
|
+ <&cru CLK_RKVDEC_CORE>, <&pmucru PLL_PPLL>,
|
|
+ <&pmucru PCLK_PMU>, <&cru PLL_CPLL>,
|
|
+ <&cru CPLL_500M>, <&cru CPLL_333M>,
|
|
+ <&cru CPLL_250M>, <&cru CPLL_125M>,
|
|
+ <&cru CPLL_100M>, <&cru CPLL_62P5M>,
|
|
+ <&cru CPLL_50M>, <&cru CPLL_25M>,
|
|
+ <&cru PLL_GPLL>,
|
|
+ <&cru ACLK_BUS>, <&cru PCLK_BUS>,
|
|
+ <&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>,
|
|
+ <&cru HCLK_TOP>, <&cru PCLK_TOP>,
|
|
+ <&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>,
|
|
+ <&cru PLL_NPLL>, <&cru ACLK_PIPE>,
|
|
+ <&cru PCLK_PIPE>, <&cru CLK_I2S0_8CH_TX_SRC>,
|
|
+ <&cru CLK_I2S0_8CH_RX_SRC>, <&cru CLK_I2S1_8CH_TX_SRC>,
|
|
+ <&cru CLK_I2S1_8CH_RX_SRC>, <&cru CLK_I2S2_2CH_SRC>,
|
|
+ <&cru CLK_I2S2_2CH_SRC>, <&cru CLK_I2S3_2CH_RX_SRC>,
|
|
+ <&cru CLK_I2S3_2CH_TX_SRC>, <&cru MCLK_SPDIF_8CH_SRC>,
|
|
+ <&cru ACLK_VOP>;
|
|
+ assigned-clock-rates =
|
|
+ <32768>, <300000000>,
|
|
+ <300000000>, <200000000>,
|
|
+ <100000000>, <1000000000>,
|
|
+ <500000000>, <333000000>,
|
|
+ <250000000>, <125000000>,
|
|
+ <100000000>, <62500000>,
|
|
+ <50000000>, <25000000>,
|
|
+ <1188000000>,
|
|
+ <150000000>, <100000000>,
|
|
+ <500000000>, <400000000>,
|
|
+ <150000000>, <100000000>,
|
|
+ <300000000>, <150000000>,
|
|
+ <1200000000>, <400000000>,
|
|
+ <100000000>, <1188000000>,
|
|
+ <1188000000>, <1188000000>,
|
|
+ <1188000000>, <1188000000>,
|
|
+ <1188000000>, <1188000000>,
|
|
+ <1188000000>, <1188000000>,
|
|
+ <500000000>;
|
|
+ assigned-clock-parents =
|
|
+ <&pmucru CLK_RTC32K_FRAC>, <&cru PLL_GPLL>,
|
|
+ <&cru PLL_GPLL>;
|
|
+ };
|
|
+
|
|
+ i2c0: i2c@fdd40000 {
|
|
+ compatible = "rockchip,rk3399-i2c";
|
|
+ reg = <0x0 0xfdd40000 0x0 0x1000>;
|
|
+ clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
|
|
+ clock-names = "i2c", "pclk";
|
|
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c0_xfer>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart0: serial@fdd50000 {
|
|
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
+ reg = <0x0 0xfdd50000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
|
|
+ clock-names = "baudclk", "apb_pclk";
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ dmas = <&dmac0 0>, <&dmac0 1>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart0_xfer>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm0: pwm@fdd70000 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfdd70000 0x0 0x10>;
|
|
+ #pwm-cells = <3>;
|
|
+ pinctrl-names = "active";
|
|
+ pinctrl-0 = <&pwm0m0_pins>;
|
|
+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm1: pwm@fdd70010 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfdd70010 0x0 0x10>;
|
|
+ #pwm-cells = <3>;
|
|
+ pinctrl-names = "active";
|
|
+ pinctrl-0 = <&pwm1m0_pins>;
|
|
+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm2: pwm@fdd70020 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfdd70020 0x0 0x10>;
|
|
+ #pwm-cells = <3>;
|
|
+ pinctrl-names = "active";
|
|
+ pinctrl-0 = <&pwm2m0_pins>;
|
|
+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm3: pwm@fdd70030 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfdd70030 0x0 0x10>;
|
|
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ #pwm-cells = <3>;
|
|
+ pinctrl-names = "active";
|
|
+ pinctrl-0 = <&pwm3_pins>;
|
|
+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pmu: power-management@fdd90000 {
|
|
+ compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
|
|
+ reg = <0x0 0xfdd90000 0x0 0x1000>;
|
|
+
|
|
+ power: power-controller {
|
|
+ compatible = "rockchip,rk3568-power-controller";
|
|
+ #power-domain-cells = <1>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "okay";
|
|
+
|
|
+ /* These power domains are grouped by VD_NPU */
|
|
+ pd_npu@RK3568_PD_NPU {
|
|
+ reg = <RK3568_PD_NPU>;
|
|
+ clocks = <&cru ACLK_NPU_PRE>,
|
|
+ <&cru HCLK_NPU_PRE>,
|
|
+ <&cru PCLK_NPU_PRE>;
|
|
+ pm_qos = <&qos_npu>;
|
|
+ };
|
|
+ /* These power domains are grouped by VD_GPU */
|
|
+ pd_gpu@RK3568_PD_GPU {
|
|
+ reg = <RK3568_PD_GPU>;
|
|
+ clocks = <&cru ACLK_GPU_PRE>,
|
|
+ <&cru PCLK_GPU_PRE>;
|
|
+ pm_qos = <&qos_gpu>;
|
|
+ };
|
|
+ /* These power domains are grouped by VD_LOGIC */
|
|
+ pd_vi@RK3568_PD_VI {
|
|
+ reg = <RK3568_PD_VI>;
|
|
+ clocks = <&cru HCLK_VI>,
|
|
+ <&cru PCLK_VI>;
|
|
+ pm_qos = <&qos_isp>,
|
|
+ <&qos_vicap0>,
|
|
+ <&qos_vicap1>;
|
|
+ };
|
|
+ pd_vo@RK3568_PD_VO {
|
|
+ reg = <RK3568_PD_VO>;
|
|
+ clocks = <&cru HCLK_VO>,
|
|
+ <&cru PCLK_VO>,
|
|
+ <&cru ACLK_VOP_PRE>;
|
|
+ pm_qos = <&qos_hdcp>,
|
|
+ <&qos_vop_m0>,
|
|
+ <&qos_vop_m1>;
|
|
+ };
|
|
+ pd_rga@RK3568_PD_RGA {
|
|
+ reg = <RK3568_PD_RGA>;
|
|
+ clocks = <&cru HCLK_RGA_PRE>,
|
|
+ <&cru PCLK_RGA_PRE>;
|
|
+ pm_qos = <&qos_ebc>,
|
|
+ <&qos_iep>,
|
|
+ <&qos_jpeg_dec>,
|
|
+ <&qos_jpeg_enc>,
|
|
+ <&qos_rga_rd>,
|
|
+ <&qos_rga_wr>;
|
|
+ };
|
|
+ pd_vpu@RK3568_PD_VPU {
|
|
+ reg = <RK3568_PD_VPU>;
|
|
+ clocks = <&cru HCLK_VPU_PRE>;
|
|
+ pm_qos = <&qos_vpu>;
|
|
+ };
|
|
+ pd_rkvdec@RK3568_PD_RKVDEC {
|
|
+ clocks = <&cru HCLK_RKVDEC_PRE>;
|
|
+ reg = <RK3568_PD_RKVDEC>;
|
|
+ pm_qos = <&qos_rkvdec>;
|
|
+ };
|
|
+ pd_rkvenc@RK3568_PD_RKVENC {
|
|
+ reg = <RK3568_PD_RKVENC>;
|
|
+ clocks = <&cru HCLK_RKVENC_PRE>;
|
|
+ pm_qos = <&qos_rkvenc_rd_m0>,
|
|
+ <&qos_rkvenc_rd_m1>,
|
|
+ <&qos_rkvenc_wr_m0>;
|
|
+ };
|
|
+ pd_pipe@RK3568_PD_PIPE {
|
|
+ reg = <RK3568_PD_PIPE>;
|
|
+ clocks = <&cru PCLK_PIPE>;
|
|
+ pm_qos = <&qos_pcie2x1>,
|
|
+ <&qos_pcie3x1>,
|
|
+ <&qos_pcie3x2>,
|
|
+ <&qos_sata0>,
|
|
+ <&qos_sata1>,
|
|
+ <&qos_sata2>,
|
|
+ <&qos_usb3_0>,
|
|
+ <&qos_usb3_1>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pvtm@fde00000 {
|
|
+ compatible = "rockchip,rk3568-core-pvtm";
|
|
+ reg = <0x0 0xfde00000 0x0 0x100>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ pvtm@0 {
|
|
+ reg = <0>;
|
|
+ clocks = <&cru CLK_CORE_PVTM>, <&cru PCLK_CORE_PVTM>;
|
|
+ clock-names = "clk", "pclk";
|
|
+ resets = <&cru SRST_CORE_PVTM>, <&cru SRST_P_CORE_PVTM>;
|
|
+ reset-names = "rts", "rst-p";
|
|
+ thermal-zone = "soc-thermal";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ rknpu: npu@fde40000 {
|
|
+ compatible = "rockchip,rk3568-rknpu", "rockchip,rknpu";
|
|
+ reg = <0x0 0xfde40000 0x0 0x10000>;
|
|
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&scmi_clk 2>, <&cru CLK_NPU>, <&cru ACLK_NPU>, <&cru HCLK_NPU>;
|
|
+ clock-names = "scmi_clk", "clk", "aclk", "hclk";
|
|
+ assigned-clocks = <&cru CLK_NPU>;
|
|
+ assigned-clock-rates = <600000000>;
|
|
+ resets = <&cru SRST_A_NPU>, <&cru SRST_H_NPU>;
|
|
+ reset-names = "srst_a", "srst_h";
|
|
+ power-domains = <&power RK3568_PD_NPU>;
|
|
+ operating-points-v2 = <&npu_opp_table>;
|
|
+ iommus = <&rknpu_mmu>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ npu_opp_table: npu-opp-table {
|
|
+ compatible = "operating-points-v2";
|
|
+
|
|
+ mbist-vmin = <825000 900000 950000>;
|
|
+ nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>;
|
|
+ nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
|
|
+ rockchip,temp-hysteresis = <5000>;
|
|
+ rockchip,low-temp = <0>;
|
|
+ rockchip,low-temp-adjust-volt = <
|
|
+ /* MHz MHz uV */
|
|
+ 0 700 50000
|
|
+ >;
|
|
+
|
|
+ opp-200000000 {
|
|
+ opp-hz = /bits/ 64 <200000000>;
|
|
+ opp-microvolt = <825000 825000 1000000>;
|
|
+ };
|
|
+ opp-300000000 {
|
|
+ opp-hz = /bits/ 64 <297000000>;
|
|
+ opp-microvolt = <825000 825000 1000000>;
|
|
+ };
|
|
+ opp-400000000 {
|
|
+ opp-hz = /bits/ 64 <400000000>;
|
|
+ opp-microvolt = <825000 825000 1000000>;
|
|
+ };
|
|
+ opp-600000000 {
|
|
+ opp-hz = /bits/ 64 <600000000>;
|
|
+ opp-microvolt = <825000 825000 1000000>;
|
|
+ };
|
|
+ opp-700000000 {
|
|
+ opp-hz = /bits/ 64 <700000000>;
|
|
+ opp-microvolt = <850000 850000 1000000>;
|
|
+ };
|
|
+ opp-800000000 {
|
|
+ opp-hz = /bits/ 64 <800000000>;
|
|
+ opp-microvolt = <875000 875000 1000000>;
|
|
+ };
|
|
+ opp-900000000 {
|
|
+ opp-hz = /bits/ 64 <900000000>;
|
|
+ opp-microvolt = <925000 925000 1000000>;
|
|
+ };
|
|
+ opp-1000000000 {
|
|
+ opp-hz = /bits/ 64 <1000000000>;
|
|
+ opp-microvolt = <1000000 1000000 1000000>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ bus_npu: bus-npu {
|
|
+ compatible = "rockchip,rk3568-bus";
|
|
+ rockchip,busfreq-policy = "clkfreq";
|
|
+ clocks = <&scmi_clk 2>;
|
|
+ clock-names = "bus";
|
|
+ operating-points-v2 = <&bus_npu_opp_table>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ bus_npu_opp_table: bus-npu-opp-table {
|
|
+ compatible = "operating-points-v2";
|
|
+ opp-shared;
|
|
+
|
|
+ nvmem-cells = <&core_pvtm>;
|
|
+ nvmem-cell-names = "pvtm";
|
|
+ rockchip,pvtm-voltage-sel = <
|
|
+ 0 82000 0
|
|
+ 82001 93000 1
|
|
+ 93001 100000 2
|
|
+ >;
|
|
+ rockchip,pvtm-ch = <0 5>;
|
|
+
|
|
+ opp-700000000 {
|
|
+ opp-hz = /bits/ 64 <700000000>;
|
|
+ opp-microvolt = <0>;
|
|
+ };
|
|
+ opp-900000000 {
|
|
+ opp-hz = /bits/ 64 <900000000>;
|
|
+ opp-microvolt = <900000>;
|
|
+ };
|
|
+ opp-1000000000 {
|
|
+ opp-hz = /bits/ 64 <1000000000>;
|
|
+ opp-microvolt = <950000>;
|
|
+ opp-microvolt-L0 = <950000>;
|
|
+ opp-microvolt-L1 = <925000>;
|
|
+ opp-microvolt-L2 = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ rknpu_mmu: iommu@fde4b000 {
|
|
+ compatible = "rockchip,iommu-v2";
|
|
+ reg = <0x0 0xfde4b000 0x0 0x40>;
|
|
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "rknpu_mmu";
|
|
+ clocks = <&cru ACLK_NPU>, <&cru HCLK_NPU>;
|
|
+ clock-names = "aclk", "iface";
|
|
+ power-domains = <&power RK3568_PD_NPU>;
|
|
+ #iommu-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gpu: gpu@fde60000 {
|
|
+ compatible = "arm,mali-bifrost";
|
|
+ reg = <0x0 0xfde60000 0x0 0x4000>;
|
|
+
|
|
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "GPU", "MMU", "JOB";
|
|
+
|
|
+ upthreshold = <40>;
|
|
+ downdifferential = <10>;
|
|
+
|
|
+ clocks = <&scmi_clk 1>, <&cru CLK_GPU>;
|
|
+ clock-names = "clk_mali", "clk_gpu";
|
|
+ power-domains = <&power RK3568_PD_GPU>;
|
|
+ #cooling-cells = <2>;
|
|
+ operating-points-v2 = <&gpu_opp_table>;
|
|
+
|
|
+ status = "disabled";
|
|
+ gpu_power_model: power-model {
|
|
+ compatible = "simple-power-model";
|
|
+ leakage-range= <5 15>;
|
|
+ ls = <(-24002) 22823 0>;
|
|
+ static-coefficient = <100000>;
|
|
+ dynamic-coefficient = <953>;
|
|
+ ts = <(-108890) 63610 (-1355) 20>;
|
|
+ thermal-zone = "gpu-thermal";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ gpu_opp_table: opp-table2 {
|
|
+ compatible = "operating-points-v2";
|
|
+
|
|
+ mbist-vmin = <825000 900000 950000>;
|
|
+ nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>;
|
|
+ nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
|
|
+
|
|
+ opp-200000000 {
|
|
+ opp-hz = /bits/ 64 <200000000>;
|
|
+ opp-microvolt = <825000>;
|
|
+ };
|
|
+ opp-300000000 {
|
|
+ opp-hz = /bits/ 64 <300000000>;
|
|
+ opp-microvolt = <825000>;
|
|
+ };
|
|
+ opp-400000000 {
|
|
+ opp-hz = /bits/ 64 <400000000>;
|
|
+ opp-microvolt = <825000>;
|
|
+ };
|
|
+ opp-600000000 {
|
|
+ opp-hz = /bits/ 64 <600000000>;
|
|
+ opp-microvolt = <825000>;
|
|
+ };
|
|
+ opp-700000000 {
|
|
+ opp-hz = /bits/ 64 <700000000>;
|
|
+ opp-microvolt = <900000>;
|
|
+ };
|
|
+ opp-800000000 {
|
|
+ opp-hz = /bits/ 64 <800000000>;
|
|
+ opp-microvolt = <950000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pvtm@fde80000 {
|
|
+ compatible = "rockchip,rk3568-gpu-pvtm";
|
|
+ reg = <0x0 0xfde80000 0x0 0x100>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ pvtm@1 {
|
|
+ reg = <1>;
|
|
+ clocks = <&cru CLK_GPU_PVTM>, <&cru PCLK_GPU_PVTM>;
|
|
+ clock-names = "clk", "pclk";
|
|
+ resets = <&cru SRST_GPU_PVTM>, <&cru SRST_P_GPU_PVTM>;
|
|
+ reset-names = "rts", "rst-p";
|
|
+ thermal-zone = "gpu-thermal";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pvtm@fde90000 {
|
|
+ compatible = "rockchip,rk3568-npu-pvtm";
|
|
+ reg = <0x0 0xfde90000 0x0 0x100>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ pvtm@2 {
|
|
+ reg = <2>;
|
|
+ clocks = <&cru CLK_NPU_PVTM>, <&cru PCLK_NPU_PVTM>,
|
|
+ <&cru HCLK_NPU_PRE>;
|
|
+ clock-names = "clk", "pclk", "hclk";
|
|
+ resets = <&cru SRST_NPU_PVTM>, <&cru SRST_P_NPU_PVTM>;
|
|
+ reset-names = "rts", "rst-p";
|
|
+ thermal-zone = "soc-thermal";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vdpu: vdpu@fdea0400 {
|
|
+ compatible = "rockchip,vpu-decoder-v2";
|
|
+ reg = <0x0 0xfdea0400 0x0 0x400>;
|
|
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "irq_dec";
|
|
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
|
|
+ clock-names = "aclk_vcodec", "hclk_vcodec";
|
|
+ resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>;
|
|
+ reset-names = "video_a", "video_h";
|
|
+ iommus = <&vdpu_mmu>;
|
|
+ power-domains = <&power RK3568_PD_VPU>;
|
|
+ rockchip,srv = <&mpp_srv>;
|
|
+ rockchip,taskqueue-node = <0>;
|
|
+ rockchip,resetgroup-node = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ vdpu_mmu: iommu@fdea0800 {
|
|
+ compatible = "rockchip,iommu-v2";
|
|
+ reg = <0x0 0xfdea0800 0x0 0x40>;
|
|
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "vdpu_mmu";
|
|
+ clock-names = "aclk", "iface";
|
|
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
|
|
+ power-domains = <&power RK3568_PD_VPU>;
|
|
+ #iommu-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ rk_rga: rk_rga@fdeb0000 {
|
|
+ compatible = "rockchip,rga2";
|
|
+ reg = <0x0 0xfdeb0000 0x0 0x1000>;
|
|
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>;
|
|
+ clock-names = "aclk_rga", "hclk_rga", "clk_rga";
|
|
+ power-domains = <&power RK3568_PD_RGA>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ ebc: ebc@fdec0000 {
|
|
+ compatible = "rockchip,rk3568-ebc-tcon";
|
|
+ reg = <0x0 0xfdec0000 0x0 0x5000>;
|
|
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru HCLK_EBC>, <&cru DCLK_EBC>;
|
|
+ clock-names = "hclk", "dclk";
|
|
+ power-domains = <&power RK3568_PD_RGA>;
|
|
+ rockchip,grf = <&grf>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&ebc_pins>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ jpegd: jpegd@fded0000 {
|
|
+ compatible = "rockchip,rkv-jpeg-decoder-v1";
|
|
+ reg = <0x0 0xfded0000 0x0 0x400>;
|
|
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>;
|
|
+ clock-names = "aclk_vcodec", "hclk_vcodec";
|
|
+ rockchip,disable-auto-freq;
|
|
+ resets = <&cru SRST_A_JDEC>, <&cru SRST_H_JDEC>;
|
|
+ reset-names = "video_a", "video_h";
|
|
+ iommus = <&jpegd_mmu>;
|
|
+ rockchip,srv = <&mpp_srv>;
|
|
+ rockchip,taskqueue-node = <1>;
|
|
+ rockchip,resetgroup-node = <1>;
|
|
+ power-domains = <&power RK3568_PD_RGA>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ jpegd_mmu: iommu@fded0480 {
|
|
+ compatible = "rockchip,iommu-v2";
|
|
+ reg = <0x0 0xfded0480 0x0 0x40>;
|
|
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "jpegd_mmu";
|
|
+ clock-names = "aclk", "iface";
|
|
+ clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>;
|
|
+ power-domains = <&power RK3568_PD_RGA>;
|
|
+ #iommu-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ vepu: vepu@fdee0000 {
|
|
+ compatible = "rockchip,vpu-encoder-v2";
|
|
+ reg = <0x0 0xfdee0000 0x0 0x400>;
|
|
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
|
|
+ clock-names = "aclk_vcodec", "hclk_vcodec";
|
|
+ rockchip,disable-auto-freq;
|
|
+ resets = <&cru SRST_A_JENC>, <&cru SRST_H_JENC>;
|
|
+ reset-names = "video_a", "video_h";
|
|
+ iommus = <&vepu_mmu>;
|
|
+ rockchip,srv = <&mpp_srv>;
|
|
+ rockchip,taskqueue-node = <2>;
|
|
+ rockchip,resetgroup-node = <2>;
|
|
+ power-domains = <&power RK3568_PD_RGA>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ vepu_mmu: iommu@fdee0800 {
|
|
+ compatible = "rockchip,iommu-v2";
|
|
+ reg = <0x0 0xfdee0800 0x0 0x40>;
|
|
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "vepu_mmu";
|
|
+ clock-names = "aclk", "iface";
|
|
+ clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
|
|
+ power-domains = <&power RK3568_PD_RGA>;
|
|
+ #iommu-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ iep: iep@fdef0000 {
|
|
+ compatible = "rockchip,iep-v2";
|
|
+ reg = <0x0 0xfdef0000 0x0 0x500>;
|
|
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>, <&cru CLK_IEP_CORE>;
|
|
+ clock-names = "aclk", "hclk", "sclk";
|
|
+ resets = <&cru SRST_A_IEP>, <&cru SRST_H_IEP>,
|
|
+ <&cru SRST_IEP_CORE>;
|
|
+ reset-names = "rst_a", "rst_h", "rst_s";
|
|
+ power-domains = <&power RK3568_PD_RGA>;
|
|
+ rockchip,srv = <&mpp_srv>;
|
|
+ rockchip,taskqueue-node = <5>;
|
|
+ rockchip,resetgroup-node = <5>;
|
|
+ iommus = <&iep_mmu>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ iep_mmu: iommu@fdef0800 {
|
|
+ compatible = "rockchip,iommu-v2";
|
|
+ reg = <0x0 0xfdef0800 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "iep_mmu";
|
|
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
|
|
+ clock-names = "aclk", "iface";
|
|
+ #iommu-cells = <0>;
|
|
+ power-domains = <&power RK3568_PD_RGA>;
|
|
+ //rockchip,disable-device-link-resume;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ eink: eink@fdf00000 {
|
|
+ compatible = "rockchip,rk3568-eink-tcon";
|
|
+ reg = <0x0 0xfdf00000 0x0 0x74>;
|
|
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru PCLK_EINK>, <&cru HCLK_EINK>;
|
|
+ clock-names = "pclk", "hclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ rkvenc: rkvenc@fdf40000 {
|
|
+ compatible = "rockchip,rkv-encoder-v1";
|
|
+ reg = <0x0 0xfdf40000 0x0 0x400>;
|
|
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "irq_enc";
|
|
+ clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>,
|
|
+ <&cru CLK_RKVENC_CORE>;
|
|
+ clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
|
|
+ rockchip,normal-rates = <297000000>, <0>, <297000000>;
|
|
+ resets = <&cru SRST_A_RKVENC>, <&cru SRST_H_RKVENC>,
|
|
+ <&cru SRST_RKVENC_CORE>;
|
|
+ reset-names = "video_a", "video_h", "video_core";
|
|
+ assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_RKVENC_CORE>;
|
|
+ assigned-clock-rates = <297000000>, <297000000>;
|
|
+ iommus = <&rkvenc_mmu>;
|
|
+ node-name = "rkvenc";
|
|
+ rockchip,srv = <&mpp_srv>;
|
|
+ rockchip,taskqueue-node = <3>;
|
|
+ rockchip,resetgroup-node = <3>;
|
|
+ power-domains = <&power RK3568_PD_RKVENC>;
|
|
+ operating-points-v2 = <&rkvenc_opp_table>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ rkvenc_opp_table: rkvenc-opp-table {
|
|
+ compatible = "operating-points-v2";
|
|
+
|
|
+ nvmem-cells = <&core_pvtm>;
|
|
+ nvmem-cell-names = "pvtm";
|
|
+ rockchip,pvtm-voltage-sel = <
|
|
+ 0 82000 0
|
|
+ 82001 93000 1
|
|
+ 93001 100000 2
|
|
+ >;
|
|
+ rockchip,pvtm-ch = <0 5>;
|
|
+
|
|
+ opp-297000000 {
|
|
+ opp-hz = /bits/ 64 <297000000>;
|
|
+ opp-microvolt = <0>;
|
|
+ };
|
|
+ opp-400000000 {
|
|
+ opp-hz = /bits/ 64 <400000000>;
|
|
+ opp-microvolt = <950000>;
|
|
+ opp-microvolt-L0 = <950000>;
|
|
+ opp-microvolt-L1 = <925000>;
|
|
+ opp-microvolt-L2 = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ rkvenc_mmu: iommu@fdf40f00 {
|
|
+ compatible = "rockchip,iommu-v2";
|
|
+ reg = <0x0 0xfdf40f00 0x0 0x40>, <0x0 0xfdf40f40 0x0 0x40>;
|
|
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "rkvenc_mmu0", "rkvenc_mmu1";
|
|
+ clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>;
|
|
+ clock-names = "aclk", "iface";
|
|
+ rockchip,disable-mmu-reset;
|
|
+ rockchip,enable-cmd-retry;
|
|
+ #iommu-cells = <0>;
|
|
+ power-domains = <&power RK3568_PD_RKVENC>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ rkvdec: rkvdec@fdf80200 {
|
|
+ compatible = "rockchip,rkv-decoder-rk3568", "rockchip,rkv-decoder-v2";
|
|
+ reg = <0x0 0xfdf80200 0x0 0x400>, <0x0 0xfdf80100 0x0 0x100>;
|
|
+ reg-names = "regs", "link";
|
|
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "irq_dec";
|
|
+ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
|
|
+ <&cru CLK_RKVDEC_CA>, <&cru CLK_RKVDEC_CORE>,
|
|
+ <&cru CLK_RKVDEC_HEVC_CA>;
|
|
+ clock-names = "aclk_vcodec", "hclk_vcodec","clk_cabac",
|
|
+ "clk_core", "clk_hevc_cabac";
|
|
+ rockchip,normal-rates = <297000000>, <0>, <297000000>,
|
|
+ <297000000>, <600000000>;
|
|
+ rockchip,advanced-rates = <396000000>, <0>, <396000000>,
|
|
+ <396000000>, <600000000>;
|
|
+ rockchip,default-max-load = <2088960>;
|
|
+ resets = <&cru SRST_A_RKVDEC>, <&cru SRST_H_RKVDEC>,
|
|
+ <&cru SRST_RKVDEC_CA>, <&cru SRST_RKVDEC_CORE>,
|
|
+ <&cru SRST_RKVDEC_HEVC_CA>;
|
|
+ assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_RKVDEC_CA>,
|
|
+ <&cru CLK_RKVDEC_CORE>, <&cru CLK_RKVDEC_HEVC_CA>;
|
|
+ assigned-clock-rates = <297000000>, <297000000>, <297000000>, <297000000>;
|
|
+ reset-names = "video_a", "video_h", "video_cabac",
|
|
+ "video_core", "video_hevc_cabac";
|
|
+ power-domains = <&power RK3568_PD_RKVDEC>;
|
|
+ iommus = <&rkvdec_mmu>;
|
|
+ rockchip,srv = <&mpp_srv>;
|
|
+ rockchip,taskqueue-node = <4>;
|
|
+ rockchip,resetgroup-node = <4>;
|
|
+ rockchip,sram = <&rkvdec_sram>;
|
|
+ /* rcb_iova: start and size */
|
|
+ rockchip,rcb-iova = <0x10000000 65536>;
|
|
+ rockchip,rcb-min-width = <512>;
|
|
+ rockchip,task-capacity = <16>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ rkvdec_mmu: iommu@fdf80800 {
|
|
+ compatible = "rockchip,iommu-v2";
|
|
+ reg = <0x0 0xfdf80800 0x0 0x40>, <0x0 0xfdf80840 0x0 0x40>;
|
|
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "rkvdec_mmu";
|
|
+ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
|
|
+ clock-names = "aclk", "iface";
|
|
+ power-domains = <&power RK3568_PD_RKVDEC>;
|
|
+ #iommu-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ mipi_csi2: mipi-csi2@fdfb0000 {
|
|
+ compatible = "rockchip,rk3568-mipi-csi2";
|
|
+ reg = <0x0 0xfdfb0000 0x0 0x10000>;
|
|
+ reg-names = "csihost_regs";
|
|
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "csi-intr1", "csi-intr2";
|
|
+ clocks = <&cru PCLK_CSI2HOST1>;
|
|
+ clock-names = "pclk_csi2host";
|
|
+ resets = <&cru SRST_P_CSI2HOST1>;
|
|
+ reset-names = "srst_csihost_p";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ rkcif: rkcif@fdfe0000 {
|
|
+ compatible = "rockchip,rk3568-cif";
|
|
+ reg = <0x0 0xfdfe0000 0x0 0x8000>;
|
|
+ reg-names = "cif_regs";
|
|
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "cif-intr";
|
|
+
|
|
+ clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>,
|
|
+ <&cru DCLK_VICAP>, <&cru ICLK_VICAP_G>;
|
|
+ clock-names = "aclk_cif", "hclk_cif",
|
|
+ "dclk_cif", "iclk_cif_g";
|
|
+ resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>,
|
|
+ <&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>,
|
|
+ <&cru SRST_I_VICAP>;
|
|
+ reset-names = "rst_cif_a", "rst_cif_h",
|
|
+ "rst_cif_d", "rst_cif_p",
|
|
+ "rst_cif_i";
|
|
+ assigned-clocks = <&cru DCLK_VICAP>;
|
|
+ assigned-clock-rates = <300000000>;
|
|
+ power-domains = <&power RK3568_PD_VI>;
|
|
+ rockchip,grf = <&grf>;
|
|
+ iommus = <&rkcif_mmu>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ rkcif_mmu: iommu@fdfe0800 {
|
|
+ compatible = "rockchip,iommu-v2";
|
|
+ reg = <0x0 0xfdfe0800 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "cif_mmu";
|
|
+ clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>;
|
|
+ clock-names = "aclk", "iface";
|
|
+ power-domains = <&power RK3568_PD_VI>;
|
|
+ rockchip,disable-mmu-reset;
|
|
+ #iommu-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ rkcif_dvp: rkcif_dvp {
|
|
+ compatible = "rockchip,rkcif-dvp";
|
|
+ rockchip,hw = <&rkcif>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ rkcif_dvp_sditf: rkcif_dvp_sditf {
|
|
+ compatible = "rockchip,rkcif-sditf";
|
|
+ rockchip,cif = <&rkcif_dvp>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ rkcif_mipi_lvds: rkcif_mipi_lvds {
|
|
+ compatible = "rockchip,rkcif-mipi-lvds";
|
|
+ rockchip,hw = <&rkcif>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ rkcif_mipi_lvds_sditf: rkcif_mipi_lvds_sditf {
|
|
+ compatible = "rockchip,rkcif-sditf";
|
|
+ rockchip,cif = <&rkcif_mipi_lvds>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ rkisp: rkisp@fdff0000 {
|
|
+ compatible = "rockchip,rk3568-rkisp";
|
|
+ reg = <0x0 0xfdff0000 0x0 0x10000>;
|
|
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "mipi_irq", "mi_irq", "isp_irq";
|
|
+ clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru CLK_ISP>;
|
|
+ clock-names = "aclk_isp", "hclk_isp", "clk_isp";
|
|
+ resets = <&cru SRST_ISP>, <&cru SRST_H_ISP>;
|
|
+ reset-names = "isp", "isp-h";
|
|
+ rockchip,grf = <&grf>;
|
|
+ power-domains = <&power RK3568_PD_VI>;
|
|
+ iommus = <&rkisp_mmu>;
|
|
+ rockchip,iq-feature = /bits/ 64 <0x3FBFFFE67FF>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ rkisp_mmu: iommu@fdff1a00 {
|
|
+ compatible = "rockchip,iommu-v2";
|
|
+ reg = <0x0 0xfdff1a00 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "isp_mmu";
|
|
+ clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
|
|
+ clock-names = "aclk", "iface";
|
|
+ power-domains = <&power RK3568_PD_VI>;
|
|
+ #iommu-cells = <0>;
|
|
+ rockchip,disable-mmu-reset;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ rkisp_vir0: rkisp-vir0 {
|
|
+ compatible = "rockchip,rkisp-vir";
|
|
+ rockchip,hw = <&rkisp>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ rkisp_vir1: rkisp-vir1 {
|
|
+ compatible = "rockchip,rkisp-vir";
|
|
+ rockchip,hw = <&rkisp>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gmac1: ethernet@fe010000 {
|
|
+ compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
|
|
+ reg = <0x0 0xfe010000 0x0 0x10000>;
|
|
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "macirq", "eth_wake_irq";
|
|
+ rockchip,grf = <&grf>;
|
|
+ clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
|
|
+ <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
|
|
+ <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
|
|
+ <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>,
|
|
+ <&cru PCLK_XPCS>;
|
|
+ clock-names = "stmmaceth", "mac_clk_rx",
|
|
+ "mac_clk_tx", "clk_mac_refout",
|
|
+ "aclk_mac", "pclk_mac",
|
|
+ "clk_mac_speed", "ptp_ref",
|
|
+ "pclk_xpcs";
|
|
+ resets = <&cru SRST_A_GMAC1>;
|
|
+ reset-names = "stmmaceth";
|
|
+
|
|
+ snps,mixed-burst;
|
|
+ snps,tso;
|
|
+
|
|
+ snps,axi-config = <&gmac1_stmmac_axi_setup>;
|
|
+ snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
|
|
+ snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
|
|
+ status = "disabled";
|
|
+
|
|
+ mdio1: mdio {
|
|
+ compatible = "snps,dwmac-mdio";
|
|
+ #address-cells = <0x1>;
|
|
+ #size-cells = <0x0>;
|
|
+ };
|
|
+
|
|
+ gmac1_stmmac_axi_setup: stmmac-axi-config {
|
|
+ snps,wr_osr_lmt = <4>;
|
|
+ snps,rd_osr_lmt = <8>;
|
|
+ snps,blen = <0 0 0 0 16 8 4>;
|
|
+ };
|
|
+
|
|
+ gmac1_mtl_rx_setup: rx-queues-config {
|
|
+ snps,rx-queues-to-use = <1>;
|
|
+ queue0 {};
|
|
+ };
|
|
+
|
|
+ gmac1_mtl_tx_setup: tx-queues-config {
|
|
+ snps,tx-queues-to-use = <1>;
|
|
+ queue0 {};
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vop: vop@fe040000 {
|
|
+ compatible = "rockchip,rk3568-vop";
|
|
+ reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
|
|
+ reg-names = "regs", "gamma_lut";
|
|
+ rockchip,grf = <&grf>;
|
|
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
|
|
+ clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2";
|
|
+ iommus = <&vop_mmu>;
|
|
+ power-domains = <&power RK3568_PD_VO>;
|
|
+ status = "disabled";
|
|
+
|
|
+ vop_out: ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ vp0: port@0 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ reg = <0>;
|
|
+
|
|
+ vp0_out_dsi0: endpoint@0 {
|
|
+ reg = <0>;
|
|
+ remote-endpoint = <&dsi0_in_vp0>;
|
|
+ };
|
|
+
|
|
+ vp0_out_dsi1: endpoint@1 {
|
|
+ reg = <1>;
|
|
+ remote-endpoint = <&dsi1_in_vp0>;
|
|
+ };
|
|
+
|
|
+ vp0_out_edp: endpoint@2 {
|
|
+ reg = <2>;
|
|
+ remote-endpoint = <&edp_in_vp0>;
|
|
+ };
|
|
+
|
|
+ vp0_out_hdmi: endpoint@3 {
|
|
+ reg = <3>;
|
|
+ remote-endpoint = <&hdmi_in_vp0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vp1: port@1 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ reg = <1>;
|
|
+
|
|
+ vp1_out_dsi0: endpoint@0 {
|
|
+ reg = <0>;
|
|
+ remote-endpoint = <&dsi0_in_vp1>;
|
|
+ };
|
|
+
|
|
+ vp1_out_dsi1: endpoint@1 {
|
|
+ reg = <1>;
|
|
+ remote-endpoint = <&dsi1_in_vp1>;
|
|
+ };
|
|
+
|
|
+ vp1_out_edp: endpoint@2 {
|
|
+ reg = <2>;
|
|
+ remote-endpoint = <&edp_in_vp1>;
|
|
+ };
|
|
+
|
|
+ vp1_out_hdmi: endpoint@3 {
|
|
+ reg = <3>;
|
|
+ remote-endpoint = <&hdmi_in_vp1>;
|
|
+ };
|
|
+
|
|
+ vp1_out_lvds: endpoint@4 {
|
|
+ reg = <4>;
|
|
+ remote-endpoint = <&lvds_in_vp1>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vp2: port@2 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ reg = <2>;
|
|
+
|
|
+ vp2_out_lvds: endpoint@0 {
|
|
+ reg = <0>;
|
|
+ remote-endpoint = <&lvds_in_vp2>;
|
|
+ };
|
|
+
|
|
+ vp2_out_rgb: endpoint@1 {
|
|
+ reg = <1>;
|
|
+ remote-endpoint = <&rgb_in_vp2>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vop_mmu: iommu@fe043e00 {
|
|
+ compatible = "rockchip,iommu-v2";
|
|
+ reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "vop_mmu";
|
|
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
|
|
+ clock-names = "aclk", "iface";
|
|
+ #iommu-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ dsi0: dsi@fe060000 {
|
|
+ compatible = "rockchip,rk3568-mipi-dsi";
|
|
+ reg = <0x0 0xfe060000 0x0 0x10000>;
|
|
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>, <&video_phy0>;
|
|
+ clock-names = "pclk", "hclk", "hs_clk";
|
|
+ resets = <&cru SRST_P_DSITX_0>;
|
|
+ reset-names = "apb";
|
|
+ phys = <&video_phy0>;
|
|
+ phy-names = "mipi_dphy";
|
|
+ power-domains = <&power RK3568_PD_VO>;
|
|
+ rockchip,grf = <&grf>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ dsi0_in: port@0 {
|
|
+ reg = <0>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ dsi0_in_vp0: endpoint@0 {
|
|
+ reg = <0>;
|
|
+ remote-endpoint = <&vp0_out_dsi0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ dsi0_in_vp1: endpoint@1 {
|
|
+ reg = <1>;
|
|
+ remote-endpoint = <&vp1_out_dsi0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dsi1: dsi@fe070000 {
|
|
+ compatible = "rockchip,rk3568-mipi-dsi";
|
|
+ reg = <0x0 0xfe070000 0x0 0x10000>;
|
|
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>, <&video_phy1>;
|
|
+ clock-names = "pclk", "hclk", "hs_clk";
|
|
+ resets = <&cru SRST_P_DSITX_1>;
|
|
+ reset-names = "apb";
|
|
+ phys = <&video_phy1>;
|
|
+ phy-names = "mipi_dphy";
|
|
+ power-domains = <&power RK3568_PD_VO>;
|
|
+ rockchip,grf = <&grf>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ dsi1_in: port@0 {
|
|
+ reg = <0>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ dsi1_in_vp0: endpoint@0 {
|
|
+ reg = <0>;
|
|
+ remote-endpoint = <&vp0_out_dsi1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ dsi1_in_vp1: endpoint@1 {
|
|
+ reg = <1>;
|
|
+ remote-endpoint = <&vp1_out_dsi1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ hdmi: hdmi@fe0a0000 {
|
|
+ compatible = "rockchip,rk3568-dw-hdmi";
|
|
+ reg = <0x0 0xfe0a0000 0x0 0x20000>;
|
|
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru PCLK_HDMI_HOST>,
|
|
+ <&cru CLK_HDMI_SFR>,
|
|
+ <&cru CLK_HDMI_CEC>,
|
|
+ <&pmucru PLL_HPLL>,
|
|
+ <&cru HCLK_VOP>;
|
|
+ clock-names = "iahb", "isfr", "cec", "ref", "hclk";
|
|
+ power-domains = <&power RK3568_PD_VO>;
|
|
+ reg-io-width = <4>;
|
|
+ rockchip,grf = <&grf>;
|
|
+ #sound-dai-cells = <0>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
|
|
+ status = "disabled";
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ hdmi_in: port {
|
|
+ reg = <0>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ hdmi_in_vp0: endpoint@0 {
|
|
+ reg = <0>;
|
|
+ remote-endpoint = <&vp0_out_hdmi>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ hdmi_in_vp1: endpoint@1 {
|
|
+ reg = <1>;
|
|
+ remote-endpoint = <&vp1_out_hdmi>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ edp: edp@fe0c0000 {
|
|
+ compatible = "rockchip,rk3568-edp";
|
|
+ reg = <0x0 0xfe0c0000 0x0 0x10000>;
|
|
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&pmucru XIN_OSC0_EDPPHY_G>, <&cru PCLK_EDP_CTRL>,
|
|
+ <&cru CLK_EDP_200M>, <&cru HCLK_VO>;
|
|
+ clock-names = "dp", "pclk", "spdif", "hclk";
|
|
+ resets = <&cru SRST_EDP_24M>, <&cru SRST_P_EDP_CTRL>;
|
|
+ reset-names = "dp", "apb";
|
|
+ phys = <&edp_phy>;
|
|
+ phy-names = "dp";
|
|
+ power-domains = <&power RK3568_PD_VO>;
|
|
+ status = "disabled";
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ edp_in: port@0 {
|
|
+ reg = <0>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ edp_in_vp0: endpoint@0 {
|
|
+ reg = <0>;
|
|
+ remote-endpoint = <&vp0_out_edp>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ edp_in_vp1: endpoint@1 {
|
|
+ reg = <1>;
|
|
+ remote-endpoint = <&vp1_out_edp>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ nocp_cpu: nocp-cpu@fe102000 {
|
|
+ compatible = "rockchip,rk3568-nocp";
|
|
+ reg = <0x0 0xfe102000 0x0 0x100>;
|
|
+ };
|
|
+
|
|
+ nocp_gpu_vpu_rga_venc: nocp-gpu-vpu-rga-venc@fe102400 {
|
|
+ compatible = "rockchip,rk3568-nocp";
|
|
+ reg = <0x0 0xfe102400 0x0 0x100>;
|
|
+ };
|
|
+
|
|
+ nocp_npu_vdec: nocp-vdec@fe102800 {
|
|
+ compatible = "rockchip,rk3568-nocp";
|
|
+ reg = <0x0 0xfe102800 0x0 0x100>;
|
|
+ };
|
|
+
|
|
+ nocp_vi_usb_peri_pipe: nocp-vi-usb-peri-pipe@fe102c00 {
|
|
+ compatible = "rockchip,rk3568-nocp";
|
|
+ reg = <0x0 0xfe102c00 0x0 0x100>;
|
|
+ };
|
|
+
|
|
+ nocp_vo: nocp-vo@fe103000 {
|
|
+ compatible = "rockchip,rk3568-nocp";
|
|
+ reg = <0x0 0xfe103000 0x0 0x100>;
|
|
+ };
|
|
+
|
|
+ qos_gpu: qos@fe128000 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x0 0xfe128000 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_rkvenc_rd_m0: qos@fe138080 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x0 0xfe138080 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_rkvenc_rd_m1: qos@fe138100 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x0 0xfe138100 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_rkvenc_wr_m0: qos@fe138180 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x0 0xfe138180 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_isp: qos@fe148000 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x0 0xfe148000 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_vicap0: qos@fe148080 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x0 0xfe148080 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_vicap1: qos@fe148100 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x0 0xfe148100 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_vpu: qos@fe150000 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x0 0xfe150000 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_ebc: qos@fe158000 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x0 0xfe158000 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_iep: qos@fe158100 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x0 0xfe158100 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_jpeg_dec: qos@fe158180 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x0 0xfe158180 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_jpeg_enc: qos@fe158200 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x0 0xfe158200 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_rga_rd: qos@fe158280 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x0 0xfe158280 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_rga_wr: qos@fe158300 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x0 0xfe158300 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_npu: qos@fe180000 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x0 0xfe180000 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_pcie2x1: qos@fe190000 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x0 0xfe190000 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_pcie3x1: qos@fe190080 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x0 0xfe190080 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_pcie3x2: qos@fe190100 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x0 0xfe190100 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_sata0: qos@fe190200 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x0 0xfe190200 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_sata1: qos@fe190280 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x0 0xfe190280 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_sata2: qos@fe190300 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x0 0xfe190300 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_usb3_0: qos@fe190380 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x0 0xfe190380 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_usb3_1: qos@fe190400 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x0 0xfe190400 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_rkvdec: qos@fe198000 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x0 0xfe198000 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_hdcp: qos@fe1a8000 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x0 0xfe1a8000 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_vop_m0: qos@fe1a8080 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x0 0xfe1a8080 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_vop_m1: qos@fe1a8100 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x0 0xfe1a8100 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ sdmmc2: dwmmc@fe000000 {
|
|
+ compatible = "rockchip,rk3568-dw-mshc",
|
|
+ "rockchip,rk3288-dw-mshc";
|
|
+ reg = <0x0 0xfe000000 0x0 0x4000>;
|
|
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ max-frequency = <150000000>;
|
|
+ clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
|
|
+ <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
|
|
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
+ fifo-depth = <0x100>;
|
|
+ resets = <&cru SRST_SDMMC2>;
|
|
+ reset-names = "reset";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ dfi: dfi@fe230000 {
|
|
+ reg = <0x00 0xfe230000 0x00 0x400>;
|
|
+ compatible = "rockchip,rk3568-dfi";
|
|
+ rockchip,pmugrf = <&pmugrf>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ dmc: dmc {
|
|
+ compatible = "rockchip,rk3568-dmc";
|
|
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "complete";
|
|
+ devfreq-events = <&dfi>;
|
|
+ clocks = <&cru SCLK_DDRCLK>;
|
|
+ clock-names = "dmc_clk";
|
|
+ operating-points-v2 = <&dmc_opp_table>;
|
|
+ ddr_timing = <&ddr_timing>;
|
|
+ vop-bw-dmc-freq = <
|
|
+ /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */
|
|
+ 0 505 324000
|
|
+ 506 99999 528000
|
|
+ >;
|
|
+ upthreshold = <40>;
|
|
+ downdifferential = <20>;
|
|
+ system-status-freq = <
|
|
+ /*system status freq(KHz)*/
|
|
+ SYS_STATUS_NORMAL 780000
|
|
+ SYS_STATUS_REBOOT 1560000
|
|
+ SYS_STATUS_SUSPEND 324000
|
|
+ SYS_STATUS_VIDEO_4K 780000
|
|
+ SYS_STATUS_VIDEO_4K_10B 780000
|
|
+ SYS_STATUS_BOOST 1560000
|
|
+ SYS_STATUS_ISP 1560000
|
|
+ SYS_STATUS_PERFORMANCE 1560000
|
|
+ SYS_STATUS_DUALVIEW 1560000
|
|
+ >;
|
|
+ auto-min-freq = <324000>;
|
|
+ auto-freq-en = <1>;
|
|
+ #cooling-cells = <2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ dmc_opp_table: dmc-opp-table {
|
|
+ compatible = "operating-points-v2";
|
|
+
|
|
+ mbist-vmin = <825000 900000 950000>;
|
|
+ nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>;
|
|
+ nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
|
|
+ rockchip,temp-hysteresis = <5000>;
|
|
+ rockchip,low-temp = <0>;
|
|
+ rockchip,low-temp-adjust-volt = <
|
|
+ /* MHz MHz uV */
|
|
+ 0 1560 75000
|
|
+ >;
|
|
+ rockchip,leakage-voltage-sel = <
|
|
+ 1 80 0
|
|
+ 81 254 1
|
|
+ >;
|
|
+ rockchip,pvtm-voltage-sel = <
|
|
+ 0 82000 0
|
|
+ 82001 100000 1
|
|
+ >;
|
|
+ rockchip,pvtm-ch = <0 5>;
|
|
+
|
|
+ opp-1560000000 {
|
|
+ opp-hz = /bits/ 64 <1560000000>;
|
|
+ opp-microvolt = <900000>;
|
|
+ opp-microvolt-L0 = <900000>;
|
|
+ opp-microvolt-L1 = <850000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dmcdbg: dmcdbg {
|
|
+ compatible = "rockchip,rk3568-dmcdbg";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pcie2x1: pcie@fe260000 {
|
|
+ compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ bus-range = <0x0 0xf>;
|
|
+ clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
|
|
+ <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
|
|
+ <&cru CLK_PCIE20_AUX_NDFT>;
|
|
+ clock-names = "aclk_mst", "aclk_slv",
|
|
+ "aclk_dbi", "pclk", "aux";
|
|
+ device_type = "pci";
|
|
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 7>;
|
|
+ interrupt-map = <0 0 0 1 &pcie2x1_intc 0>,
|
|
+ <0 0 0 2 &pcie2x1_intc 1>,
|
|
+ <0 0 0 3 &pcie2x1_intc 2>,
|
|
+ <0 0 0 4 &pcie2x1_intc 3>;
|
|
+ linux,pci-domain = <0>;
|
|
+ num-ib-windows = <6>;
|
|
+ num-ob-windows = <2>;
|
|
+ max-link-speed = <2>;
|
|
+ msi-map = <0x0 &its 0x0 0x1000>;
|
|
+ num-lanes = <1>;
|
|
+ phys = <&combphy2_psq PHY_TYPE_PCIE>;
|
|
+ phy-names = "pcie-phy";
|
|
+ power-domains = <&power RK3568_PD_PIPE>;
|
|
+ ranges = <0x00000800 0x0 0x00000000 0x3 0x00000000 0x0 0x800000
|
|
+ 0x81000000 0x0 0x00800000 0x3 0x00800000 0x0 0x100000
|
|
+ 0x83000000 0x0 0x00900000 0x3 0x00900000 0x0 0x3f700000>;
|
|
+ reg = <0x3 0xc0000000 0x0 0x400000>,
|
|
+ <0x0 0xfe260000 0x0 0x10000>;
|
|
+ reg-names = "pcie-dbi", "pcie-apb";
|
|
+ resets = <&cru SRST_PCIE20_POWERUP>;
|
|
+ reset-names = "pipe";
|
|
+ status = "disabled";
|
|
+
|
|
+ pcie2x1_intc: legacy-interrupt-controller {
|
|
+ interrupt-controller;
|
|
+ #address-cells = <0>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-parent = <&gic>;
|
|
+ interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pcie3x1: pcie@fe270000 {
|
|
+ compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ bus-range = <0x10 0x1f>;
|
|
+ clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
|
|
+ <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
|
|
+ <&cru CLK_PCIE30X1_AUX_NDFT>;
|
|
+ clock-names = "aclk_mst", "aclk_slv",
|
|
+ "aclk_dbi", "pclk", "aux";
|
|
+ device_type = "pci";
|
|
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 7>;
|
|
+ interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
|
|
+ <0 0 0 2 &pcie3x1_intc 1>,
|
|
+ <0 0 0 3 &pcie3x1_intc 2>,
|
|
+ <0 0 0 4 &pcie3x1_intc 3>;
|
|
+ linux,pci-domain = <1>;
|
|
+ num-ib-windows = <6>;
|
|
+ num-ob-windows = <2>;
|
|
+ max-link-speed = <3>;
|
|
+ msi-map = <0x1000 &its 0x1000 0x1000>;
|
|
+ num-lanes = <1>;
|
|
+ phys = <&pcie30phy>;
|
|
+ phy-names = "pcie-phy";
|
|
+ power-domains = <&power RK3568_PD_PIPE>;
|
|
+ ranges = <0x00000800 0x0 0x40000000 0x3 0x40000000 0x0 0x800000
|
|
+ 0x81000000 0x0 0x40800000 0x3 0x40800000 0x0 0x100000
|
|
+ 0x83000000 0x0 0x40900000 0x3 0x40900000 0x0 0x3f700000>;
|
|
+ reg = <0x3 0xc0400000 0x0 0x400000>,
|
|
+ <0x0 0xfe270000 0x0 0x10000>;
|
|
+ reg-names = "pcie-dbi", "pcie-apb";
|
|
+ resets = <&cru SRST_PCIE30X1_POWERUP>;
|
|
+ reset-names = "pipe";
|
|
+ /* rockchip,bifurcation; lane1 when using 1+1 */
|
|
+ status = "disabled";
|
|
+
|
|
+ pcie3x1_intc: legacy-interrupt-controller {
|
|
+ interrupt-controller;
|
|
+ #address-cells = <0>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-parent = <&gic>;
|
|
+ interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pcie3x2: pcie@fe280000 {
|
|
+ compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ bus-range = <0x20 0x2f>;
|
|
+ clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
|
|
+ <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
|
|
+ <&cru CLK_PCIE30X2_AUX_NDFT>;
|
|
+ clock-names = "aclk_mst", "aclk_slv",
|
|
+ "aclk_dbi", "pclk", "aux";
|
|
+ device_type = "pci";
|
|
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 7>;
|
|
+ interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
|
|
+ <0 0 0 2 &pcie3x2_intc 1>,
|
|
+ <0 0 0 3 &pcie3x2_intc 2>,
|
|
+ <0 0 0 4 &pcie3x2_intc 3>;
|
|
+ linux,pci-domain = <2>;
|
|
+ num-ib-windows = <6>;
|
|
+ num-ob-windows = <2>;
|
|
+ max-link-speed = <3>;
|
|
+ msi-map = <0x2000 &its 0x2000 0x1000>;
|
|
+ num-lanes = <2>;
|
|
+ phys = <&pcie30phy>;
|
|
+ phy-names = "pcie-phy";
|
|
+ power-domains = <&power RK3568_PD_PIPE>;
|
|
+ ranges = <0x00000800 0x0 0x80000000 0x3 0x80000000 0x0 0x800000
|
|
+ 0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000
|
|
+ 0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
|
|
+ reg = <0x3 0xc0800000 0x0 0x400000>,
|
|
+ <0x0 0xfe280000 0x0 0x10000>;
|
|
+ reg-names = "pcie-dbi", "pcie-apb";
|
|
+ resets = <&cru SRST_PCIE30X2_POWERUP>;
|
|
+ reset-names = "pipe";
|
|
+ /* rockchip,bifurcation; lane0 when using 1+1 */
|
|
+ status = "disabled";
|
|
+
|
|
+ pcie3x2_intc: legacy-interrupt-controller {
|
|
+ interrupt-controller;
|
|
+ #address-cells = <0>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-parent = <&gic>;
|
|
+ interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ gmac0: ethernet@fe2a0000 {
|
|
+ compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
|
|
+ reg = <0x0 0xfe2a0000 0x0 0x10000>;
|
|
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "macirq", "eth_wake_irq";
|
|
+ rockchip,grf = <&grf>;
|
|
+ clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
|
|
+ <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
|
|
+ <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
|
|
+ <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
|
|
+ <&cru PCLK_XPCS>;
|
|
+ clock-names = "stmmaceth", "mac_clk_rx",
|
|
+ "mac_clk_tx", "clk_mac_refout",
|
|
+ "aclk_mac", "pclk_mac",
|
|
+ "clk_mac_speed", "ptp_ref",
|
|
+ "pclk_xpcs";
|
|
+ resets = <&cru SRST_A_GMAC0>;
|
|
+ reset-names = "stmmaceth";
|
|
+
|
|
+ snps,mixed-burst;
|
|
+ snps,tso;
|
|
+
|
|
+ snps,axi-config = <&gmac0_stmmac_axi_setup>;
|
|
+ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
|
|
+ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
|
|
+ status = "disabled";
|
|
+
|
|
+ mdio0: mdio {
|
|
+ compatible = "snps,dwmac-mdio";
|
|
+ #address-cells = <0x1>;
|
|
+ #size-cells = <0x0>;
|
|
+ };
|
|
+
|
|
+ gmac0_stmmac_axi_setup: stmmac-axi-config {
|
|
+ snps,wr_osr_lmt = <4>;
|
|
+ snps,rd_osr_lmt = <8>;
|
|
+ snps,blen = <0 0 0 0 16 8 4>;
|
|
+ };
|
|
+
|
|
+ gmac0_mtl_rx_setup: rx-queues-config {
|
|
+ snps,rx-queues-to-use = <1>;
|
|
+ queue0 {};
|
|
+ };
|
|
+
|
|
+ gmac0_mtl_tx_setup: tx-queues-config {
|
|
+ snps,tx-queues-to-use = <1>;
|
|
+ queue0 {};
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc0: dwmmc@fe2b0000 {
|
|
+ compatible = "rockchip,rk3568-dw-mshc",
|
|
+ "rockchip,rk3288-dw-mshc";
|
|
+ reg = <0x0 0xfe2b0000 0x0 0x4000>;
|
|
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ max-frequency = <150000000>;
|
|
+ clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
|
|
+ <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
|
|
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
+ fifo-depth = <0x100>;
|
|
+ resets = <&cru SRST_SDMMC0>;
|
|
+ reset-names = "reset";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ sdmmc1: dwmmc@fe2c0000 {
|
|
+ compatible = "rockchip,rk3568-dw-mshc",
|
|
+ "rockchip,rk3288-dw-mshc";
|
|
+ reg = <0x0 0xfe2c0000 0x0 0x4000>;
|
|
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ max-frequency = <150000000>;
|
|
+ clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
|
|
+ <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
|
|
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
+ fifo-depth = <0x100>;
|
|
+ resets = <&cru SRST_SDMMC1>;
|
|
+ reset-names = "reset";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ sfc: sfc@fe300000 {
|
|
+ compatible = "rockchip,sfc";
|
|
+ reg = <0x0 0xfe300000 0x0 0x4000>;
|
|
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
|
|
+ clock-names = "clk_sfc", "hclk_sfc";
|
|
+ assigned-clocks = <&cru SCLK_SFC>;
|
|
+ assigned-clock-rates = <100000000>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ sdhci: sdhci@fe310000 {
|
|
+ compatible = "rockchip,dwcmshc-sdhci", "snps,dwcmshc-sdhci";
|
|
+ reg = <0x0 0xfe310000 0x0 0x10000>;
|
|
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>,
|
|
+ <&cru CCLK_EMMC>;
|
|
+ assigned-clock-rates = <200000000>, <24000000>, <200000000>;
|
|
+ clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
|
|
+ <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
|
|
+ <&cru TCLK_EMMC>;
|
|
+ clock-names = "core", "bus", "axi", "block", "timer";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ nandc0: nandc@fe330000 {
|
|
+ compatible = "rockchip,rk-nandc-v9";
|
|
+ reg = <0x0 0xfe330000 0x0 0x4000>;
|
|
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ nandc_id = <0>;
|
|
+ clocks = <&cru NCLK_NANDC>, <&cru HCLK_NANDC>;
|
|
+ clock-names = "clk_nandc", "hclk_nandc";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ crypto: crypto@fe380000 {
|
|
+ compatible = "rockchip,rk3568-crypto";
|
|
+ reg = <0x0 0xfe380000 0x0 0x4000>;
|
|
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru ACLK_CRYPTO_NS>, <&cru HCLK_CRYPTO_NS>,
|
|
+ <&cru CLK_CRYPTO_NS_CORE>, <&cru CLK_CRYPTO_NS_PKA>;
|
|
+ clock-names = "aclk", "hclk", "sclk", "apb_pclk";
|
|
+ assigned-clocks = <&cru CLK_CRYPTO_NS_CORE>;
|
|
+ assigned-clock-rates = <200000000>;
|
|
+ resets = <&cru SRST_CRYPTO_NS_CORE>;
|
|
+ reset-names = "crypto-rst";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ rng: rng@fe388000 {
|
|
+ compatible = "rockchip,cryptov2-rng";
|
|
+ reg = <0x0 0xfe388000 0x0 0x2000>;
|
|
+ clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
|
|
+ clock-names = "clk_trng", "hclk_trng";
|
|
+ resets = <&cru SRST_TRNG_NS>;
|
|
+ reset-names = "reset";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ otp: otp@fe38c000 {
|
|
+ compatible = "rockchip,rk3568-otp";
|
|
+ reg = <0x0 0xfe38c000 0x0 0x4000>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ clocks = <&cru CLK_OTPC_NS_USR>, <&cru CLK_OTPC_NS_SBPI>,
|
|
+ <&cru PCLK_OTPC_NS>, <&cru PCLK_OTPPHY>;
|
|
+ clock-names = "usr", "sbpi", "apb", "phy";
|
|
+ resets = <&cru SRST_OTPPHY>;
|
|
+ reset-names = "otp_phy";
|
|
+
|
|
+ /* Data cells */
|
|
+ cpu_code: cpu-code@2 {
|
|
+ reg = <0x02 0x2>;
|
|
+ };
|
|
+ otp_cpu_version: cpu-version@8 {
|
|
+ reg = <0x08 0x1>;
|
|
+ bits = <3 3>;
|
|
+ };
|
|
+ mbist_vmin: mbist-vmin@9 {
|
|
+ reg = <0x09 0x1>;
|
|
+ bits = <0 4>;
|
|
+ };
|
|
+ otp_id: id@a {
|
|
+ reg = <0x0a 0x10>;
|
|
+ };
|
|
+ cpu_leakage: cpu-leakage@1a {
|
|
+ reg = <0x1a 0x1>;
|
|
+ };
|
|
+ log_leakage: log-leakage@1b {
|
|
+ reg = <0x1b 0x1>;
|
|
+ };
|
|
+ npu_leakage: npu-leakage@1c {
|
|
+ reg = <0x1c 0x1>;
|
|
+ };
|
|
+ gpu_leakage: gpu-leakage@1d {
|
|
+ reg = <0x1d 0x1>;
|
|
+ };
|
|
+ core_pvtm:core-pvtm@2a {
|
|
+ reg = <0x2a 0x2>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2s0_8ch: i2s@fe400000 {
|
|
+ compatible = "rockchip,rk3568-i2s-tdm";
|
|
+ reg = <0x0 0xfe400000 0x0 0x1000>;
|
|
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
|
|
+ clock-names = "mclk_tx", "mclk_rx", "hclk";
|
|
+ dmas = <&dmac1 0>;
|
|
+ dma-names = "tx";
|
|
+ resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
|
|
+ reset-names = "tx-m", "rx-m";
|
|
+ rockchip,cru = <&cru>;
|
|
+ rockchip,grf = <&grf>;
|
|
+ rockchip,playback-only;
|
|
+ #sound-dai-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2s1_8ch: i2s@fe410000 {
|
|
+ compatible = "rockchip,rk3568-i2s-tdm";
|
|
+ reg = <0x0 0xfe410000 0x0 0x1000>;
|
|
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
|
|
+ clock-names = "mclk_tx", "mclk_rx", "hclk";
|
|
+ dmas = <&dmac1 2>, <&dmac1 3>;
|
|
+ dma-names = "tx", "rx";
|
|
+ resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
|
|
+ reset-names = "tx-m", "rx-m";
|
|
+ rockchip,cru = <&cru>;
|
|
+ rockchip,grf = <&grf>;
|
|
+ #sound-dai-cells = <0>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2s1m0_sclktx
|
|
+ &i2s1m0_sclkrx
|
|
+ &i2s1m0_lrcktx
|
|
+ &i2s1m0_lrckrx
|
|
+ &i2s1m0_sdi0
|
|
+ &i2s1m0_sdi1
|
|
+ &i2s1m0_sdi2
|
|
+ &i2s1m0_sdi3
|
|
+ &i2s1m0_sdo0
|
|
+ &i2s1m0_sdo1
|
|
+ &i2s1m0_sdo2
|
|
+ &i2s1m0_sdo3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2s2_2ch: i2s@fe420000 {
|
|
+ compatible = "rockchip,rk3568-i2s-tdm";
|
|
+ reg = <0x0 0xfe420000 0x0 0x1000>;
|
|
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
|
|
+ clock-names = "mclk_tx", "mclk_rx", "hclk";
|
|
+ dmas = <&dmac1 4>, <&dmac1 5>;
|
|
+ dma-names = "tx", "rx";
|
|
+ rockchip,cru = <&cru>;
|
|
+ rockchip,grf = <&grf>;
|
|
+ rockchip,clk-trcm = <1>;
|
|
+ #sound-dai-cells = <0>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2s2m0_sclktx
|
|
+ &i2s2m0_lrcktx
|
|
+ &i2s2m0_sdi
|
|
+ &i2s2m0_sdo>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2s3_2ch: i2s@fe430000 {
|
|
+ compatible = "rockchip,rk3568-i2s-tdm";
|
|
+ reg = <0x0 0xfe430000 0x0 0x1000>;
|
|
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, <&cru HCLK_I2S3_2CH>;
|
|
+ clock-names = "mclk_tx", "mclk_rx", "hclk";
|
|
+ dmas = <&dmac1 6>, <&dmac1 7>;
|
|
+ dma-names = "tx", "rx";
|
|
+ resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>;
|
|
+ reset-names = "tx-m", "rx-m";
|
|
+ rockchip,cru = <&cru>;
|
|
+ rockchip,grf = <&grf>;
|
|
+ rockchip,clk-trcm = <1>;
|
|
+ #sound-dai-cells = <0>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2s3m0_sclk
|
|
+ &i2s3m0_lrck
|
|
+ &i2s3m0_sdi
|
|
+ &i2s3m0_sdo>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pdm: pdm@fe440000 {
|
|
+ compatible = "rockchip,rk3568-pdm";
|
|
+ reg = <0x0 0xfe440000 0x0 0x1000>;
|
|
+ clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
|
|
+ clock-names = "pdm_clk", "pdm_hclk";
|
|
+ dmas = <&dmac1 9>;
|
|
+ dma-names = "rx";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pdmm0_clk
|
|
+ &pdmm0_clk1
|
|
+ &pdmm0_sdi0
|
|
+ &pdmm0_sdi1
|
|
+ &pdmm0_sdi2
|
|
+ &pdmm0_sdi3>;
|
|
+ #sound-dai-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ vad: vad@fe450000 {
|
|
+ compatible = "rockchip,rk3568-vad";
|
|
+ reg = <0x0 0xfe450000 0x0 0x10000>;
|
|
+ reg-names = "vad";
|
|
+ clocks = <&cru HCLK_VAD>;
|
|
+ clock-names = "hclk";
|
|
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ rockchip,audio-src = <0>;
|
|
+ rockchip,det-channel = <0>;
|
|
+ rockchip,mode = <0>;
|
|
+ #sound-dai-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ spdif_8ch: spdif@fe460000 {
|
|
+ compatible = "rockchip,rk3568-spdif";
|
|
+ reg = <0x0 0xfe460000 0x0 0x1000>;
|
|
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ dmas = <&dmac1 1>;
|
|
+ dma-names = "tx";
|
|
+ clock-names = "mclk", "hclk";
|
|
+ clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
|
|
+ #sound-dai-cells = <0>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&spdifm0_tx>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ audpwm: audpwm@fe470000 {
|
|
+ compatible = "rockchip,rk3568-audio-pwm", "rockchip,audio-pwm-v1";
|
|
+ reg = <0x0 0xfe470000 0x0 0x1000>;
|
|
+ clocks = <&cru SCLK_AUDPWM>, <&cru HCLK_AUDPWM>;
|
|
+ clock-names = "clk", "hclk";
|
|
+ dmas = <&dmac1 8>;
|
|
+ dma-names = "tx";
|
|
+ #sound-dai-cells = <0>;
|
|
+ rockchip,sample-width-bits = <11>;
|
|
+ rockchip,interpolat-points = <1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ dig_acodec: codec-digital@fe478000 {
|
|
+ compatible = "rockchip,rk3568-codec-digital", "rockchip,codec-digital-v1";
|
|
+ reg = <0x0 0xfe478000 0x0 0x1000>;
|
|
+ clocks = <&cru CLK_ACDCDIG_ADC>, <&cru CLK_ACDCDIG_DAC>,
|
|
+ <&cru CLK_ACDCDIG_I2C>, <&cru HCLK_ACDCDIG>;
|
|
+ clock-names = "adc", "dac", "i2c", "pclk";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&acodec_pins>;
|
|
+ resets = <&cru SRST_ACDCDIG>;
|
|
+ reset-names = "reset" ;
|
|
+ rockchip,grf = <&grf>;
|
|
+ #sound-dai-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ dmac0: dmac@fe530000 {
|
|
+ compatible = "arm,pl330", "arm,primecell";
|
|
+ reg = <0x0 0xfe530000 0x0 0x4000>;
|
|
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru ACLK_BUS>;
|
|
+ clock-names = "apb_pclk";
|
|
+ #dma-cells = <1>;
|
|
+ arm,pl330-periph-burst;
|
|
+ };
|
|
+
|
|
+ dmac1: dmac@fe550000 {
|
|
+ compatible = "arm,pl330", "arm,primecell";
|
|
+ reg = <0x0 0xfe550000 0x0 0x4000>;
|
|
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru ACLK_BUS>;
|
|
+ clock-names = "apb_pclk";
|
|
+ #dma-cells = <1>;
|
|
+ arm,pl330-periph-burst;
|
|
+ };
|
|
+
|
|
+ scr: rkscr@fe560000 {
|
|
+ compatible = "rockchip-scr";
|
|
+ reg = <0x0 0xfe560000 0x0 0x10000>;
|
|
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&scr_pins>;
|
|
+ clocks = <&cru PCLK_SCR>;
|
|
+ clock-names = "g_pclk_sim_card";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ can0: can@fe570000 {
|
|
+ compatible = "rockchip,canfd-1.0";
|
|
+ reg = <0x0 0xfe570000 0x0 0x1000>;
|
|
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>;
|
|
+ clock-names = "baudclk", "apb_pclk";
|
|
+ resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>;
|
|
+ reset-names = "can", "can-apb";
|
|
+ tx-fifo-depth = <1>;
|
|
+ rx-fifo-depth = <6>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ can1: can@fe580000 {
|
|
+ compatible = "rockchip,canfd-1.0";
|
|
+ reg = <0x0 0xfe580000 0x0 0x1000>;
|
|
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>;
|
|
+ clock-names = "baudclk", "apb_pclk";
|
|
+ resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>;
|
|
+ reset-names = "can", "can-apb";
|
|
+ tx-fifo-depth = <1>;
|
|
+ rx-fifo-depth = <6>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ can2: can@fe590000 {
|
|
+ compatible = "rockchip,canfd-1.0";
|
|
+ reg = <0x0 0xfe590000 0x0 0x1000>;
|
|
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>;
|
|
+ clock-names = "baudclk", "apb_pclk";
|
|
+ resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>;
|
|
+ reset-names = "can", "can-apb";
|
|
+ tx-fifo-depth = <1>;
|
|
+ rx-fifo-depth = <6>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2c1: i2c@fe5a0000 {
|
|
+ compatible = "rockchip,rk3399-i2c";
|
|
+ reg = <0x0 0xfe5a0000 0x0 0x1000>;
|
|
+ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
|
|
+ clock-names = "i2c", "pclk";
|
|
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c1_xfer>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2c2: i2c@fe5b0000 {
|
|
+ compatible = "rockchip,rk3399-i2c";
|
|
+ reg = <0x0 0xfe5b0000 0x0 0x1000>;
|
|
+ clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
|
|
+ clock-names = "i2c", "pclk";
|
|
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c2m0_xfer>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2c3: i2c@fe5c0000 {
|
|
+ compatible = "rockchip,rk3399-i2c";
|
|
+ reg = <0x0 0xfe5c0000 0x0 0x1000>;
|
|
+ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
|
|
+ clock-names = "i2c", "pclk";
|
|
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c3m0_xfer>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2c4: i2c@fe5d0000 {
|
|
+ compatible = "rockchip,rk3399-i2c";
|
|
+ reg = <0x0 0xfe5d0000 0x0 0x1000>;
|
|
+ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
|
|
+ clock-names = "i2c", "pclk";
|
|
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c4m0_xfer>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2c5: i2c@fe5e0000 {
|
|
+ compatible = "rockchip,rk3399-i2c";
|
|
+ reg = <0x0 0xfe5e0000 0x0 0x1000>;
|
|
+ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
|
|
+ clock-names = "i2c", "pclk";
|
|
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c5m0_xfer>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ rktimer: timer@fe5f0000 {
|
|
+ compatible = "rockchip,rk3568-timer", "rockchip,rk3288-timer";
|
|
+ reg = <0x0 0xfe5f0000 0x0 0x1000>;
|
|
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
|
|
+ clock-names = "pclk", "timer";
|
|
+ };
|
|
+
|
|
+ wdt: watchdog@fe600000 {
|
|
+ compatible = "snps,dw-wdt";
|
|
+ reg = <0x0 0xfe600000 0x0 0x100>;
|
|
+ clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
|
|
+ clock-names = "tclk", "pclk";
|
|
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
+ spi0: spi@fe610000 {
|
|
+ compatible = "rockchip,rk3066-spi";
|
|
+ reg = <0x0 0xfe610000 0x0 0x1000>;
|
|
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
|
|
+ clock-names = "spiclk", "apb_pclk";
|
|
+ dmas = <&dmac0 20>, <&dmac0 21>;
|
|
+ dma-names = "tx", "rx";
|
|
+ pinctrl-names = "default", "high_speed";
|
|
+ pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
|
|
+ pinctrl-1 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins_hs>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ spi1: spi@fe620000 {
|
|
+ compatible = "rockchip,rk3066-spi";
|
|
+ reg = <0x0 0xfe620000 0x0 0x1000>;
|
|
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
|
|
+ clock-names = "spiclk", "apb_pclk";
|
|
+ dmas = <&dmac0 22>, <&dmac0 23>;
|
|
+ dma-names = "tx", "rx";
|
|
+ pinctrl-names = "default", "high_speed";
|
|
+ pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
|
|
+ pinctrl-1 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins_hs>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ spi2: spi@fe630000 {
|
|
+ compatible = "rockchip,rk3066-spi";
|
|
+ reg = <0x0 0xfe630000 0x0 0x1000>;
|
|
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
|
|
+ clock-names = "spiclk", "apb_pclk";
|
|
+ dmas = <&dmac0 24>, <&dmac0 25>;
|
|
+ dma-names = "tx", "rx";
|
|
+ pinctrl-names = "default", "high_speed";
|
|
+ pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
|
|
+ pinctrl-1 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins_hs>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ spi3: spi@fe640000 {
|
|
+ compatible = "rockchip,rk3066-spi";
|
|
+ reg = <0x0 0xfe640000 0x0 0x1000>;
|
|
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
|
|
+ clock-names = "spiclk", "apb_pclk";
|
|
+ dmas = <&dmac0 26>, <&dmac0 27>;
|
|
+ dma-names = "tx", "rx";
|
|
+ pinctrl-names = "default", "high_speed";
|
|
+ pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
|
|
+ pinctrl-1 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins_hs>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart1: serial@fe650000 {
|
|
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
+ reg = <0x0 0xfe650000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
|
|
+ clock-names = "baudclk", "apb_pclk";
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ dmas = <&dmac0 2>, <&dmac0 3>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart1m0_xfer>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart2: serial@fe660000 {
|
|
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
+ reg = <0x0 0xfe660000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
|
|
+ clock-names = "baudclk", "apb_pclk";
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ dmas = <&dmac0 4>, <&dmac0 5>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart2m0_xfer>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart3: serial@fe670000 {
|
|
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
+ reg = <0x0 0xfe670000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
|
|
+ clock-names = "baudclk", "apb_pclk";
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ dmas = <&dmac0 6>, <&dmac0 7>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart3m0_xfer>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart4: serial@fe680000 {
|
|
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
+ reg = <0x0 0xfe680000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
|
|
+ clock-names = "baudclk", "apb_pclk";
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ dmas = <&dmac0 8>, <&dmac0 9>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart4m0_xfer>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart5: serial@fe690000 {
|
|
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
+ reg = <0x0 0xfe690000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
|
|
+ clock-names = "baudclk", "apb_pclk";
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ dmas = <&dmac0 10>, <&dmac0 11>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart5m0_xfer>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart6: serial@fe6a0000 {
|
|
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
+ reg = <0x0 0xfe6a0000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
|
|
+ clock-names = "baudclk", "apb_pclk";
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ dmas = <&dmac0 12>, <&dmac0 13>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart6m0_xfer>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart7: serial@fe6b0000 {
|
|
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
+ reg = <0x0 0xfe6b0000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
|
|
+ clock-names = "baudclk", "apb_pclk";
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ dmas = <&dmac0 14>, <&dmac0 15>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart7m0_xfer>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart8: serial@fe6c0000 {
|
|
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
+ reg = <0x0 0xfe6c0000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
|
|
+ clock-names = "baudclk", "apb_pclk";
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ dmas = <&dmac0 16>, <&dmac0 17>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart8m0_xfer>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart9: serial@fe6d0000 {
|
|
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
+ reg = <0x0 0xfe6d0000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
|
|
+ clock-names = "baudclk", "apb_pclk";
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ dmas = <&dmac0 18>, <&dmac0 19>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart9m0_xfer>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm4: pwm@fe6e0000 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfe6e0000 0x0 0x10>;
|
|
+ #pwm-cells = <3>;
|
|
+ pinctrl-names = "active";
|
|
+ pinctrl-0 = <&pwm4_pins>;
|
|
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm5: pwm@fe6e0010 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfe6e0010 0x0 0x10>;
|
|
+ #pwm-cells = <3>;
|
|
+ pinctrl-names = "active";
|
|
+ pinctrl-0 = <&pwm5_pins>;
|
|
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm6: pwm@fe6e0020 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfe6e0020 0x0 0x10>;
|
|
+ #pwm-cells = <3>;
|
|
+ pinctrl-names = "active";
|
|
+ pinctrl-0 = <&pwm6_pins>;
|
|
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm7: pwm@fe6e0030 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfe6e0030 0x0 0x10>;
|
|
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ #pwm-cells = <3>;
|
|
+ pinctrl-names = "active";
|
|
+ pinctrl-0 = <&pwm7_pins>;
|
|
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm8: pwm@fe6f0000 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfe6f0000 0x0 0x10>;
|
|
+ #pwm-cells = <3>;
|
|
+ pinctrl-names = "active";
|
|
+ pinctrl-0 = <&pwm8m0_pins>;
|
|
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm9: pwm@fe6f0010 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfe6f0010 0x0 0x10>;
|
|
+ #pwm-cells = <3>;
|
|
+ pinctrl-names = "active";
|
|
+ pinctrl-0 = <&pwm9m0_pins>;
|
|
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm10: pwm@fe6f0020 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfe6f0020 0x0 0x10>;
|
|
+ #pwm-cells = <3>;
|
|
+ pinctrl-names = "active";
|
|
+ pinctrl-0 = <&pwm10m0_pins>;
|
|
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm11: pwm@fe6f0030 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfe6f0030 0x0 0x10>;
|
|
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ #pwm-cells = <3>;
|
|
+ pinctrl-names = "active";
|
|
+ pinctrl-0 = <&pwm11m0_pins>;
|
|
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm12: pwm@fe700000 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfe700000 0x0 0x10>;
|
|
+ #pwm-cells = <3>;
|
|
+ pinctrl-names = "active";
|
|
+ pinctrl-0 = <&pwm12m0_pins>;
|
|
+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm13: pwm@fe700010 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfe700010 0x0 0x10>;
|
|
+ #pwm-cells = <3>;
|
|
+ pinctrl-names = "active";
|
|
+ pinctrl-0 = <&pwm13m0_pins>;
|
|
+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm14: pwm@fe700020 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfe700020 0x0 0x10>;
|
|
+ #pwm-cells = <3>;
|
|
+ pinctrl-names = "active";
|
|
+ pinctrl-0 = <&pwm14m0_pins>;
|
|
+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm15: pwm@fe700030 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfe700030 0x0 0x10>;
|
|
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ #pwm-cells = <3>;
|
|
+ pinctrl-names = "active";
|
|
+ pinctrl-0 = <&pwm15m0_pins>;
|
|
+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ tsadc: tsadc@fe710000 {
|
|
+ compatible = "rockchip,rk3568-tsadc";
|
|
+ reg = <0x0 0xfe710000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ rockchip,grf = <&grf>;
|
|
+ clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
|
|
+ clock-names = "tsadc", "apb_pclk";
|
|
+ assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
|
|
+ assigned-clock-rates = <17000000>, <700000>;
|
|
+ resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>,
|
|
+ <&cru SRST_TSADCPHY>;
|
|
+ reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
|
|
+ #thermal-sensor-cells = <1>;
|
|
+ rockchip,hw-tshut-temp = <120000>;
|
|
+ rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
|
|
+ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
|
|
+ pinctrl-names = "gpio", "otpout";
|
|
+ pinctrl-0 = <&tsadc_gpio_func>;
|
|
+ pinctrl-1 = <&tsadc_shutorg>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ saradc: saradc@fe720000 {
|
|
+ compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
|
|
+ reg = <0x0 0xfe720000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ #io-channel-cells = <1>;
|
|
+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
|
|
+ clock-names = "saradc", "apb_pclk";
|
|
+ resets = <&cru SRST_P_SARADC>;
|
|
+ reset-names = "saradc-apb";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ mailbox: mailbox@fe780000 {
|
|
+ compatible = "rockchip,rk3568-mailbox",
|
|
+ "rockchip,rk3368-mailbox";
|
|
+ reg = <0x0 0xfe780000 0x0 0x1000>;
|
|
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru PCLK_MAILBOX>;
|
|
+ clock-names = "pclk_mailbox";
|
|
+ #mbox-cells = <1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ combphy0_us: phy@fe820000 {
|
|
+ compatible = "rockchip,rk3568-naneng-combphy";
|
|
+ reg = <0x0 0xfe820000 0x0 0x100>;
|
|
+ #phy-cells = <1>;
|
|
+ clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>,
|
|
+ <&cru PCLK_PIPE>;
|
|
+ clock-names = "refclk", "apbclk", "pipe_clk";
|
|
+ assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
|
|
+ assigned-clock-rates = <100000000>;
|
|
+ resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>;
|
|
+ reset-names = "combphy-apb", "combphy";
|
|
+ rockchip,pipe-grf = <&pipegrf>;
|
|
+ rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ combphy1_usq: phy@fe830000 {
|
|
+ compatible = "rockchip,rk3568-naneng-combphy";
|
|
+ reg = <0x0 0xfe830000 0x0 0x100>;
|
|
+ #phy-cells = <1>;
|
|
+ clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>,
|
|
+ <&cru PCLK_PIPE>;
|
|
+ clock-names = "refclk", "apbclk", "pipe_clk";
|
|
+ assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
|
|
+ assigned-clock-rates = <100000000>;
|
|
+ resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>;
|
|
+ reset-names = "combphy-apb", "combphy";
|
|
+ rockchip,pipe-grf = <&pipegrf>;
|
|
+ rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ combphy2_psq: phy@fe840000 {
|
|
+ compatible = "rockchip,rk3568-naneng-combphy";
|
|
+ reg = <0x0 0xfe840000 0x0 0x100>;
|
|
+ #phy-cells = <1>;
|
|
+ clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>,
|
|
+ <&cru PCLK_PIPE>;
|
|
+ clock-names = "refclk", "apbclk", "pipe_clk";
|
|
+ assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
|
|
+ assigned-clock-rates = <100000000>;
|
|
+ resets = <&cru SRST_P_PIPEPHY2>, <&cru SRST_PIPEPHY2>;
|
|
+ reset-names = "combphy-apb", "combphy";
|
|
+ rockchip,pipe-grf = <&pipegrf>;
|
|
+ rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ video_phy0: video-phy@fe850000 {
|
|
+ compatible = "rockchip,rk3568-video-phy";
|
|
+ reg = <0x0 0xfe850000 0x0 0x10000>,
|
|
+ <0x0 0xfe060000 0x0 0x10000>;
|
|
+ clocks = <&pmucru CLK_MIPIDSIPHY0_REF>,
|
|
+ <&cru PCLK_MIPIDSIPHY0>, <&cru PCLK_DSITX_0>;
|
|
+ clock-names = "ref", "pclk_phy", "pclk_host";
|
|
+ #clock-cells = <0>;
|
|
+ resets = <&cru SRST_P_MIPIDSIPHY0>;
|
|
+ reset-names = "rst";
|
|
+ power-domains = <&power RK3568_PD_VO>;
|
|
+ #phy-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ video_phy1: video-phy@fe860000 {
|
|
+ compatible = "rockchip,rk3568-video-phy";
|
|
+ reg = <0x0 0xfe860000 0x0 0x10000>,
|
|
+ <0x0 0xfe070000 0x0 0x10000>;
|
|
+ clocks = <&pmucru CLK_MIPIDSIPHY1_REF>,
|
|
+ <&cru PCLK_MIPIDSIPHY1>, <&cru PCLK_DSITX_1>;
|
|
+ clock-names = "ref", "pclk_phy", "pclk_host";
|
|
+ #clock-cells = <0>;
|
|
+ resets = <&cru SRST_P_MIPIDSIPHY1>;
|
|
+ reset-names = "rst";
|
|
+ power-domains = <&power RK3568_PD_VO>;
|
|
+ #phy-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ csi2_dphy_hw: csi2-dphy-hw@fe870000 {
|
|
+ compatible = "rockchip,rk3568-csi2-dphy-hw";
|
|
+ reg = <0x0 0xfe870000 0x0 0x1000>;
|
|
+ clocks = <&cru PCLK_MIPICSIPHY>;
|
|
+ clock-names = "pclk";
|
|
+ rockchip,grf = <&grf>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ /*
|
|
+ * csi2_dphy0: used for csi2 dphy full mode,
|
|
+ is mutually exclusive with
|
|
+ csi2_dphy1 and csi2_dphy2
|
|
+ * csi2_dphy1: used for csi2 dphy split mode,
|
|
+ physical lanes use lane0 and lane1,
|
|
+ can be used with csi2_dphy2 parallel
|
|
+ * csi2_dphy2: used for csi2 dphy split mode,
|
|
+ physical lanes use lane2 and lane3,
|
|
+ can be used with csi2_dphy1 parallel
|
|
+ */
|
|
+ csi2_dphy0: csi2-dphy0 {
|
|
+ compatible = "rockchip,rk3568-csi2-dphy";
|
|
+ rockchip,hw = <&csi2_dphy_hw>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ csi2_dphy1: csi2-dphy1 {
|
|
+ compatible = "rockchip,rk3568-csi2-dphy";
|
|
+ rockchip,hw = <&csi2_dphy_hw>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ csi2_dphy2: csi2-dphy2 {
|
|
+ compatible = "rockchip,rk3568-csi2-dphy";
|
|
+ rockchip,hw = <&csi2_dphy_hw>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb2phy0: usb2-phy@fe8a0000 {
|
|
+ compatible = "rockchip,rk3568-usb2phy";
|
|
+ reg = <0x0 0xfe8a0000 0x0 0x10000>;
|
|
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&pmucru CLK_USBPHY0_REF>;
|
|
+ clock-names = "phyclk";
|
|
+ #clock-cells = <0>;
|
|
+ assigned-clocks = <&cru USB480M>;
|
|
+ assigned-clock-parents = <&usb2phy0>;
|
|
+ clock-output-names = "usb480m_phy";
|
|
+ rockchip,usbgrf = <&usb2phy0_grf>;
|
|
+ status = "disabled";
|
|
+
|
|
+ u2phy0_host: host-port {
|
|
+ #phy-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ u2phy0_otg: otg-port {
|
|
+ #phy-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usb2phy1: usb2-phy@fe8b0000 {
|
|
+ compatible = "rockchip,rk3568-usb2phy";
|
|
+ reg = <0x0 0xfe8b0000 0x0 0x10000>;
|
|
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&pmucru CLK_USBPHY1_REF>;
|
|
+ clock-names = "phyclk";
|
|
+ #clock-cells = <0>;
|
|
+ rockchip,usbgrf = <&usb2phy1_grf>;
|
|
+ status = "disabled";
|
|
+
|
|
+ u2phy1_host: host-port {
|
|
+ #phy-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ u2phy1_otg: otg-port {
|
|
+ #phy-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pcie30phy: phy@fe8c0000 {
|
|
+ compatible = "rockchip,rk3568-pcie3-phy";
|
|
+ reg = <0x0 0xfe8c0000 0x0 0x20000>;
|
|
+ #phy-cells = <0>;
|
|
+ clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
|
|
+ <&cru PCLK_PCIE30PHY>;
|
|
+ clock-names = "refclk_m", "refclk_n", "pclk";
|
|
+ resets = <&cru SRST_PCIE30PHY>;
|
|
+ reset-names = "phy";
|
|
+ rockchip,phy-grf = <&pcie30_phy_grf>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pinctrl: pinctrl {
|
|
+ compatible = "rockchip,rk3568-pinctrl";
|
|
+ rockchip,grf = <&grf>;
|
|
+ rockchip,pmu = <&pmugrf>;
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <2>;
|
|
+ ranges;
|
|
+
|
|
+ gpio0: gpio@fdd60000 {
|
|
+ compatible = "rockchip,gpio-bank";
|
|
+ reg = <0x0 0xfdd60000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
|
|
+
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ gpio-ranges = <&pinctrl 0 0 32>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ };
|
|
+
|
|
+ gpio1: gpio@fe740000 {
|
|
+ compatible = "rockchip,gpio-bank";
|
|
+ reg = <0x0 0xfe740000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
|
|
+
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ gpio-ranges = <&pinctrl 0 32 32>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ };
|
|
+
|
|
+ gpio2: gpio@fe750000 {
|
|
+ compatible = "rockchip,gpio-bank";
|
|
+ reg = <0x0 0xfe750000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
|
|
+
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ gpio-ranges = <&pinctrl 0 64 32>;
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+ interrupt-controller;
|
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+ #interrupt-cells = <2>;
|
|
+ };
|
|
+
|
|
+ gpio3: gpio@fe760000 {
|
|
+ compatible = "rockchip,gpio-bank";
|
|
+ reg = <0x0 0xfe760000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
|
|
+
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ gpio-ranges = <&pinctrl 0 96 32>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ };
|
|
+
|
|
+ gpio4: gpio@fe770000 {
|
|
+ compatible = "rockchip,gpio-bank";
|
|
+ reg = <0x0 0xfe770000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
|
|
+
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ gpio-ranges = <&pinctrl 0 128 32>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+#include "rk3568-pinctrl.dtsi"
|