89 lines
3.4 KiB
Diff
89 lines
3.4 KiB
Diff
From 28ad70a06fb84fe63cd036970db2561b2fd1562b Mon Sep 17 00:00:00 2001
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From: Hans de Goede <hdegoede@redhat.com>
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Date: Sun, 5 Nov 2017 16:51:23 +0100
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Subject: [PATCH v3 1/2] i915: pm: Be less agressive with clockfreq changes on
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Bay Trail
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Bay Trail devices are known to hang when changing the frequency often,
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this is discussed in great length in:
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https://bugzilla.kernel.org/show_bug.cgi?id=109051
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Commit 6067a27d1f01 ("drm/i915: Avoid tweaking evaluation thresholds
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on Baytrail v3") is an attempt to workaround this. Several users in
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bko109051 report that an earlier version of this patch, v1:
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https://bugzilla.kernel.org/attachment.cgi?id=251471
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Works better for them and they still see hangs with the merged v3.
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Comparing the 2 versions shows that they are indeed not equivalent,
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v1 not only skips writing the GEN6_RP* registers from valleyview_set_rps,
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as v3 does. It also contained these modifications to i915_irq.c:
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if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
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if (!vlv_c0_above(dev_priv,
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&dev_priv->rps.down_ei, &now,
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- dev_priv->rps.down_threshold))
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+ VLV_RP_DOWN_EI_THRESHOLD))
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events |= GEN6_PM_RP_DOWN_THRESHOLD;
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dev_priv->rps.down_ei = now;
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}
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if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
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if (vlv_c0_above(dev_priv,
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&dev_priv->rps.up_ei, &now,
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- dev_priv->rps.up_threshold))
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+ VLV_RP_UP_EI_THRESHOLD))
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events |= GEN6_PM_RP_UP_THRESHOLD;
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dev_priv->rps.up_ei = now;
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}
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Which use less aggressive up/down thresholds, which results in less
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GEN6_PM_RP_*_THRESHOLD events and thus in less calls to intel_set_rps() ->
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valleyview_set_rps() -> vlv_punit_write(PUNIT_REG_GPU_FREQ_REQ).
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With the last call being the likely cause of the hang.
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This commit hardcodes the threshold_up and _down values for Bay Trail to
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less aggressive values, reducing the amount of clock frequency changes,
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thus avoiding the hangs some people are still seeing with the merged fix.
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Buglink: https://bugzilla.kernel.org/show_bug.cgi?id=109051
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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---
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drivers/gpu/drm/i915/i915_reg.h | 3 +++
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drivers/gpu/drm/i915/intel_pm.c | 5 ++++-
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2 files changed, 7 insertions(+), 1 deletion(-)
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diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
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index 68a58cce6ab1..2561af075ebb 100644
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--- a/drivers/gpu/drm/i915/i915_reg.h
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+++ b/drivers/gpu/drm/i915/i915_reg.h
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@@ -1355,6 +1355,9 @@ enum i915_power_well_id {
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#define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
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#define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
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+#define VLV_RP_UP_EI_THRESHOLD 90
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+#define VLV_RP_DOWN_EI_THRESHOLD 70
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+
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/* vlv2 north clock has */
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#define CCK_FUSE_REG 0x8
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#define CCK_FUSE_HPLL_FREQ_MASK 0x3
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diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
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index 01966b89be14..177b6caa0a38 100644
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--- a/drivers/gpu/drm/i915/intel_pm.c
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+++ b/drivers/gpu/drm/i915/intel_pm.c
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@@ -6096,8 +6096,11 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
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/* When byt can survive without system hang with dynamic
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* sw freq adjustments, this restriction can be lifted.
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*/
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- if (IS_VALLEYVIEW(dev_priv))
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+ if (IS_VALLEYVIEW(dev_priv)) {
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+ threshold_up = VLV_RP_UP_EI_THRESHOLD;
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+ threshold_down = VLV_RP_DOWN_EI_THRESHOLD;
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goto skip_hw_write;
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+ }
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I915_WRITE(GEN6_RP_UP_EI,
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GT_INTERVAL_FROM_US(dev_priv, ei_up));
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--
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2.14.3
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