c24972b592
Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Closes Homebrew/homebrew#12798. Signed-off-by: Adam Vandenberg <flangy@gmail.com>
15 lines
391 B
Ruby
15 lines
391 B
Ruby
require 'formula'
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class Verilator < Formula
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homepage 'http://www.veripool.org/wiki/verilator'
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url 'http://www.veripool.org/ftp/verilator-3.833.tgz'
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sha1 '4ca58d609371b0a6309c5564a5e8ba6857aa15db'
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skip_clean 'bin' # Allows perl scripts to keep their executable flag
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def install
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system "./configure", "--prefix=#{prefix}"
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system "make"
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system "make install"
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end
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end
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