This is an *initial* tune-up. This update puts Itanium2 back on par with
Itanium. I mean if overall performance improvement over C version was X for Itanium, it's now X even for Itanium2.
This commit is contained in:
Andy Polyakov
parent
b01db3b279
commit
30167ace51
1 changed files with 76 additions and 47 deletions
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@ -1,6 +1,6 @@
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.explicit
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.text
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.ident "ia64.S, Version 1.2"
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.ident "ia64.S, Version 2.0"
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.ident "IA-64 ISA artwork by Andy Polyakov <appro@fy.chalmers.se>"
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//
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@ -13,6 +13,35 @@
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// disclaimed.
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// ====================================================================
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//
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// Version 2.x is Itanium2 re-tune. Few words about how Itanum2 is
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// different from Itanium to this module viewpoint. Most notably, is it
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// "wider" than Itanium? Can you experience loop scalability as
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// discussed in commentary sections? Not really:-( Itanium2 has 6
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// integer ALU ports, i.e. it's 2 ports wider, but it's not enough to
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// spin twice as fast, as I need 8 IALU ports. Amount of floating point
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// ports is the same, i.e. 2, while I need 4. In other words, to this
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// module Itanium2 remains effectively as "wide" as Itanium. Yet it's
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// essentially different in respect to this module, and a re-tune was
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// required. Well, because some intruction latencies has changed. Most
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// noticeably those intensively used:
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//
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// Itanium Itanium2
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// ldf8 9 6 L2 hit
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// ld8 2 1 L1 hit
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// getf 2 5
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// xma[->getf] 7[+1] 4[+0]
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// add[->st8] 1[+1] 1[+0]
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//
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// What does it mean? You might ratiocinate that the original code
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// should run just faster... Because sum of latencies is smaller...
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// Wrong! Note that getf latency increased. This means that if a loop is
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// scheduled for lower latency (and they are), then it will suffer from
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// stall condition and the code will therefore turn anti-scalable, e.g.
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// original bn_mul_words spun at 5*n or 2.5 times slower than expected
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// on Itanium2! What to do? Reschedule loops for Itanium2? But then
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// Itanium would exhibit anti-scalability. So I've chosen to reschedule
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// for worst latency for every instruction aiming for best *all-round*
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// performance.
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// Q. How much faster does it get?
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// A. Here is the output from 'openssl speed rsa dsa' for vanilla
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@ -283,7 +312,7 @@ bn_mul_words:
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#ifdef XMA_TEMPTATION
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{ .mfi; alloc r2=ar.pfs,4,0,0,0 };;
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#else
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{ .mfi; alloc r2=ar.pfs,4,4,0,8 };;
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{ .mfi; alloc r2=ar.pfs,4,12,0,16 };;
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#endif
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{ .mib; mov r8=r0 // return value
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cmp4.le p6,p0=r34,r0
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@ -296,8 +325,8 @@ bn_mul_words:
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.body
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{ .mib; setf.sig f8=r35 // w
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mov pr.rot=0x400001<<16
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// ------^----- serves as (p48) at first (p26)
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mov pr.rot=0x800001<<16
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// ------^----- serves as (p50) at first (p27)
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brp.loop.imp .L_bn_mul_words_ctop,.L_bn_mul_words_cend-16
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}
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@ -312,14 +341,14 @@ bn_mul_words:
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mov r15=r33 // ap
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#endif
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mov ar.lc=r10 }
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{ .mii; mov r39=0 // serves as r33 at first (p26)
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mov ar.ec=12 };;
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{ .mii; mov r40=0 // serves as r35 at first (p27)
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mov ar.ec=13 };;
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// This loop spins in 2*(n+11) ticks. It's scheduled for data in L2
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// cache (i.e. 9 ticks away) as floating point load/store instructions
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// This loop spins in 2*(n+12) ticks. It's scheduled for data in Itanium
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// L2 cache (i.e. 9 ticks away) as floating point load/store instructions
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// bypass L1 cache and L2 latency is actually best-case scenario for
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// ldf8. The loop is not scalable and shall run in 2*(n+11) even on
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// "wider" IA-64 implementations. It's a trade-off here. n+22 loop
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// ldf8. The loop is not scalable and shall run in 2*(n+12) even on
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// "wider" IA-64 implementations. It's a trade-off here. n+24 loop
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// would give us ~5% in *overall* performance improvement on "wider"
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// IA-64, but would hurt Itanium for about same because of longer
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// epilogue. As it's a matter of few percents in either case I've
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@ -327,25 +356,25 @@ bn_mul_words:
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// this very instruction sequence in bn_mul_add_words loop which in
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// turn is scalable).
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.L_bn_mul_words_ctop:
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{ .mfi; (p25) getf.sig r36=f49 // low
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(p21) xmpy.lu f45=f37,f8
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(p27) cmp.ltu p52,p48=r39,r38 }
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{ .mfi; (p25) getf.sig r36=f52 // low
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(p21) xmpy.lu f48=f37,f8
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(p28) cmp.ltu p54,p50=r41,r39 }
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{ .mfi; (p16) ldf8 f32=[r15],8
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(p21) xmpy.hu f38=f37,f8
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(p21) xmpy.hu f40=f37,f8
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(p0) nop.i 0x0 };;
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{ .mii; (p26) getf.sig r32=f43 // high
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.pred.rel "mutex",p48,p52
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(p48) add r38=r37,r33 // (p26)
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(p52) add r38=r37,r33,1 } // (p26)
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{ .mfb; (p27) st8 [r14]=r39,8
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{ .mii; (p25) getf.sig r32=f44 // high
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.pred.rel "mutex",p50,p54
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(p50) add r40=r38,r35 // (p27)
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(p54) add r40=r38,r35,1 } // (p27)
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{ .mfb; (p28) st8 [r14]=r41,8
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(p0) nop.f 0x0
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br.ctop.sptk .L_bn_mul_words_ctop };;
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.L_bn_mul_words_cend:
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{ .mii; nop.m 0x0
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.pred.rel "mutex",p49,p53
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(p49) add r8=r34,r0
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(p53) add r8=r34,r0,1 }
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.pred.rel "mutex",p51,p55
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(p51) add r8=r36,r0
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(p55) add r8=r36,r0,1 }
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{ .mfb; nop.m 0x0
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nop.f 0x0
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nop.b 0x0 }
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@ -412,8 +441,8 @@ bn_mul_add_words:
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.body
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{ .mib; setf.sig f8=r35 // w
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mov pr.rot=0x400001<<16
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// ------^----- serves as (p48) at first (p26)
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mov pr.rot=0x800001<<16
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// ------^----- serves as (p50) at first (p27)
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brp.loop.imp .L_bn_mul_add_words_ctop,.L_bn_mul_add_words_cend-16
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}
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{ .mii;
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@ -425,55 +454,55 @@ bn_mul_add_words:
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mov r15=r33 // ap
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#endif
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mov ar.lc=r10 }
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{ .mii; mov r39=0 // serves as r33 at first (p26)
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{ .mii; mov r40=0 // serves as r35 at first (p27)
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#if defined(_HPUX_SOURCE) && defined(_ILP32)
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addp4 r18=0,r32 // rp copy
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#else
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mov r18=r32 // rp copy
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#endif
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mov ar.ec=14 };;
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mov ar.ec=15 };;
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// This loop spins in 3*(n+13) ticks on Itanium and should spin in
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// 2*(n+13) on "wider" IA-64 implementations (to be verified with new
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// This loop spins in 3*(n+14) ticks on Itanium and should spin in
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// 2*(n+14) on "wider" IA-64 implementations (to be verified with new
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// µ-architecture manuals as they become available). As usual it's
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// possible to compress the epilogue, down to 10 in this case, at the
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// cost of scalability. Compressed (and therefore non-scalable) loop
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// running at 3*(n+10) would buy you ~10% on Itanium but take ~35%
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// running at 3*(n+11) would buy you ~10% on Itanium but take ~35%
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// from "wider" IA-64 so let it be scalable! Special attention was
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// paid for having the loop body split at 64-byte boundary. ld8 is
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// scheduled for L1 cache as the data is more than likely there.
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// Indeed, bn_mul_words has put it there a moment ago:-)
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.L_bn_mul_add_words_ctop:
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{ .mfi; (p25) getf.sig r36=f49 // low
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(p21) xmpy.lu f45=f37,f8
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(p27) cmp.ltu p52,p48=r39,r38 }
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{ .mfi; (p25) getf.sig r36=f52 // low
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(p21) xmpy.lu f48=f37,f8
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(p28) cmp.ltu p54,p50=r41,r39 }
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{ .mfi; (p16) ldf8 f32=[r15],8
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(p21) xmpy.hu f38=f37,f8
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(p27) add r43=r43,r39 };;
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{ .mii; (p26) getf.sig r32=f43 // high
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.pred.rel "mutex",p48,p52
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(p48) add r38=r37,r33 // (p26)
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(p52) add r38=r37,r33,1 } // (p26)
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{ .mfb; (p27) cmp.ltu.unc p56,p0=r43,r39
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(p21) xmpy.hu f40=f37,f8
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(p28) add r45=r45,r41 };;
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{ .mii; (p25) getf.sig r32=f44 // high
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.pred.rel "mutex",p50,p54
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(p50) add r40=r38,r35 // (p27)
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(p54) add r40=r38,r35,1 } // (p27)
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{ .mfb; (p28) cmp.ltu.unc p60,p0=r45,r41
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(p0) nop.f 0x0
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(p0) nop.b 0x0 }
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{ .mii; (p26) ld8 r42=[r18],8
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(p58) cmp.eq.or p57,p0=-1,r44
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(p58) add r44=1,r44 }
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{ .mfb; (p29) st8 [r14]=r45,8
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{ .mii; (p27) ld8 r44=[r18],8
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(p62) cmp.eq.or p61,p0=-1,r46
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(p62) add r46=1,r46 }
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{ .mfb; (p30) st8 [r14]=r47,8
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(p0) nop.f 0x0
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br.ctop.sptk .L_bn_mul_add_words_ctop};;
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.L_bn_mul_add_words_cend:
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{ .mii; nop.m 0x0
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.pred.rel "mutex",p51,p55
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(p51) add r8=r36,r0
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(p55) add r8=r36,r0,1 }
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.pred.rel "mutex",p53,p57
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(p53) add r8=r38,r0
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(p57) add r8=r38,r0,1 }
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{ .mfb; nop.m 0x0
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nop.f 0x0
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nop.b 0x0 };;
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{ .mii;
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(p59) add r8=1,r8
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(p63) add r8=1,r8
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mov pr=r9,0x1ffff
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mov ar.lc=r3 }
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{ .mfb; rum 1<<5 // clear um.mfh
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