gcm128.c and assembler modules: change argument order for gcm_ghash_4bit.
ghash-x86*.pl: fix performance numbers for Core2, as it turned out previous ones were "tainted" by variable clock frequency.
This commit is contained in:
Andy Polyakov
parent
8decc967dc
commit
4f39edbff1
6 changed files with 38 additions and 47 deletions
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@ -31,10 +31,10 @@ $Thi1="t5";
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$Tlo1="t6";
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$rem="t7"; # $8
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#################
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$Xi="a0"; # $16
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$Xi="a0"; # $16, input argument block
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$Htbl="a1";
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$inp="a2";
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$len="a3";
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$nlo="a4"; # $20
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$nhi="a5";
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$Zhi="t8";
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@ -314,12 +314,6 @@ $code.=<<___;
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.end gcm_gmult_4bit
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___
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# argument block for gcm_ghash_4bit
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$inp="a0"; # $16
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$len="a1";
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$Xi ="a2";
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$Htbl="a3";
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$inhi="s0";
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$inlo="s1";
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@ -142,13 +142,13 @@ gcm_ghash_4bit:
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.prologue
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{ .mmi; .save ar.pfs,prevfs
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alloc prevfs=ar.pfs,4,4,0,8
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$ADDP inp=15,in0 // &inp[15]
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$ADDP inp=15,in2 // &inp[15]
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mov rem_4bitp=ip }
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{ .mmi; $ADDP end=in1,in0 // &inp[len]
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$ADDP Xi=15,in2 // &Xi[15]
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{ .mmi; $ADDP end=in3,in2 // &inp[len]
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$ADDP Xi=15,in0 // &Xi[15]
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.save ar.lc,prevlc
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mov prevlc=ar.lc };;
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{ .mmi; $ADDP Htbl=8,in3 // &Htbl[0].lo
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{ .mmi; $ADDP Htbl=8,in1 // &Htbl[0].lo
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mov mask0xf0=0xf0
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.save pr,prevpr
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mov prevpr=pr }
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@ -54,10 +54,10 @@ $remi="%l5";
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$Htblo="%l6";
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$cnt="%l7";
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$inp="%i0"; # input arguments for gcm_ghash_4bit
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$len="%i1";
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$Xi="%i2";
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$Htbl="%i3";
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$Xi="%i0"; # input argument block
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$Htbl="%i1";
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$inp="%i2";
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$len="%i3";
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$code.=<<___;
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.section ".text",#alloc,#execinstr
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@ -208,8 +208,6 @@ gcm_ghash_4bit:
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.size gcm_ghash_4bit,(.-gcm_ghash_4bit)
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___
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$Xi="%i0"; # input arguments for gcm_gmult_4bit
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$Htbl="%i1";
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undef $inp;
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undef $len;
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@ -23,7 +23,7 @@
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# PIII 63 /77 16 24
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# P4 96 /122 30 84(***)
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# Opteron 50 /71 21 30
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# Core2 63 /102 19 28
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# Core2 54 /68 13 18
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#
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# (*) gcc 3.4.x was observed to generate few percent slower code,
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# which is one of reasons why 2.95.3 results were chosen,
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@ -317,12 +317,12 @@ if ($unroll) {
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&lea ("eax",&DWP(&label("rem_4bit")."-".&label("pic_point"),"eax"));
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&mov ($inp,&wparam(0)); # load in
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&mov ($Zlh,&wparam(1)); # load len
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&mov ($Zhh,&wparam(2)); # load Xi
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&mov ($Htbl,&wparam(3)); # load Htable
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&mov ($Zhh,&wparam(0)); # load Xi
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&mov ($Htbl,&wparam(1)); # load Htable
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&mov ($inp,&wparam(2)); # load in
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&mov ($Zlh,&wparam(3)); # load len
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&add ($Zlh,$inp);
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&mov (&wparam(1),$Zlh); # len to point at the end of input
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&mov (&wparam(3),$Zlh); # len to point at the end of input
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&stack_push(4+1); # +1 for stack alignment
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&mov ($Zll,&DWP(12,$Zhh)); # load Xi[16]
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&mov ($Zhl,&DWP(4,$Zhh));
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@ -344,10 +344,10 @@ if ($unroll) {
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&mmx_loop("esp","eax");
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&lea ($inp,&DWP(16,$inp));
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&cmp ($inp,&wparam(1));
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&cmp ($inp,&wparam(3));
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&jb (&label("mmx_outer_loop"));
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&mov ($inp,&wparam(2)); # load Xi
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&mov ($inp,&wparam(0)); # load Xi
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&emms ();
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&mov (&DWP(12,$inp),$Zll);
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&mov (&DWP(4,$inp),$Zhl);
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@ -359,12 +359,12 @@ if ($unroll) {
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&set_label("x86",16);
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}
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&stack_push(16+4+1); # +1 for 64-bit alignment
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&mov ($inp,&wparam(0)); # load in
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&mov ("ecx",&wparam(1)); # load len
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&mov ($Zll,&wparam(2)); # load Xi
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&mov ($Htbl,&wparam(3)); # load Htable
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&mov ($Zll,&wparam(0)); # load Xi
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&mov ($Htbl,&wparam(1)); # load Htable
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&mov ($inp,&wparam(2)); # load in
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&mov ("ecx",&wparam(3)); # load len
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&add ("ecx",$inp);
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&mov (&wparam(1),"ecx");
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&mov (&wparam(3),"ecx");
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&mov ($Zhh,&DWP(0,$Zll)); # load Xi[16]
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&mov ($Zhl,&DWP(4,$Zll));
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@ -390,14 +390,14 @@ if ($unroll) {
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&call ("_x86_gmult_4bit_inner");
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} else {
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&x86_loop(0);
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&mov ($inp,&wparam(0));
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&mov ($inp,&wparam(2));
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}
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&lea ($inp,&DWP(16,$inp));
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&cmp ($inp,&wparam(1));
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&mov (&wparam(0),$inp) if (!$unroll);
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&cmp ($inp,&wparam(3));
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&mov (&wparam(2),$inp) if (!$unroll);
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&jb (&label("x86_outer_loop"));
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&mov ($inp,&wparam(2)); # load Xi
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&mov ($inp,&wparam(0)); # load Xi
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&mov (&DWP(12,$inp),$Zll);
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&mov (&DWP(8,$inp),$Zlh);
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&mov (&DWP(4,$inp),$Zhl);
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@ -18,7 +18,7 @@
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# gcc 3.4.x assembler
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#
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# Opteron 18.5 10.2 +80%
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# Core2 26.0 16.4 +58%
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# Core2 17.5 11.0 +59%
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$flavour = shift;
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$output = shift;
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@ -41,10 +41,10 @@ $Zhi="%r9";
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$tmp="%r10";
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$rem_4bit = "%r11";
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# per-function register layout
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$Xi="%rdi";
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$Htbl="%rsi";
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# per-function register layout
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$cnt="%rcx";
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$rem="%rdx";
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@ -159,10 +159,8 @@ ___
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# per-function register layout
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$inp="%rdi";
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$len="%rsi";
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$Xi="%rdx";
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$Htbl="%rcx";
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$inp="%rdx";
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$len="%rcx";
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$cnt="%rbp";
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$rem="%r12";
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@ -339,7 +339,7 @@ static const size_t rem_4bit[16] = {
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PACK(0xE100), PACK(0xFD20), PACK(0xD940), PACK(0xC560),
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PACK(0x9180), PACK(0x8DA0), PACK(0xA9C0), PACK(0xB5E0) };
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static void gcm_gmult_4bit(u64 Xi[2], u128 Htable[16])
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static void gcm_gmult_4bit(u64 Xi[2], const u128 Htable[16])
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{
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u128 Z;
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int cnt = 15;
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@ -410,7 +410,8 @@ static void gcm_gmult_4bit(u64 Xi[2], u128 Htable[16])
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* mostly as reference and a placeholder for possible future
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* non-trivial optimization[s]...
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*/
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static void gcm_ghash_4bit(const u8 *inp,size_t len,u64 Xi[2], u128 Htable[16])
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static void gcm_ghash_4bit(u64 Xi[2],const u128 Htable[16],
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const u8 *inp,size_t len)
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{
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u128 Z;
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int cnt;
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@ -479,13 +480,13 @@ static void gcm_ghash_4bit(const u8 *inp,size_t len,u64 Xi[2], u128 Htable[16])
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}
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#endif
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#else
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void gcm_gmult_4bit(u64 Xi[2],u128 Htable[16]);
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void gcm_ghash_4bit(const u8 *inp,size_t len,u64 Xi[2],u128 Htable[16]);
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void gcm_gmult_4bit(u64 Xi[2],const u128 Htable[16]);
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void gcm_ghash_4bit(u64 Xi[2],const u128 Htable[16],const u8 *inp,size_t len);
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#endif
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#define GCM_MUL(ctx,Xi) gcm_gmult_4bit(ctx->Xi.u,ctx->Htable)
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#if defined(GHASH_ASM) || !defined(OPENSSL_SMALL_FOOTPRINT)
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#define GHASH(in,len,ctx) gcm_ghash_4bit(in,len,(ctx)->Xi.u,(ctx)->Htable)
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#define GHASH(in,len,ctx) gcm_ghash_4bit((ctx)->Xi.u,(ctx)->Htable,in,len)
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/* GHASH_CHUNK is "stride parameter" missioned to mitigate cache
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* trashing effect. In other words idea is to hash data while it's
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* still in L1 cache after encryption pass... */
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