Add iOS-specific armv4cpud.S module.
Normally it would be generated from a perlasm module, but doing so would affect existing armv4cpuid.S, which in turn would formally void previously validated platforms. Hense separate module is generated. Reviewed-by: Dr. Stephen Henson <steve@openssl.org>
This commit is contained in:
Andy Polyakov
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874faf2ffb
commit
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1 changed files with 210 additions and 0 deletions
210
crypto/armv4cpuid_ios.S
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210
crypto/armv4cpuid_ios.S
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#include "arm_arch.h"
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.text
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.code 32
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.align 5
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.globl _OPENSSL_atomic_add
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_OPENSSL_atomic_add:
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#if __ARM_ARCH__>=6
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Ladd: ldrex r2,[r0]
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add r3,r2,r1
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strex r2,r3,[r0]
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cmp r2,#0
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bne Ladd
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mov r0,r3
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bx lr
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#else
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stmdb sp!,{r4,r5,r6,lr}
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ldr r2,Lspinlock
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adr r3,Lspinlock
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mov r4,r0
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mov r5,r1
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add r6,r3,r2 @ &spinlock
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b .+8
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Lspin: bl sched_yield
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mov r0,#-1
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swp r0,r0,[r6]
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cmp r0,#0
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bne Lspin
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ldr r2,[r4]
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add r2,r2,r5
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str r2,[r4]
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str r0,[r6] @ release spinlock
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ldmia sp!,{r4,r5,r6,lr}
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tst lr,#1
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moveq pc,lr
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.word 0xe12fff1e @ bx lr
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#endif
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.globl _OPENSSL_cleanse
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_OPENSSL_cleanse:
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eor ip,ip,ip
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cmp r1,#7
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subhs r1,r1,#4
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bhs Lot
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cmp r1,#0
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beq Lcleanse_done
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Little:
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strb ip,[r0],#1
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subs r1,r1,#1
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bhi Little
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b Lcleanse_done
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Lot: tst r0,#3
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beq Laligned
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strb ip,[r0],#1
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sub r1,r1,#1
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b Lot
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Laligned:
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str ip,[r0],#4
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subs r1,r1,#4
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bhs Laligned
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adds r1,r1,#4
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bne Little
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Lcleanse_done:
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#if __ARM_ARCH__>=5
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bx lr
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#else
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tst lr,#1
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moveq pc,lr
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.word 0xe12fff1e @ bx lr
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#endif
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.align 5
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.globl __armv7_neon_probe
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__armv7_neon_probe:
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vorr q0,q0,q0
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bx lr
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.globl __armv7_tick
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__armv7_tick:
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#ifdef __APPLE__
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mrrc p15,0,r0,r1,c14 @ CNTPCT
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#else
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mrrc p15,1,r0,r1,c14 @ CNTVCT
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#endif
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bx lr
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.globl __armv8_aes_probe
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__armv8_aes_probe:
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.byte 0x00,0x03,0xb0,0xf3 @ aese.8 q0,q0
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bx lr
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.globl __armv8_sha1_probe
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__armv8_sha1_probe:
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.byte 0x40,0x0c,0x00,0xf2 @ sha1c.32 q0,q0,q0
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bx lr
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.globl __armv8_sha256_probe
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__armv8_sha256_probe:
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.byte 0x40,0x0c,0x00,0xf3 @ sha256h.32 q0,q0,q0
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bx lr
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.globl __armv8_pmull_probe
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__armv8_pmull_probe:
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.byte 0x00,0x0e,0xa0,0xf2 @ vmull.p64 q0,d0,d0
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bx lr
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.globl _OPENSSL_wipe_cpu
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_OPENSSL_wipe_cpu:
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ldr r0,LOPENSSL_armcap
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adr r1,LOPENSSL_armcap
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ldr r0,[r1,r0]
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#ifdef __APPLE__
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ldr r0,[r0]
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#endif
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eor r2,r2,r2
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eor r3,r3,r3
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eor ip,ip,ip
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tst r0,#1
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beq Lwipe_done
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veor q0, q0, q0
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veor q1, q1, q1
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veor q2, q2, q2
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veor q3, q3, q3
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veor q8, q8, q8
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veor q9, q9, q9
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veor q10, q10, q10
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veor q11, q11, q11
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veor q12, q12, q12
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veor q13, q13, q13
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veor q14, q14, q14
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veor q15, q15, q15
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Lwipe_done:
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mov r0,sp
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#if __ARM_ARCH__>=5
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bx lr
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#else
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tst lr,#1
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moveq pc,lr
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.word 0xe12fff1e @ bx lr
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#endif
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.globl _OPENSSL_instrument_bus
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_OPENSSL_instrument_bus:
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eor r0,r0,r0
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#if __ARM_ARCH__>=5
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bx lr
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#else
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tst lr,#1
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moveq pc,lr
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.word 0xe12fff1e @ bx lr
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#endif
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.globl _OPENSSL_instrument_bus2
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_OPENSSL_instrument_bus2:
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eor r0,r0,r0
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#if __ARM_ARCH__>=5
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bx lr
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#else
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tst lr,#1
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moveq pc,lr
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.word 0xe12fff1e @ bx lr
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#endif
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.align 5
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LOPENSSL_armcap:
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.word OPENSSL_armcap_P-.
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#if __ARM_ARCH__>=6
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.align 5
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#else
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Lspinlock:
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.word atomic_add_spinlock-Lspinlock
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.align 5
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.data
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.align 2
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atomic_add_spinlock:
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.word
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#endif
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.comm _OPENSSL_armcap_P,4
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.non_lazy_symbol_pointer
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OPENSSL_armcap_P:
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.indirect_symbol _OPENSSL_armcap_P
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.long 0
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.private_extern _OPENSSL_armcap_P
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