x86[_64] assembler pack: back-port SHA1 and RC4 from HEAD.
This commit is contained in:
Andy Polyakov
parent
10fd0b7b55
commit
84968e25f3
4 changed files with 2505 additions and 280 deletions
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@ -24,10 +24,38 @@
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# For reference! This code delivers ~80% of rc4-amd64.pl
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# performance on the same Opteron machine.
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# (**) This number requires compressed key schedule set up by
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# private_RC4_set_key [see commentary below for further details].
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# RC4_set_key [see commentary below for further details].
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#
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# <appro@fy.chalmers.se>
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# May 2011
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#
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# Optimize for Core2 and Westmere [and incidentally Opteron]. Current
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# performance in cycles per processed byte (less is better) and
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# improvement relative to previous version of this module is:
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#
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# Pentium 10.2 # original numbers
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# Pentium III 7.8(*)
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# Intel P4 7.5
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#
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# Opteron 6.1/+20% # new MMX numbers
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# Core2 5.3/+67%(**)
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# Westmere 5.1/+94%(**)
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# Sandy Bridge 5.0/+8%
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# Atom 12.6/+6%
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#
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# (*) PIII can actually deliver 6.6 cycles per byte with MMX code,
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# but this specific code performs poorly on Core2. And vice
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# versa, below MMX/SSE code delivering 5.8/7.1 on Core2 performs
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# poorly on PIII, at 8.0/14.5:-( As PIII is not a "hot" CPU
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# [anymore], I chose to discard PIII-specific code path and opt
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# for original IALU-only code, which is why MMX/SSE code path
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# is guarded by SSE2 bit (see below), not MMX/SSE.
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# (**) Performance vs. block size on Core2 and Westmere had a maximum
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# at ... 64 bytes block size. And it was quite a maximum, 40-60%
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# in comparison to largest 8KB block size. Above improvement
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# coefficients are for the largest block size.
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$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
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push(@INC,"${dir}","${dir}../../perlasm");
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require "x86asm.pl";
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@ -62,6 +90,68 @@ sub RC4_loop {
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&$func ($out,&DWP(0,$dat,$ty,4));
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}
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if ($alt=0) {
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# >20% faster on Atom and Sandy Bridge[!], 8% faster on Opteron,
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# but ~40% slower on Core2 and Westmere... Attempt to add movz
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# brings down Opteron by 25%, Atom and Sandy Bridge by 15%, yet
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# on Core2 with movz it's almost 20% slower than below alternative
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# code... Yes, it's a total mess...
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my @XX=($xx,$out);
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$RC4_loop_mmx = sub { # SSE actually...
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my $i=shift;
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my $j=$i<=0?0:$i>>1;
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my $mm=$i<=0?"mm0":"mm".($i&1);
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&add (&LB($yy),&LB($tx));
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&lea (@XX[1],&DWP(1,@XX[0]));
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&pxor ("mm2","mm0") if ($i==0);
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&psllq ("mm1",8) if ($i==0);
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&and (@XX[1],0xff);
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&pxor ("mm0","mm0") if ($i<=0);
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&mov ($ty,&DWP(0,$dat,$yy,4));
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&mov (&DWP(0,$dat,$yy,4),$tx);
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&pxor ("mm1","mm2") if ($i==0);
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&mov (&DWP(0,$dat,$XX[0],4),$ty);
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&add (&LB($ty),&LB($tx));
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&movd (@XX[0],"mm7") if ($i==0);
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&mov ($tx,&DWP(0,$dat,@XX[1],4));
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&pxor ("mm1","mm1") if ($i==1);
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&movq ("mm2",&QWP(0,$inp)) if ($i==1);
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&movq (&QWP(-8,(@XX[0],$inp)),"mm1") if ($i==0);
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&pinsrw ($mm,&DWP(0,$dat,$ty,4),$j);
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push (@XX,shift(@XX)) if ($i>=0);
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}
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} else {
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# Using pinsrw here improves performane on Intel CPUs by 2-3%, but
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# brings down AMD by 7%...
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$RC4_loop_mmx = sub {
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my $i=shift;
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&add (&LB($yy),&LB($tx));
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&psllq ("mm1",8*(($i-1)&7)) if (abs($i)!=1);
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&mov ($ty,&DWP(0,$dat,$yy,4));
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&mov (&DWP(0,$dat,$yy,4),$tx);
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&mov (&DWP(0,$dat,$xx,4),$ty);
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&inc ($xx);
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&add ($ty,$tx);
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&movz ($xx,&LB($xx)); # (*)
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&movz ($ty,&LB($ty)); # (*)
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&pxor ("mm2",$i==1?"mm0":"mm1") if ($i>=0);
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&movq ("mm0",&QWP(0,$inp)) if ($i<=0);
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&movq (&QWP(-8,($out,$inp)),"mm2") if ($i==0);
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&mov ($tx,&DWP(0,$dat,$xx,4));
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&movd ($i>0?"mm1":"mm2",&DWP(0,$dat,$ty,4));
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# (*) This is the key to Core2 and Westmere performance.
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# Whithout movz out-of-order execution logic confuses
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# itself and fails to reorder loads and stores. Problem
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# appears to be fixed in Sandy Bridge...
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}
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}
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&external_label("OPENSSL_ia32cap_P");
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# void RC4(RC4_KEY *key,size_t len,const unsigned char *inp,unsigned char *out);
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&function_begin("RC4");
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&mov ($dat,&wparam(0)); # load key schedule pointer
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@ -94,11 +184,56 @@ sub RC4_loop {
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&and ($ty,-4); # how many 4-byte chunks?
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&jz (&label("loop1"));
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&test ($ty,-8);
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&mov (&wparam(3),$out); # $out as accumulator in these loops
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&jz (&label("go4loop4"));
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&picmeup($out,"OPENSSL_ia32cap_P");
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&bt (&DWP(0,$out),26); # check SSE2 bit [could have been MMX]
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&jnc (&label("go4loop4"));
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&mov ($out,&wparam(3)) if (!$alt);
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&movd ("mm7",&wparam(3)) if ($alt);
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&and ($ty,-8);
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&lea ($ty,&DWP(-8,$inp,$ty));
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&mov (&DWP(-4,$dat),$ty); # save input+(len/8)*8-8
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&$RC4_loop_mmx(-1);
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&jmp(&label("loop_mmx_enter"));
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&set_label("loop_mmx",16);
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&$RC4_loop_mmx(0);
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&set_label("loop_mmx_enter");
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for ($i=1;$i<8;$i++) { &$RC4_loop_mmx($i); }
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&mov ($ty,$yy);
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&xor ($yy,$yy); # this is second key to Core2
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&mov (&LB($yy),&LB($ty)); # and Westmere performance...
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&cmp ($inp,&DWP(-4,$dat));
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&lea ($inp,&DWP(8,$inp));
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&jb (&label("loop_mmx"));
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if ($alt) {
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&movd ($out,"mm7");
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&pxor ("mm2","mm0");
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&psllq ("mm1",8);
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&pxor ("mm1","mm2");
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&movq (&QWP(-8,$out,$inp),"mm1");
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} else {
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&psllq ("mm1",56);
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&pxor ("mm2","mm1");
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&movq (&QWP(-8,$out,$inp),"mm2");
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}
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&emms ();
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&cmp ($inp,&wparam(1)); # compare to input+len
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&je (&label("done"));
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&jmp (&label("loop1"));
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&set_label("go4loop4",16);
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&lea ($ty,&DWP(-4,$inp,$ty));
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&mov (&wparam(2),$ty); # save input+(len/4)*4-4
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&mov (&wparam(3),$out); # $out as accumulator in this loop
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&set_label("loop4",16);
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&set_label("loop4");
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for ($i=0;$i<4;$i++) { RC4_loop($i); }
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&ror ($out,8);
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&xor ($out,&DWP(0,$inp));
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@ -151,7 +286,7 @@ sub RC4_loop {
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&set_label("done");
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&dec (&LB($xx));
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&mov (&BP(-4,$dat),&LB($yy)); # save key->y
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&mov (&DWP(-4,$dat),$yy); # save key->y
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&mov (&BP(-8,$dat),&LB($xx)); # save key->x
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&set_label("abort");
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&function_end("RC4");
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@ -164,10 +299,8 @@ $idi="ebp";
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$ido="ecx";
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$idx="edx";
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&external_label("OPENSSL_ia32cap_P");
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# void private_RC4_set_key(RC4_KEY *key,int len,const unsigned char *data);
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&function_begin("private_RC4_set_key");
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# void RC4_set_key(RC4_KEY *key,int len,const unsigned char *data);
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&function_begin("RC4_set_key");
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&mov ($out,&wparam(0)); # load key
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&mov ($idi,&wparam(1)); # load len
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&mov ($inp,&wparam(2)); # load data
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@ -245,7 +378,7 @@ $idx="edx";
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&xor ("eax","eax");
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&mov (&DWP(-8,$out),"eax"); # key->x=0;
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&mov (&DWP(-4,$out),"eax"); # key->y=0;
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&function_end("private_RC4_set_key");
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&function_end("RC4_set_key");
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# const char *RC4_options(void);
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&function_begin_B("RC4_options");
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@ -254,14 +387,21 @@ $idx="edx";
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&blindpop("eax");
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&lea ("eax",&DWP(&label("opts")."-".&label("pic_point"),"eax"));
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&picmeup("edx","OPENSSL_ia32cap_P");
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&bt (&DWP(0,"edx"),20);
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&jnc (&label("skip"));
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&add ("eax",12);
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&set_label("skip");
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&mov ("edx",&DWP(0,"edx"));
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&bt ("edx",20);
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&jc (&label("1xchar"));
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&bt ("edx",26);
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&jnc (&label("ret"));
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&add ("eax",25);
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&ret ();
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&set_label("1xchar");
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&add ("eax",12);
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&set_label("ret");
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&ret ();
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&set_label("opts",64);
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&asciz ("rc4(4x,int)");
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&asciz ("rc4(1x,char)");
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&asciz ("rc4(8x,mmx)");
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&asciz ("RC4 for x86, CRYPTOGAMS by <appro\@openssl.org>");
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&align (64);
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&function_end_B("RC4_options");
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@ -7,6 +7,8 @@
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# details see http://www.openssl.org/~appro/cryptogams/.
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# ====================================================================
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#
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# July 2004
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#
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# 2.22x RC4 tune-up:-) It should be noted though that my hand [as in
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# "hand-coded assembler"] doesn't stand for the whole improvement
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# coefficient. It turned out that eliminating RC4_CHAR from config
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@ -19,6 +21,8 @@
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# to operate on partial registers, it turned out to be the best bet.
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# At least for AMD... How IA32E would perform remains to be seen...
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# November 2004
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#
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# As was shown by Marc Bevand reordering of couple of load operations
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# results in even higher performance gain of 3.3x:-) At least on
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# Opteron... For reference, 1x in this case is RC4_CHAR C-code
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@ -26,6 +30,8 @@
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# Latter means that if you want to *estimate* what to expect from
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# *your* Opteron, then multiply 54 by 3.3 and clock frequency in GHz.
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# November 2004
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#
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# Intel P4 EM64T core was found to run the AMD64 code really slow...
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# The only way to achieve comparable performance on P4 was to keep
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# RC4_CHAR. Kind of ironic, huh? As it's apparently impossible to
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@ -33,10 +39,14 @@
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# on either AMD and Intel platforms, I implement both cases. See
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# rc4_skey.c for further details...
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# April 2005
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#
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# P4 EM64T core appears to be "allergic" to 64-bit inc/dec. Replacing
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# those with add/sub results in 50% performance improvement of folded
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# loop...
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# May 2005
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#
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# As was shown by Zou Nanhai loop unrolling can improve Intel EM64T
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# performance by >30% [unlike P4 32-bit case that is]. But this is
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# provided that loads are reordered even more aggressively! Both code
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@ -50,6 +60,8 @@
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# is not implemented, then this final RC4_CHAR code-path should be
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# preferred, as it provides better *all-round* performance].
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# March 2007
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#
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# Intel Core2 was observed to perform poorly on both code paths:-( It
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# apparently suffers from some kind of partial register stall, which
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# occurs in 64-bit mode only [as virtually identical 32-bit loop was
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@ -58,6 +70,37 @@
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# fit for Core2 and therefore the code was modified to skip cloop8 on
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# this CPU.
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# May 2010
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#
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# Intel Westmere was observed to perform suboptimally. Adding yet
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# another movzb to cloop1 improved performance by almost 50%! Core2
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# performance is improved too, but nominally...
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# May 2011
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#
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# The only code path that was not modified is P4-specific one. Non-P4
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# Intel code path optimization is heavily based on submission by Maxim
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# Perminov, Maxim Locktyukhin and Jim Guilford of Intel. I've used
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# some of the ideas even in attempt to optmize the original RC4_INT
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# code path... Current performance in cycles per processed byte (less
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# is better) and improvement coefficients relative to previous
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# version of this module are:
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#
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# Opteron 5.3/+0%(*)
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# P4 6.5
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# Core2 6.2/+15%(**)
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# Westmere 4.2/+60%
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# Sandy Bridge 4.2/+120%
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# Atom 9.3/+80%
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#
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# (*) But corresponding loop has less instructions, which should have
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# positive effect on upcoming Bulldozer, which has one less ALU.
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# For reference, Intel code runs at 6.8 cpb rate on Opteron.
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# (**) Note that Core2 result is ~15% lower than corresponding result
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# for 32-bit code, meaning that it's possible to improve it,
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# but more than likely at the cost of the others (see rc4-586.pl
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# to get the idea)...
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$flavour = shift;
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$output = shift;
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if ($flavour =~ /\./) { $output = $flavour; undef $flavour; }
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@ -76,13 +119,10 @@ $len="%rsi"; # arg2
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$inp="%rdx"; # arg3
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$out="%rcx"; # arg4
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@XX=("%r8","%r10");
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@TX=("%r9","%r11");
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$YY="%r12";
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$TY="%r13";
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{
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$code=<<___;
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.text
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.extern OPENSSL_ia32cap_P
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.globl RC4
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.type RC4,\@function,4
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@ -95,48 +135,173 @@ RC4: or $len,$len
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push %r12
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push %r13
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.Lprologue:
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mov $len,%r11
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mov $inp,%r12
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mov $out,%r13
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___
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my $len="%r11"; # reassign input arguments
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my $inp="%r12";
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my $out="%r13";
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add \$8,$dat
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movl -8($dat),$XX[0]#d
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movl -4($dat),$YY#d
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my @XX=("%r10","%rsi");
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my @TX=("%rax","%rbx");
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my $YY="%rcx";
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my $TY="%rdx";
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$code.=<<___;
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xor $XX[0],$XX[0]
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xor $YY,$YY
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lea 8($dat),$dat
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mov -8($dat),$XX[0]#b
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mov -4($dat),$YY#b
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cmpl \$-1,256($dat)
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je .LRC4_CHAR
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mov OPENSSL_ia32cap_P(%rip),%r8d
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xor $TX[1],$TX[1]
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inc $XX[0]#b
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sub $XX[0],$TX[1]
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sub $inp,$out
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movl ($dat,$XX[0],4),$TX[0]#d
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test \$-8,$len
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test \$-16,$len
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jz .Lloop1
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jmp .Lloop8
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bt \$30,%r8d # Intel CPU?
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jc .Lintel
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and \$7,$TX[1]
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lea 1($XX[0]),$XX[1]
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jz .Loop8
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sub $TX[1],$len
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.Loop8_warmup:
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add $TX[0]#b,$YY#b
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movl ($dat,$YY,4),$TY#d
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movl $TX[0]#d,($dat,$YY,4)
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movl $TY#d,($dat,$XX[0],4)
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add $TY#b,$TX[0]#b
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inc $XX[0]#b
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movl ($dat,$TX[0],4),$TY#d
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movl ($dat,$XX[0],4),$TX[0]#d
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xorb ($inp),$TY#b
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movb $TY#b,($out,$inp)
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lea 1($inp),$inp
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dec $TX[1]
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jnz .Loop8_warmup
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lea 1($XX[0]),$XX[1]
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jmp .Loop8
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.align 16
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.Lloop8:
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.Loop8:
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___
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for ($i=0;$i<8;$i++) {
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$code.=<<___ if ($i==7);
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add \$8,$XX[1]#b
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___
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$code.=<<___;
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add $TX[0]#b,$YY#b
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mov $XX[0],$XX[1]
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movl ($dat,$YY,4),$TY#d
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ror \$8,%rax # ror is redundant when $i=0
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inc $XX[1]#b
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movl ($dat,$XX[1],4),$TX[1]#d
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cmp $XX[1],$YY
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movl $TX[0]#d,($dat,$YY,4)
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cmove $TX[0],$TX[1]
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movl $TY#d,($dat,$XX[0],4)
|
||||
movl `4*($i==7?-1:$i)`($dat,$XX[1],4),$TX[1]#d
|
||||
ror \$8,%r8 # ror is redundant when $i=0
|
||||
movl $TY#d,4*$i($dat,$XX[0],4)
|
||||
add $TX[0]#b,$TY#b
|
||||
movb ($dat,$TY,4),%al
|
||||
movb ($dat,$TY,4),%r8b
|
||||
___
|
||||
push(@TX,shift(@TX)); push(@XX,shift(@XX)); # "rotate" registers
|
||||
push(@TX,shift(@TX)); #push(@XX,shift(@XX)); # "rotate" registers
|
||||
}
|
||||
$code.=<<___;
|
||||
ror \$8,%rax
|
||||
add \$8,$XX[0]#b
|
||||
ror \$8,%r8
|
||||
sub \$8,$len
|
||||
|
||||
xor ($inp),%rax
|
||||
add \$8,$inp
|
||||
mov %rax,($out)
|
||||
add \$8,$out
|
||||
xor ($inp),%r8
|
||||
mov %r8,($out,$inp)
|
||||
lea 8($inp),$inp
|
||||
|
||||
test \$-8,$len
|
||||
jnz .Lloop8
|
||||
jnz .Loop8
|
||||
cmp \$0,$len
|
||||
jne .Lloop1
|
||||
jmp .Lexit
|
||||
|
||||
.align 16
|
||||
.Lintel:
|
||||
test \$-32,$len
|
||||
jz .Lloop1
|
||||
and \$15,$TX[1]
|
||||
jz .Loop16_is_hot
|
||||
sub $TX[1],$len
|
||||
.Loop16_warmup:
|
||||
add $TX[0]#b,$YY#b
|
||||
movl ($dat,$YY,4),$TY#d
|
||||
movl $TX[0]#d,($dat,$YY,4)
|
||||
movl $TY#d,($dat,$XX[0],4)
|
||||
add $TY#b,$TX[0]#b
|
||||
inc $XX[0]#b
|
||||
movl ($dat,$TX[0],4),$TY#d
|
||||
movl ($dat,$XX[0],4),$TX[0]#d
|
||||
xorb ($inp),$TY#b
|
||||
movb $TY#b,($out,$inp)
|
||||
lea 1($inp),$inp
|
||||
dec $TX[1]
|
||||
jnz .Loop16_warmup
|
||||
|
||||
mov $YY,$TX[1]
|
||||
xor $YY,$YY
|
||||
mov $TX[1]#b,$YY#b
|
||||
|
||||
.Loop16_is_hot:
|
||||
lea ($dat,$XX[0],4),$XX[1]
|
||||
___
|
||||
sub RC4_loop {
|
||||
my $i=shift;
|
||||
my $j=$i<0?0:$i;
|
||||
my $xmm="%xmm".($j&1);
|
||||
|
||||
$code.=" add \$16,$XX[0]#b\n" if ($i==15);
|
||||
$code.=" movdqu ($inp),%xmm2\n" if ($i==15);
|
||||
$code.=" add $TX[0]#b,$YY#b\n" if ($i<=0);
|
||||
$code.=" movl ($dat,$YY,4),$TY#d\n";
|
||||
$code.=" pxor %xmm0,%xmm2\n" if ($i==0);
|
||||
$code.=" psllq \$8,%xmm1\n" if ($i==0);
|
||||
$code.=" pxor $xmm,$xmm\n" if ($i<=1);
|
||||
$code.=" movl $TX[0]#d,($dat,$YY,4)\n";
|
||||
$code.=" add $TY#b,$TX[0]#b\n";
|
||||
$code.=" movl `4*($j+1)`($XX[1]),$TX[1]#d\n" if ($i<15);
|
||||
$code.=" movz $TX[0]#b,$TX[0]#d\n";
|
||||
$code.=" movl $TY#d,4*$j($XX[1])\n";
|
||||
$code.=" pxor %xmm1,%xmm2\n" if ($i==0);
|
||||
$code.=" lea ($dat,$XX[0],4),$XX[1]\n" if ($i==15);
|
||||
$code.=" add $TX[1]#b,$YY#b\n" if ($i<15);
|
||||
$code.=" pinsrw \$`($j>>1)&7`,($dat,$TX[0],4),$xmm\n";
|
||||
$code.=" movdqu %xmm2,($out,$inp)\n" if ($i==0);
|
||||
$code.=" lea 16($inp),$inp\n" if ($i==0);
|
||||
$code.=" movl ($XX[1]),$TX[1]#d\n" if ($i==15);
|
||||
}
|
||||
RC4_loop(-1);
|
||||
$code.=<<___;
|
||||
jmp .Loop16_enter
|
||||
.align 16
|
||||
.Loop16:
|
||||
___
|
||||
|
||||
for ($i=0;$i<16;$i++) {
|
||||
$code.=".Loop16_enter:\n" if ($i==1);
|
||||
RC4_loop($i);
|
||||
push(@TX,shift(@TX)); # "rotate" registers
|
||||
}
|
||||
$code.=<<___;
|
||||
mov $YY,$TX[1]
|
||||
xor $YY,$YY # keyword to partial register
|
||||
sub \$16,$len
|
||||
mov $TX[1]#b,$YY#b
|
||||
test \$-16,$len
|
||||
jnz .Loop16
|
||||
|
||||
psllq \$8,%xmm1
|
||||
pxor %xmm0,%xmm2
|
||||
pxor %xmm1,%xmm2
|
||||
movdqu %xmm2,($out,$inp)
|
||||
lea 16($inp),$inp
|
||||
|
||||
cmp \$0,$len
|
||||
jne .Lloop1
|
||||
jmp .Lexit
|
||||
|
|
@ -152,9 +317,8 @@ $code.=<<___;
|
|||
movl ($dat,$TX[0],4),$TY#d
|
||||
movl ($dat,$XX[0],4),$TX[0]#d
|
||||
xorb ($inp),$TY#b
|
||||
inc $inp
|
||||
movb $TY#b,($out)
|
||||
inc $out
|
||||
movb $TY#b,($out,$inp)
|
||||
lea 1($inp),$inp
|
||||
dec $len
|
||||
jnz .Lloop1
|
||||
jmp .Lexit
|
||||
|
|
@ -165,13 +329,11 @@ $code.=<<___;
|
|||
movzb ($dat,$XX[0]),$TX[0]#d
|
||||
test \$-8,$len
|
||||
jz .Lcloop1
|
||||
cmpl \$0,260($dat)
|
||||
jnz .Lcloop1
|
||||
jmp .Lcloop8
|
||||
.align 16
|
||||
.Lcloop8:
|
||||
mov ($inp),%eax
|
||||
mov 4($inp),%ebx
|
||||
mov ($inp),%r8d
|
||||
mov 4($inp),%r9d
|
||||
___
|
||||
# unroll 2x4-wise, because 64-bit rotates kill Intel P4...
|
||||
for ($i=0;$i<4;$i++) {
|
||||
|
|
@ -188,8 +350,8 @@ $code.=<<___;
|
|||
mov $TX[0],$TX[1]
|
||||
.Lcmov$i:
|
||||
add $TX[0]#b,$TY#b
|
||||
xor ($dat,$TY),%al
|
||||
ror \$8,%eax
|
||||
xor ($dat,$TY),%r8b
|
||||
ror \$8,%r8d
|
||||
___
|
||||
push(@TX,shift(@TX)); push(@XX,shift(@XX)); # "rotate" registers
|
||||
}
|
||||
|
|
@ -207,16 +369,16 @@ $code.=<<___;
|
|||
mov $TX[0],$TX[1]
|
||||
.Lcmov$i:
|
||||
add $TX[0]#b,$TY#b
|
||||
xor ($dat,$TY),%bl
|
||||
ror \$8,%ebx
|
||||
xor ($dat,$TY),%r9b
|
||||
ror \$8,%r9d
|
||||
___
|
||||
push(@TX,shift(@TX)); push(@XX,shift(@XX)); # "rotate" registers
|
||||
}
|
||||
$code.=<<___;
|
||||
lea -8($len),$len
|
||||
mov %eax,($out)
|
||||
mov %r8d,($out)
|
||||
lea 8($inp),$inp
|
||||
mov %ebx,4($out)
|
||||
mov %r9d,4($out)
|
||||
lea 8($out),$out
|
||||
|
||||
test \$-8,$len
|
||||
|
|
@ -229,6 +391,7 @@ $code.=<<___;
|
|||
.align 16
|
||||
.Lcloop1:
|
||||
add $TX[0]#b,$YY#b
|
||||
movzb $YY#b,$YY#d
|
||||
movzb ($dat,$YY),$TY#d
|
||||
movb $TX[0]#b,($dat,$YY)
|
||||
movb $TY#b,($dat,$XX[0])
|
||||
|
|
@ -260,16 +423,16 @@ $code.=<<___;
|
|||
ret
|
||||
.size RC4,.-RC4
|
||||
___
|
||||
}
|
||||
|
||||
$idx="%r8";
|
||||
$ido="%r9";
|
||||
|
||||
$code.=<<___;
|
||||
.extern OPENSSL_ia32cap_P
|
||||
.globl private_RC4_set_key
|
||||
.type private_RC4_set_key,\@function,3
|
||||
.globl RC4_set_key
|
||||
.type RC4_set_key,\@function,3
|
||||
.align 16
|
||||
private_RC4_set_key:
|
||||
RC4_set_key:
|
||||
lea 8($dat),$dat
|
||||
lea ($inp,$len),$inp
|
||||
neg $len
|
||||
|
|
@ -280,12 +443,9 @@ private_RC4_set_key:
|
|||
xor %r11,%r11
|
||||
|
||||
mov OPENSSL_ia32cap_P(%rip),$idx#d
|
||||
bt \$20,$idx#d
|
||||
jnc .Lw1stloop
|
||||
bt \$30,$idx#d
|
||||
setc $ido#b
|
||||
mov $ido#d,260($dat)
|
||||
jmp .Lc1stloop
|
||||
bt \$20,$idx#d # RC4_CHAR?
|
||||
jc .Lc1stloop
|
||||
jmp .Lw1stloop
|
||||
|
||||
.align 16
|
||||
.Lw1stloop:
|
||||
|
|
@ -339,7 +499,7 @@ private_RC4_set_key:
|
|||
mov %eax,-8($dat)
|
||||
mov %eax,-4($dat)
|
||||
ret
|
||||
.size private_RC4_set_key,.-private_RC4_set_key
|
||||
.size RC4_set_key,.-RC4_set_key
|
||||
|
||||
.globl RC4_options
|
||||
.type RC4_options,\@abi-omnipotent
|
||||
|
|
@ -348,18 +508,20 @@ RC4_options:
|
|||
lea .Lopts(%rip),%rax
|
||||
mov OPENSSL_ia32cap_P(%rip),%edx
|
||||
bt \$20,%edx
|
||||
jnc .Ldone
|
||||
add \$12,%rax
|
||||
jc .L8xchar
|
||||
bt \$30,%edx
|
||||
jnc .Ldone
|
||||
add \$13,%rax
|
||||
add \$25,%rax
|
||||
ret
|
||||
.L8xchar:
|
||||
add \$12,%rax
|
||||
.Ldone:
|
||||
ret
|
||||
.align 64
|
||||
.Lopts:
|
||||
.asciz "rc4(8x,int)"
|
||||
.asciz "rc4(8x,char)"
|
||||
.asciz "rc4(1x,char)"
|
||||
.asciz "rc4(16x,int)"
|
||||
.asciz "RC4 for x86_64, CRYPTOGAMS by <appro\@openssl.org>"
|
||||
.align 64
|
||||
.size RC4_options,.-RC4_options
|
||||
|
|
@ -497,7 +659,17 @@ key_se_handler:
|
|||
___
|
||||
}
|
||||
|
||||
$code =~ s/#([bwd])/$1/gm;
|
||||
sub reg_part {
|
||||
my ($reg,$conv)=@_;
|
||||
if ($reg =~ /%r[0-9]+/) { $reg .= $conv; }
|
||||
elsif ($conv eq "b") { $reg =~ s/%[er]([^x]+)x?/%$1l/; }
|
||||
elsif ($conv eq "w") { $reg =~ s/%[er](.+)/%$1/; }
|
||||
elsif ($conv eq "d") { $reg =~ s/%[er](.+)/%e$1/; }
|
||||
return $reg;
|
||||
}
|
||||
|
||||
$code =~ s/(%[a-z0-9]+)#([bwd])/reg_part($1,$2)/gem;
|
||||
$code =~ s/\`([^\`]*)\`/eval $1/gem;
|
||||
|
||||
print $code;
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
Loading…
Reference in a new issue