parisc-mont.pl: PA-RISC 2.0 code path optimization based on intruction-
level profiling data resulted in almost 50% performance improvement. PA-RISC 1.1 is also reordered in same manner, mostly to be consistent, as no gain was observed, not on PA-7100LC.
This commit is contained in:
Andy Polyakov
parent
cab6de03a2
commit
964ed94649
1 changed files with 139 additions and 132 deletions
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@ -20,39 +20,45 @@
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# for PA-RISC 1.1, but the "baseline" is far from optimal. The actual
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# improvement coefficient was never collected on PA-7100LC, or any
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# other 1.1 CPU, because I don't have access to such machine with
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# vendor compiler. But to give you a taste, PA-RISC 1.1 code-path
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# vendor compiler. But to give you a taste, PA-RISC 1.1 code path
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# reportedly outperformed code generated by cc +DA1.1 +O3 by factor
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# of ~5x on PA-8600.
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#
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# On PA-RISC 2.0 it has to compete with pa-risc2[W].s, which is
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# reportedly ~2x faster than vendor compiler generated code [see
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# commentary in assembler source code]. Here comes a catch. Execution
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# core of this implementation is actually 32-bit one, in the sense
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# that it expects arrays of 32-bit BN_LONG values as input. But
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# pa-risc2[W].s operates on arrays of 64-bit BN_LONGs... How do they
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# interoperate then? Simple. This module picks halves of 64-bit
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# values in reverse order. But can it compete with "pure" 64-bit code
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# such as pa-risc2[W].s then? Well, the thing is that 32x32=64-bit
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# multiplication is the best even PA-RISC 2.0 can do, i.e. there is
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# no "wider" multiplication like on most other 64-bit platforms.
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# This means that even being effectively 32-bit, this implementation
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# performs the same computational task in same amount of arithmetic
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# operations, most notably multiplications. It requires more memory
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# references, most notably to tp[num], but this doesn't seem to
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# exhaust memory port capacity. In other words this implementation,
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# or more specifically its PA-RISC 2.0 code-path, competes with
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# pa-risc2W.s on virtually same terms.
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# reportedly ~2x faster than vendor compiler generated code [according
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# to comment in pa-risc2[W].s]. Here comes a catch. Execution core of
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# this implementation is actually 32-bit one, in the sense that it
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# operates on 32-bit values. But pa-risc2[W].s operates on arrays of
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# 64-bit BN_LONGs... How do they interoperate then? No problem. This
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# module picks halves of 64-bit values in reverse order and pretends
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# they were 32-bit BN_LONGs. But can 32-bit core compete with "pure"
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# 64-bit code such as pa-risc2[W].s then? Well, the thing is that
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# 32x32=64-bit multiplication is the best even PA-RISC 2.0 can do,
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# i.e. there is no "wider" multiplication like on most other 64-bit
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# platforms. This means that even being effectively 32-bit, this
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# implementation performs "64-bit" computational task in same amount
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# of arithmetic operations, most notably multiplications. It requires
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# more memory references, most notably to tp[num], but this doesn't
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# seem to exhaust memory port capacity. And indeed, dedicated PA-RISC
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# 2.0 code path, provides virtually same performance as pa-risc2[W].s:
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# it's ~10% better for shortest key length and ~10% worse for longest
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# one.
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#
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# In case it wasn't clear. The module has two distinct code-paths:
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# In case it wasn't clear. The module has two distinct code paths:
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# PA-RISC 1.1 and PA-RISC 2.0 ones. Latter features carry-free 64-bit
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# additions and 64-bit integer loads, not to mention specific
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# instruction scheduling. In 32-bit build module imposes couple of
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# limitations: vector lengths has to be even and vector addresses has
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# to be 64-bit aligned. Normally neither is a problem: most common
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# key lengths are even and vectors are commonly malloc-ed, which
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# ensures 64-bit alignment.
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# instruction scheduling. In 64-bit build naturally only 2.0 code path
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# is assembled. In 32-bit application context both code paths are
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# assembled, PA-RISC 2.0 CPU is detected at run-time and proper path
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# is taken automatically. Also, in 32-bit build the module imposes
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# couple of limitations: vector lengths has to be even and vector
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# addresses has to be 64-bit aligned. Normally neither is a problem:
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# most common key lengths are even and vectors are commonly malloc-ed,
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# which ensures alignment.
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#
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# Special thanks to polarhome.com for providing HP-UX account.
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# Special thanks to polarhome.com for providing HP-UX account on
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# PA-RISC 1.1 machine, and to correspondent who chose to remain
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# anonymous for testing the code on PA-RISC 2.0 machine.
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$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
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@ -134,7 +140,7 @@ $code=<<___;
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.SUBSPA \$CODE\$,QUAD=0,ALIGN=8,ACCESS=0x2C,CODE_ONLY
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.EXPORT bn_mul_mont,ENTRY,ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
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.ALIGN 16
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.ALIGN 64
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bn_mul_mont
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.PROC
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.CALLINFO FRAME=`$FRAME-8*$SIZE_T`,NO_CALLS,SAVE_RP,SAVE_SP,ENTRY_GR=6
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@ -168,6 +174,7 @@ $code.=<<___ if ($BN_SZ==4);
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b L\$abort
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nop
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nop ; alignment
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nop
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fldws 0($n0),${fn0}
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fldws,ma 4($bp),${fbi} ; bp[0]
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@ -219,58 +226,58 @@ $code.=<<___ if ($BN_SZ==4);
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nop
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___
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$code.=<<___; # PA-RISC 2.0 code-path
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xmpyu ${fai}L,${fbi},${fab0} ; ap[j]*bp[0]
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xmpyu ${fni}L,${fm0}R,${fnm0} ; np[j]*m
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ldd -16($xfer),$ab0
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ldd -8($xfer),$nm0
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fstds ${fab0},-16($xfer)
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extrd,u $ab0,31,32,$hi0
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extrd,u $ab0,63,32,$ab0
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ldd -8($xfer),$nm0
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fstds ${fnm0},-8($xfer)
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ldo 8($idx),$idx ; j++++
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addl $ab0,$nm0,$nm0 ; low part is discarded
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extrd,u $nm0,31,32,$hi1
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ldd 0($xfer),$ab1
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L\$1st
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xmpyu ${fai}L,${fbi},${fab0} ; ap[j]*bp[0]
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xmpyu ${fni}L,${fm0}R,${fnm0} ; np[j]*m
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ldd 8($xfer),$nm1
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fstds ${fab0},-16($xfer)
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xmpyu ${fai}R,${fbi},${fab1} ; ap[j+1]*bp[0]
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xmpyu ${fni}R,${fm0}R,${fnm1} ; np[j+1]*m
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fstds ${fnm0},-8($xfer)
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addl $hi0,$ab1,$ab1
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ldd 0($xfer),$ab1
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fstds ${fab1},0($xfer)
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addl $hi0,$ab1,$ab1
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extrd,u $ab1,31,32,$hi0
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ldd 8($xfer),$nm1
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fstds ${fnm1},8($xfer)
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extrd,u $ab1,63,32,$ab1
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addl $hi1,$nm1,$nm1
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ldd -16($xfer),$ab0
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flddx $idx($ap),${fai} ; ap[j,j+1]
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flddx $idx($np),${fni} ; np[j,j+1]
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addl $ab1,$nm1,$nm1
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ldd -8($xfer),$nm0
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extrd,u $nm1,31,32,$hi1
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flddx $idx($ap),${fai} ; ap[j,j+1]
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xmpyu ${fai}L,${fbi},${fab0} ; ap[j]*bp[0]
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xmpyu ${fni}L,${fm0}R,${fnm0} ; np[j]*m
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ldd -16($xfer),$ab0
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fstds ${fab0},-16($xfer)
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addl $hi0,$ab0,$ab0
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flddx $idx($np),${fni} ; np[j,j+1]
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extrd,u $ab0,31,32,$hi0
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stw $nm1,-4($tp) ; tp[j-1]
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ldd -8($xfer),$nm0
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fstds ${fnm0},-8($xfer)
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extrd,u $ab0,63,32,$ab0
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addl $hi1,$nm0,$nm0
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stw $nm1,-4($tp) ; tp[j-1]
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addl $ab0,$nm0,$nm0
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ldd 0($xfer),$ab1
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stw,ma $nm0,8($tp) ; tp[j-1]
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addib,<> 8,$idx,L\$1st ; j++++
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extrd,u $nm0,31,32,$hi1
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xmpyu ${fai}L,${fbi},${fab0} ; ap[j]*bp[0]
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xmpyu ${fni}L,${fm0}R,${fnm0} ; np[j]*m
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ldd 8($xfer),$nm1
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fstds ${fab0},-16($xfer)
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xmpyu ${fai}R,${fbi},${fab1} ; ap[j]*bp[0]
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xmpyu ${fni}R,${fm0}R,${fnm1} ; np[j]*m
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fstds ${fnm0},-8($xfer)
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addl $hi0,$ab1,$ab1
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ldd 0($xfer),$ab1
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fstds ${fab1},0($xfer)
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addl $hi0,$ab1,$ab1
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extrd,u $ab1,31,32,$hi0
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ldd 8($xfer),$nm1
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fstds ${fnm1},8($xfer)
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extrd,u $ab1,63,32,$ab1
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addl $hi1,$nm1,$nm1
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@ -340,6 +347,8 @@ L\$outer
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ldd -8($xfer),$nm0
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ldw 0($xfer),$hi0 ; high part
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xmpyu ${fai}L,${fbi},${fab0} ; ap[j]*bp[i]
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xmpyu ${fni}L,${fm0}R,${fnm0} ; np[j]*m
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extrd,u $ab0,31,32,$ti0 ; carry bit
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extrd,u $ab0,63,32,$ab0
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fstds ${fab1},0($xfer)
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@ -348,61 +357,59 @@ L\$outer
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addl $ab0,$nm0,$nm0 ; low part is discarded
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ldw 0($tp),$ti1 ; tp[1]
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extrd,u $nm0,31,32,$hi1
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ldd 0($xfer),$ab1
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fstds ${fab0},-16($xfer)
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fstds ${fnm0},-8($xfer)
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L\$inner
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xmpyu ${fai}L,${fbi},${fab0} ; ap[j]*bp[i]
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xmpyu ${fni}L,${fm0}R,${fnm0} ; np[j]*m
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ldd 8($xfer),$nm1
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fstds ${fab0},-16($xfer)
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xmpyu ${fai}R,${fbi},${fab1} ; ap[j+1]*bp[i]
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xmpyu ${fni}R,${fm0}R,${fnm1} ; np[j+1]*m
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fstds ${fnm0},-8($xfer)
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ldw 4($tp),$ti0 ; tp[j]
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addl $hi0,$ab1,$ab1
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ldd 0($xfer),$ab1
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fstds ${fab1},0($xfer)
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addl $hi0,$ti1,$ti1
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addl $ti1,$ab1,$ab1
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extrd,u $ab1,31,32,$hi0
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ldd 8($xfer),$nm1
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fstds ${fnm1},8($xfer)
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extrd,u $ab1,31,32,$hi0
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extrd,u $ab1,63,32,$ab1
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addl $hi1,$nm1,$nm1
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ldd -16($xfer),$ab0
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addl $ab1,$nm1,$nm1
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ldd -8($xfer),$nm0
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extrd,u $nm1,31,32,$hi1
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flddx $idx($ap),${fai} ; ap[j,j+1]
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addl $hi0,$ab0,$ab0
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flddx $idx($np),${fni} ; np[j,j+1]
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addl $ti0,$ab0,$ab0
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addl $hi1,$nm1,$nm1
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addl $ab1,$nm1,$nm1
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ldw 4($tp),$ti0 ; tp[j]
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stw $nm1,-4($tp) ; tp[j-1]
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xmpyu ${fai}L,${fbi},${fab0} ; ap[j]*bp[i]
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xmpyu ${fni}L,${fm0}R,${fnm0} ; np[j]*m
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ldd -16($xfer),$ab0
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fstds ${fab0},-16($xfer)
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addl $hi0,$ti0,$ti0
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addl $ti0,$ab0,$ab0
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ldd -8($xfer),$nm0
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fstds ${fnm0},-8($xfer)
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extrd,u $ab0,31,32,$hi0
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extrd,u $nm1,31,32,$hi1
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ldw 8($tp),$ti1 ; tp[j]
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extrd,u $ab0,63,32,$ab0
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addl $hi1,$nm0,$nm0
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addl $ab0,$nm0,$nm0
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ldd 0($xfer),$ab1
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stw,ma $nm0,8($tp) ; tp[j-1]
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addib,<> 8,$idx,L\$inner ; j++++
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extrd,u $nm0,31,32,$hi1
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xmpyu ${fai}L,${fbi},${fab0} ; ap[j]*bp[i]
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xmpyu ${fni}L,${fm0}R,${fnm0} ; np[j]*m
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ldd 8($xfer),$nm1
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fstds ${fab0},-16($xfer)
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xmpyu ${fai}R,${fbi},${fab1} ; ap[j]*bp[i]
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xmpyu ${fni}R,${fm0}R,${fnm1} ; np[j]*m
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fstds ${fnm0},-8($xfer)
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ldw 4($tp),$ti0 ; tp[j]
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addl $hi0,$ab1,$ab1
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ldd 0($xfer),$ab1
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fstds ${fab1},0($xfer)
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addl $hi0,$ti1,$ti1
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addl $ti1,$ab1,$ab1
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extrd,u $ab1,31,32,$hi0
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ldd 8($xfer),$nm1
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fstds ${fnm1},8($xfer)
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extrd,u $ab1,31,32,$hi0
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extrd,u $ab1,63,32,$ab1
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ldw 4($tp),$ti0 ; tp[j]
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addl $hi1,$nm1,$nm1
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ldd -16($xfer),$ab0
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addl $ab1,$nm1,$nm1
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ldd -16($xfer),$ab0
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ldd -8($xfer),$nm0
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extrd,u $nm1,31,32,$hi1
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@ -549,46 +556,50 @@ $code.=<<___;
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.ALIGN 8
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L\$parisc11
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ldw -16($xfer),$hi0
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xmpyu ${fai}L,${fbi},${fab0} ; ap[j]*bp[0]
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xmpyu ${fni}L,${fm0}R,${fnm0} ; np[j]*m
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ldw -12($xfer),$ablo
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ldw -8($xfer),$nmhi0
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ldw -16($xfer),$hi0
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ldw -4($xfer),$nmlo0
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ldw -8($xfer),$nmhi0
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fstds ${fab0},-16($xfer)
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fstds ${fnm0},-8($xfer)
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ldo 8($idx),$idx ; j++++
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add $ablo,$nmlo0,$nmlo0 ; discarded
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addc %r0,$nmhi0,$hi1
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ldw 0($xfer),$abhi
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ldw 4($xfer),$ablo
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ldw 0($xfer),$abhi
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nop
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L\$1st_pa11
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xmpyu ${fai}L,${fbi},${fab0} ; ap[j]*bp[0]
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ldw 8($xfer),$nmhi1
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xmpyu ${fni}L,${fm0}R,${fnm0} ; np[j]*m
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ldw 12($xfer),$nmlo1
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xmpyu ${fai}R,${fbi},${fab1} ; ap[j+1]*bp[0]
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fstds ${fab0},-16($xfer)
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xmpyu ${fni}R,${fm0}R,${fnm1} ; np[j+1]*m
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fstds ${fnm0},-8($xfer)
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add $hi0,$ablo,$ablo
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fstds ${fab1},0($xfer)
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addc %r0,$abhi,$hi0
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fstds ${fnm1},8($xfer)
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add $ablo,$nmlo1,$nmlo1
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ldw -16($xfer),$abhi
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addc %r0,$nmhi1,$nmhi1
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ldw -12($xfer),$ablo
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add $hi1,$nmlo1,$nmlo1
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ldw -8($xfer),$nmhi0
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addc %r0,$nmhi1,$hi1
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ldw -4($xfer),$nmlo0
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add $hi0,$ablo,$ablo
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flddx $idx($ap),${fai} ; ap[j,j+1]
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addc %r0,$abhi,$hi0
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xmpyu ${fni}R,${fm0}R,${fnm1} ; np[j+1]*m
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flddx $idx($np),${fni} ; np[j,j+1]
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add $ablo,$nmlo0,$nmlo0
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add $hi0,$ablo,$ablo
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ldw 12($xfer),$nmlo1
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addc %r0,$abhi,$hi0
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ldw 8($xfer),$nmhi1
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add $ablo,$nmlo1,$nmlo1
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fstds ${fab1},0($xfer)
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addc %r0,$nmhi1,$nmhi1
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fstds ${fnm1},8($xfer)
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add $hi1,$nmlo1,$nmlo1
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ldw -12($xfer),$ablo
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addc %r0,$nmhi1,$hi1
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ldw -16($xfer),$abhi
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xmpyu ${fai}L,${fbi},${fab0} ; ap[j]*bp[0]
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ldw -4($xfer),$nmlo0
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xmpyu ${fni}L,${fm0}R,${fnm0} ; np[j]*m
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ldw -8($xfer),$nmhi0
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add $hi0,$ablo,$ablo
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stw $nmlo1,-4($tp) ; tp[j-1]
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addc %r0,$abhi,$hi0
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fstds ${fab0},-16($xfer)
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add $ablo,$nmlo0,$nmlo0
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fstds ${fnm0},-8($xfer)
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addc %r0,$nmhi0,$nmhi0
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ldw 0($xfer),$abhi
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add $hi1,$nmlo0,$nmlo0
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@ -597,14 +608,10 @@ L\$1st_pa11
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addib,<> 8,$idx,L\$1st_pa11 ; j++++
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addc %r0,$nmhi0,$hi1
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xmpyu ${fai}L,${fbi},${fab0} ; ap[j]*bp[0]
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ldw 8($xfer),$nmhi1
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xmpyu ${fni}L,${fm0}R,${fnm0} ; np[j]*m
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ldw 12($xfer),$nmlo1
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xmpyu ${fai}R,${fbi},${fab1} ; ap[j]*bp[0]
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xmpyu ${fni}R,${fm0}R,${fnm1} ; np[j]*m
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fstds ${fab0},-16($xfer)
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fstds ${fnm0},-8($xfer)
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add $hi0,$ablo,$ablo
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fstds ${fab1},0($xfer)
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addc %r0,$abhi,$hi0
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||||
|
|
@ -677,65 +684,65 @@ L\$outer_pa11
|
|||
ldw -4($xfer),$nmlo0
|
||||
ldw 0($xfer),$hi0 ; high part
|
||||
|
||||
xmpyu ${fai}L,${fbi},${fab0} ; ap[j]*bp[i]
|
||||
xmpyu ${fni}L,${fm0}R,${fnm0} ; np[j]*m
|
||||
fstds ${fab1},0($xfer)
|
||||
addl $abhi,$hi0,$hi0 ; account carry bit
|
||||
fstds ${fnm1},8($xfer)
|
||||
add $ablo,$nmlo0,$nmlo0 ; discarded
|
||||
ldw 0($tp),$ti1 ; tp[1]
|
||||
addc %r0,$nmhi0,$hi1
|
||||
ldw 0($xfer),$abhi
|
||||
fstds ${fab0},-16($xfer)
|
||||
fstds ${fnm0},-8($xfer)
|
||||
ldw 4($xfer),$ablo
|
||||
ldw 0($xfer),$abhi
|
||||
|
||||
L\$inner_pa11
|
||||
xmpyu ${fai}L,${fbi},${fab0} ; ap[j]*bp[i]
|
||||
ldw 8($xfer),$nmhi1
|
||||
xmpyu ${fni}L,${fm0}R,${fnm0} ; np[j]*m
|
||||
ldw 12($xfer),$nmlo1
|
||||
xmpyu ${fai}R,${fbi},${fab1} ; ap[j+1]*bp[i]
|
||||
fstds ${fab0},-16($xfer)
|
||||
flddx $idx($ap),${fai} ; ap[j,j+1]
|
||||
xmpyu ${fni}R,${fm0}R,${fnm1} ; np[j+1]*m
|
||||
fstds ${fnm0},-8($xfer)
|
||||
flddx $idx($np),${fni} ; np[j,j+1]
|
||||
add $hi0,$ablo,$ablo
|
||||
ldw 4($tp),$ti0 ; tp[j]
|
||||
addc %r0,$abhi,$abhi
|
||||
fstds ${fab1},0($xfer)
|
||||
ldw 12($xfer),$nmlo1
|
||||
add $ti1,$ablo,$ablo
|
||||
fstds ${fnm1},8($xfer)
|
||||
ldw 8($xfer),$nmhi1
|
||||
addc %r0,$abhi,$hi0
|
||||
ldw -16($xfer),$abhi
|
||||
fstds ${fab1},0($xfer)
|
||||
add $ablo,$nmlo1,$nmlo1
|
||||
ldw -12($xfer),$ablo
|
||||
fstds ${fnm1},8($xfer)
|
||||
addc %r0,$nmhi1,$nmhi1
|
||||
ldw -8($xfer),$nmhi0
|
||||
ldw -12($xfer),$ablo
|
||||
add $hi1,$nmlo1,$nmlo1
|
||||
ldw -4($xfer),$nmlo0
|
||||
ldw -16($xfer),$abhi
|
||||
addc %r0,$nmhi1,$hi1
|
||||
|
||||
flddx $idx($ap),${fai} ; ap[j,j+1]
|
||||
addl,nuv $hi0,$ablo,$ablo
|
||||
addi 1,$abhi,$abhi
|
||||
flddx $idx($np),${fni} ; np[j,j+1]
|
||||
add $ti0,$ablo,$ablo
|
||||
stw $nmlo1,-4($tp) ; tp[j-1]
|
||||
addc %r0,$abhi,$hi0
|
||||
xmpyu ${fai}L,${fbi},${fab0} ; ap[j]*bp[i]
|
||||
ldw 8($tp),$ti1 ; tp[j]
|
||||
addl,nuv $ablo,$nmlo0,$nmlo0
|
||||
addi 1,$nmhi0,$nmhi0
|
||||
xmpyu ${fni}L,${fm0}R,${fnm0} ; np[j]*m
|
||||
ldw -4($xfer),$nmlo0
|
||||
add $hi0,$ablo,$ablo
|
||||
ldw -8($xfer),$nmhi0
|
||||
addc %r0,$abhi,$abhi
|
||||
stw $nmlo1,-4($tp) ; tp[j-1]
|
||||
add $ti0,$ablo,$ablo
|
||||
fstds ${fab0},-16($xfer)
|
||||
addc %r0,$abhi,$hi0
|
||||
fstds ${fnm0},-8($xfer)
|
||||
add $ablo,$nmlo0,$nmlo0
|
||||
ldw 4($xfer),$ablo
|
||||
addc %r0,$nmhi0,$nmhi0
|
||||
ldw 0($xfer),$abhi
|
||||
add $hi1,$nmlo0,$nmlo0
|
||||
ldw 4($xfer),$ablo
|
||||
stws,ma $nmlo0,8($tp) ; tp[j-1]
|
||||
addib,<> 8,$idx,L\$inner_pa11 ; j++++
|
||||
addc %r0,$nmhi0,$hi1
|
||||
|
||||
xmpyu ${fai}L,${fbi},${fab0} ; ap[j]*bp[i]
|
||||
ldw 8($xfer),$nmhi1
|
||||
xmpyu ${fni}L,${fm0}R,${fnm0} ; np[j]*m
|
||||
ldw 12($xfer),$nmlo1
|
||||
xmpyu ${fai}R,${fbi},${fab1} ; ap[j]*bp[i]
|
||||
fstds ${fab0},-16($xfer)
|
||||
ldw 12($xfer),$nmlo1
|
||||
xmpyu ${fni}R,${fm0}R,${fnm1} ; np[j]*m
|
||||
fstds ${fnm0},-8($xfer)
|
||||
ldw 8($xfer),$nmhi1
|
||||
add $hi0,$ablo,$ablo
|
||||
ldw 4($tp),$ti0 ; tp[j]
|
||||
addc %r0,$abhi,$abhi
|
||||
|
|
|
|||
Loading…
Reference in a new issue