MIPS assembly pack: jumbo update from HEAD.
This commit is contained in:
Andy Polyakov
parent
9a7f80c869
commit
988037fe18
7 changed files with 1100 additions and 278 deletions
4
CHANGES
4
CHANGES
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@ -4,6 +4,10 @@
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Changes between 1.0.1 and 1.0.2 [xx XXX xxxx]
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*) MIPS assembly pack updates: support for MIPS32r2 and SmartMIPS ASE,
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platform support for Linux and Android.
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[Andy Polyakov]
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*) Call OCSP Stapling callback after ciphersuite has been chosen, so
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the right response is stapled. Also change current certificate to
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the certificate actually sent.
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14
Configure
14
Configure
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@ -348,6 +348,13 @@ my %table=(
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# It's believed that majority of ARM toolchains predefine appropriate -march.
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# If you compiler does not, do complement config command line with one!
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"linux-armv4", "gcc:-DTERMIO -O3 -Wall::-D_REENTRANT::-ldl:BN_LLONG RC4_CHAR RC4_CHUNK DES_INT DES_UNROLL BF_PTR:${armv4_asm}:dlfcn:linux-shared:-fPIC::.so.\$(SHLIB_MAJOR).\$(SHLIB_MINOR)",
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# Configure script adds minimally required -march for assembly support,
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# if no -march was specified at command line. mips32 and mips64 below
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# refer to contemporary MIPS Architecture specifications, MIPS32 and
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# MIPS64, rather than to kernel bitness.
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"linux-mips32", "gcc:-mabi=32 -DTERMIO -O3 -Wall::-D_REENTRANT::-ldl:BN_LLONG RC4_CHAR RC4_CHUNK DES_INT DES_UNROLL BF_PTR:${mips32_asm}:o32:dlfcn:linux-shared:-fPIC::.so.\$(SHLIB_MAJOR).\$(SHLIB_MINOR)",
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"linux-mips64", "gcc:-mabi=n32 -DTERMIO -O3 -Wall::-D_REENTRANT::-ldl:SIXTY_FOUR_BIT RC4_CHAR RC4_CHUNK DES_INT DES_UNROLL BF_PTR:${mips64_asm}:n32:dlfcn:linux-shared:-fPIC:-mabi=n32:.so.\$(SHLIB_MAJOR).\$(SHLIB_MINOR):::32",
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"linux64-mips64", "gcc:-mabi=64 -DTERMIO -O3 -Wall::-D_REENTRANT::-ldl:SIXTY_FOUR_BIT_LONG RC4_CHAR RC4_CHUNK DES_INT DES_UNROLL BF_PTR:${mips64_asm}:64:dlfcn:linux-shared:-fPIC:-mabi=64:.so.\$(SHLIB_MAJOR).\$(SHLIB_MINOR):::64",
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#### IA-32 targets...
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"linux-ia32-icc", "icc:-DL_ENDIAN -DTERMIO -O2 -no_cpprt::-D_REENTRANT::-ldl:BN_LLONG ${x86_gcc_des} ${x86_gcc_opts}:${x86_elf_asm}:dlfcn:linux-shared:-KPIC::.so.\$(SHLIB_MAJOR).\$(SHLIB_MINOR)",
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"linux-elf", "gcc:-DL_ENDIAN -DTERMIO -O3 -fomit-frame-pointer -Wall::-D_REENTRANT::-ldl:BN_LLONG ${x86_gcc_des} ${x86_gcc_opts}:${x86_elf_asm}:dlfcn:linux-shared:-fPIC::.so.\$(SHLIB_MAJOR).\$(SHLIB_MINOR)",
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@ -406,6 +413,7 @@ my %table=(
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"android","gcc:-mandroid -I\$(ANDROID_DEV)/include -B\$(ANDROID_DEV)/lib -O3 -fomit-frame-pointer -Wall::-D_REENTRANT::-ldl:BN_LLONG RC4_CHAR RC4_CHUNK DES_INT DES_UNROLL BF_PTR:${no_asm}:dlfcn:linux-shared:-fPIC::.so.\$(SHLIB_MAJOR).\$(SHLIB_MINOR)",
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"android-x86","gcc:-mandroid -I\$(ANDROID_DEV)/include -B\$(ANDROID_DEV)/lib -O3 -fomit-frame-pointer -Wall::-D_REENTRANT::-ldl:BN_LLONG ${x86_gcc_des} ${x86_gcc_opts}:".eval{my $asm=${x86_elf_asm};$asm=~s/:elf/:android/;$asm}.":dlfcn:linux-shared:-fPIC::.so.\$(SHLIB_MAJOR).\$(SHLIB_MINOR)",
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"android-armv7","gcc:-march=armv7-a -mandroid -I\$(ANDROID_DEV)/include -B\$(ANDROID_DEV)/lib -O3 -fomit-frame-pointer -Wall::-D_REENTRANT::-ldl:BN_LLONG RC4_CHAR RC4_CHUNK DES_INT DES_UNROLL BF_PTR:${armv4_asm}:dlfcn:linux-shared:-fPIC::.so.\$(SHLIB_MAJOR).\$(SHLIB_MINOR)",
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"android-mips","gcc:-mandroid -I\$(ANDROID_DEV)/include -B\$(ANDROID_DEV)/lib -O3 -Wall::-D_REENTRANT::-ldl:BN_LLONG RC4_CHAR RC4_CHUNK DES_INT DES_UNROLL BF_PTR:${mips32_asm}:o32:dlfcn:linux-shared:-fPIC::.so.\$(SHLIB_MAJOR).\$(SHLIB_MINOR)",
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#### *BSD [do see comment about ${BSDthreads} above!]
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"BSD-generic32","gcc:-DTERMIOS -O3 -fomit-frame-pointer -Wall::${BSDthreads}:::BN_LLONG RC2_CHAR RC4_INDEX DES_INT DES_UNROLL:${no_asm}:dlfcn:bsd-gcc-shared:-fPIC::.so.\$(SHLIB_MAJOR).\$(SHLIB_MINOR)",
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@ -1202,6 +1210,12 @@ if ($target =~ /^mingw/ && `$cc --target-help 2>&1` !~ m/\-mno\-cygwin/m)
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$shared_ldflag =~ s/\-mno\-cygwin\s*//;
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}
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if ($target =~ /linux.*\-mips/ && !$no_asm && $flags !~ /\-m(ips|arch=)/) {
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# minimally required architecture flags for assembly modules
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$cflags="-mips2 $cflags" if ($target =~ /mips32/);
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$cflags="-mips3 $cflags" if ($target =~ /mips64/);
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}
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my $no_shared_warn=0;
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my $no_user_cflags=0;
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132
TABLE
132
TABLE
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@ -1089,6 +1089,39 @@ $ranlib =
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$arflags =
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$multilib =
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*** android-mips
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$cc = gcc
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$cflags = -mandroid -I$(ANDROID_DEV)/include -B$(ANDROID_DEV)/lib -O3 -Wall
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$unistd =
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$thread_cflag = -D_REENTRANT
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$sys_id =
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$lflags = -ldl
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$bn_ops = BN_LLONG RC4_CHAR RC4_CHUNK DES_INT DES_UNROLL BF_PTR
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$cpuid_obj =
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$bn_obj = bn-mips.o mips-mont.o
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$des_obj =
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$aes_obj = aes_cbc.o aes-mips.o
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$bf_obj =
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$md5_obj =
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$sha1_obj = sha1-mips.o sha256-mips.o
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$cast_obj =
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$rc4_obj =
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$rmd160_obj =
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$rc5_obj =
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$wp_obj =
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$cmll_obj =
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$modes_obj =
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$engines_obj =
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$perlasm_scheme = o32
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$dso_scheme = dlfcn
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$shared_target= linux-shared
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$shared_cflag = -fPIC
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$shared_ldflag =
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$shared_extension = .so.$(SHLIB_MAJOR).$(SHLIB_MINOR)
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$ranlib =
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$arflags =
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$multilib =
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*** android-x86
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$cc = gcc
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$cflags = -mandroid -I$(ANDROID_DEV)/include -B$(ANDROID_DEV)/lib -O3 -fomit-frame-pointer -Wall
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@ -4191,6 +4224,72 @@ $ranlib =
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$arflags =
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$multilib =
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*** linux-mips32
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$cc = gcc
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$cflags = -mabi=32 -DTERMIO -O3 -Wall
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$unistd =
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$thread_cflag = -D_REENTRANT
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$sys_id =
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$lflags = -ldl
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$bn_ops = BN_LLONG RC4_CHAR RC4_CHUNK DES_INT DES_UNROLL BF_PTR
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$cpuid_obj =
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$bn_obj = bn-mips.o mips-mont.o
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$des_obj =
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$aes_obj = aes_cbc.o aes-mips.o
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$bf_obj =
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$md5_obj =
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$sha1_obj = sha1-mips.o sha256-mips.o
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$cast_obj =
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$rc4_obj =
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$rmd160_obj =
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$rc5_obj =
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$wp_obj =
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$cmll_obj =
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$modes_obj =
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$engines_obj =
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$perlasm_scheme = o32
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$dso_scheme = dlfcn
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$shared_target= linux-shared
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$shared_cflag = -fPIC
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$shared_ldflag =
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$shared_extension = .so.$(SHLIB_MAJOR).$(SHLIB_MINOR)
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$ranlib =
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$arflags =
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$multilib =
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*** linux-mips64
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$cc = gcc
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$cflags = -mabi=n32 -DTERMIO -O3 -Wall
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$unistd =
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$thread_cflag = -D_REENTRANT
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$sys_id =
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$lflags = -ldl
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$bn_ops = SIXTY_FOUR_BIT RC4_CHAR RC4_CHUNK DES_INT DES_UNROLL BF_PTR
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$cpuid_obj =
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$bn_obj = bn-mips.o mips-mont.o
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$des_obj =
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$aes_obj = aes_cbc.o aes-mips.o
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$bf_obj =
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$md5_obj =
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$sha1_obj = sha1-mips.o sha256-mips.o sha512-mips.o
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$cast_obj =
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$rc4_obj =
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$rmd160_obj =
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$rc5_obj =
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$wp_obj =
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$cmll_obj =
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$modes_obj =
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$engines_obj =
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$perlasm_scheme = n32
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$dso_scheme = dlfcn
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$shared_target= linux-shared
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$shared_cflag = -fPIC
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$shared_ldflag = -mabi=n32
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$shared_extension = .so.$(SHLIB_MAJOR).$(SHLIB_MINOR)
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$ranlib =
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$arflags =
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$multilib = 32
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*** linux-ppc
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$cc = gcc
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$cflags = -DB_ENDIAN -DTERMIO -O3 -Wall
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@ -4422,6 +4521,39 @@ $ranlib =
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$arflags =
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$multilib = /highgprs
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*** linux64-mips64
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$cc = gcc
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$cflags = -mabi=64 -DTERMIO -O3 -Wall
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$unistd =
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$thread_cflag = -D_REENTRANT
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$sys_id =
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$lflags = -ldl
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$bn_ops = SIXTY_FOUR_BIT_LONG RC4_CHAR RC4_CHUNK DES_INT DES_UNROLL BF_PTR
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$cpuid_obj =
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$bn_obj = bn-mips.o mips-mont.o
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$des_obj =
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$aes_obj = aes_cbc.o aes-mips.o
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$bf_obj =
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$md5_obj =
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$sha1_obj = sha1-mips.o sha256-mips.o sha512-mips.o
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$cast_obj =
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$rc4_obj =
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$rmd160_obj =
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$rc5_obj =
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$wp_obj =
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$cmll_obj =
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$modes_obj =
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$engines_obj =
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$perlasm_scheme = 64
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$dso_scheme = dlfcn
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$shared_target= linux-shared
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$shared_cflag = -fPIC
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$shared_ldflag = -mabi=64
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$shared_extension = .so.$(SHLIB_MAJOR).$(SHLIB_MINOR)
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$ranlib =
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$arflags =
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$multilib = 64
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*** linux64-s390x
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$cc = gcc
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$cflags = -m64 -DB_ENDIAN -DTERMIO -O3 -Wall
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10
config
10
config
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@ -596,6 +596,16 @@ case "$GUESSOS" in
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OUT="linux-ppc"
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;;
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ppc-*-linux2) OUT="linux-ppc" ;;
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mips64*-*-linux2)
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echo "WARNING! If you wish to build 64-bit library, then you have to"
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echo " invoke './Configure linux64-mips64' *manually*."
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if [ "$TEST" = "false" -a -t 1 ]; then
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echo " You have about 5 seconds to press Ctrl-C to abort."
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(trap "stty `stty -g`" 2 0; stty -icanon min 0 time 50; read waste) <&1
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fi
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OUT="linux-mips64"
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;;
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mips*-*-linux2) OUT="linux-mips32" ;;
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ppc60x-*-vxworks*) OUT="vxworks-ppc60x" ;;
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ppcgen-*-vxworks*) OUT="vxworks-ppcgen" ;;
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pentium-*-vxworks*) OUT="vxworks-pentium" ;;
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File diff suppressed because it is too large
Load diff
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@ -15,6 +15,10 @@
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# compatible subroutine. There is room for minor optimization on
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# little-endian platforms...
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# September 2012.
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#
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# Add MIPS32r2 code (>25% less instructions).
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######################################################################
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# There is a number of MIPS ABI in use, O32 and N32/64 are most
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# widely used. Then there is a new contender: NUBI. It appears that if
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@ -95,6 +99,10 @@ sub BODY_00_14 {
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my ($i,$a,$b,$c,$d,$e)=@_;
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my $j=$i+1;
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$code.=<<___ if (!$big_endian);
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#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
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wsbh @X[$i],@X[$i] # byte swap($i)
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rotr @X[$i],@X[$i],16
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#else
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srl $t0,@X[$i],24 # byte swap($i)
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srl $t1,@X[$i],8
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andi $t2,@X[$i],0xFF00
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@ -104,8 +112,22 @@ $code.=<<___ if (!$big_endian);
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or @X[$i],$t0
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or $t1,$t2
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or @X[$i],$t1
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#endif
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___
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$code.=<<___;
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#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
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addu $e,$K # $i
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xor $t0,$c,$d
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rotr $t1,$a,27
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lwl @X[$j],$j*4+$MSB($inp)
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and $t0,$b
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addu $e,$t1
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lwr @X[$j],$j*4+$LSB($inp)
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xor $t0,$d
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addu $e,@X[$i]
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rotr $b,$b,2
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addu $e,$t0
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#else
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lwl @X[$j],$j*4+$MSB($inp)
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sll $t0,$a,5 # $i
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addu $e,$K
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@ -121,6 +143,7 @@ $code.=<<___;
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addu $e,@X[$i]
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or $b,$t2
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addu $e,$t0
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#endif
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___
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}
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@ -129,6 +152,10 @@ my ($i,$a,$b,$c,$d,$e)=@_;
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my $j=$i+1;
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$code.=<<___ if (!$big_endian && $i==15);
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#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
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wsbh @X[$i],@X[$i] # byte swap($i)
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rotr @X[$i],@X[$i],16
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#else
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srl $t0,@X[$i],24 # byte swap($i)
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srl $t1,@X[$i],8
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andi $t2,@X[$i],0xFF00
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@ -138,8 +165,24 @@ $code.=<<___ if (!$big_endian && $i==15);
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or @X[$i],$t0
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or @X[$i],$t1
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or @X[$i],$t2
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#endif
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___
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$code.=<<___;
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#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
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addu $e,$K # $i
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xor @X[$j%16],@X[($j+2)%16]
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xor $t0,$c,$d
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rotr $t1,$a,27
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xor @X[$j%16],@X[($j+8)%16]
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and $t0,$b
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addu $e,$t1
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xor @X[$j%16],@X[($j+13)%16]
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xor $t0,$d
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addu $e,@X[$i%16]
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rotr @X[$j%16],@X[$j%16],31
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rotr $b,$b,2
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addu $e,$t0
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#else
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xor @X[$j%16],@X[($j+2)%16]
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sll $t0,$a,5 # $i
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addu $e,$K
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@ -159,6 +202,7 @@ $code.=<<___;
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addu $e,@X[$i%16]
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or $b,$t2
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addu $e,$t0
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#endif
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___
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}
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@ -166,6 +210,20 @@ sub BODY_20_39 {
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my ($i,$a,$b,$c,$d,$e)=@_;
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my $j=$i+1;
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$code.=<<___ if ($i<79);
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#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
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xor @X[$j%16],@X[($j+2)%16]
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addu $e,$K # $i
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rotr $t1,$a,27
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xor @X[$j%16],@X[($j+8)%16]
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xor $t0,$c,$d
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addu $e,$t1
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xor @X[$j%16],@X[($j+13)%16]
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xor $t0,$b
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addu $e,@X[$i%16]
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rotr @X[$j%16],@X[$j%16],31
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rotr $b,$b,2
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addu $e,$t0
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#else
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xor @X[$j%16],@X[($j+2)%16]
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sll $t0,$a,5 # $i
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addu $e,$K
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@ -184,8 +242,24 @@ $code.=<<___ if ($i<79);
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or @X[$j%16],$t1
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or $b,$t2
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addu $e,$t0
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#endif
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___
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$code.=<<___ if ($i==79);
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#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
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lw @X[0],0($ctx)
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addu $e,$K # $i
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lw @X[1],4($ctx)
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rotr $t1,$a,27
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lw @X[2],8($ctx)
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xor $t0,$c,$d
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addu $e,$t1
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lw @X[3],12($ctx)
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xor $t0,$b
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addu $e,@X[$i%16]
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lw @X[4],16($ctx)
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rotr $b,$b,2
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addu $e,$t0
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#else
|
||||
lw @X[0],0($ctx)
|
||||
sll $t0,$a,5 # $i
|
||||
addu $e,$K
|
||||
|
|
@ -203,6 +277,7 @@ $code.=<<___ if ($i==79);
|
|||
addu $e,@X[$i%16]
|
||||
or $b,$t2
|
||||
addu $e,$t0
|
||||
#endif
|
||||
___
|
||||
}
|
||||
|
||||
|
|
@ -210,6 +285,22 @@ sub BODY_40_59 {
|
|||
my ($i,$a,$b,$c,$d,$e)=@_;
|
||||
my $j=$i+1;
|
||||
$code.=<<___ if ($i<79);
|
||||
#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
|
||||
addu $e,$K # $i
|
||||
and $t0,$c,$d
|
||||
xor @X[$j%16],@X[($j+2)%16]
|
||||
rotr $t1,$a,27
|
||||
addu $e,$t0
|
||||
xor @X[$j%16],@X[($j+8)%16]
|
||||
xor $t0,$c,$d
|
||||
addu $e,$t1
|
||||
xor @X[$j%16],@X[($j+13)%16]
|
||||
and $t0,$b
|
||||
addu $e,@X[$i%16]
|
||||
rotr @X[$j%16],@X[$j%16],31
|
||||
rotr $b,$b,2
|
||||
addu $e,$t0
|
||||
#else
|
||||
xor @X[$j%16],@X[($j+2)%16]
|
||||
sll $t0,$a,5 # $i
|
||||
addu $e,$K
|
||||
|
|
@ -230,6 +321,7 @@ $code.=<<___ if ($i<79);
|
|||
addu $e,@X[$i%16]
|
||||
or $b,$t2
|
||||
addu $e,$t0
|
||||
#endif
|
||||
___
|
||||
}
|
||||
|
||||
|
|
@ -241,6 +333,10 @@ $code=<<___;
|
|||
# include <openssl/fipssyms.h>
|
||||
#endif
|
||||
|
||||
#if defined(__mips_smartmips) && !defined(_MIPS_ARCH_MIPS32R2)
|
||||
#define _MIPS_ARCH_MIPS32R2
|
||||
#endif
|
||||
|
||||
.text
|
||||
|
||||
.set noat
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#!/usr/bin/env perl
|
||||
|
||||
# ====================================================================
|
||||
# Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
|
||||
# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
|
||||
# project. The module is, however, dual licensed under OpenSSL and
|
||||
# CRYPTOGAMS licenses depending on where you obtain it. For further
|
||||
# details see http://www.openssl.org/~appro/cryptogams/.
|
||||
|
|
@ -17,6 +17,10 @@
|
|||
# ~17%, but it comes for free, because it's same instruction sequence.
|
||||
# Improvement coefficients are for aligned input.
|
||||
|
||||
# September 2012.
|
||||
#
|
||||
# Add MIPS[32|64]R2 code (>25% less instructions).
|
||||
|
||||
######################################################################
|
||||
# There is a number of MIPS ABI in use, O32 and N32/64 are most
|
||||
# widely used. Then there is a new contender: NUBI. It appears that if
|
||||
|
|
@ -45,7 +49,7 @@
|
|||
# ($s0,$s1,$s2,$s3,$s4,$s5,$s6,$s7)=map("\$$_",(16..23));
|
||||
# ($gp,$sp,$fp,$ra)=map("\$$_",(28..31));
|
||||
#
|
||||
$flavour = shift; # supported flavours are o32,n32,64,nubi32,nubi64
|
||||
$flavour = shift || "o32"; # supported flavours are o32,n32,64,nubi32,nubi64
|
||||
|
||||
if ($flavour =~ /64|n32/i) {
|
||||
$PTR_ADD="dadd"; # incidentally works even on n32
|
||||
|
|
@ -83,6 +87,7 @@ if ($output =~ /512/) {
|
|||
$SLL="dsll"; # shift left logical
|
||||
$SRL="dsrl"; # shift right logical
|
||||
$ADDU="daddu";
|
||||
$ROTR="drotr";
|
||||
@Sigma0=(28,34,39);
|
||||
@Sigma1=(14,18,41);
|
||||
@sigma0=( 7, 1, 8); # right shift first
|
||||
|
|
@ -97,6 +102,7 @@ if ($output =~ /512/) {
|
|||
$SLL="sll"; # shift left logical
|
||||
$SRL="srl"; # shift right logical
|
||||
$ADDU="addu";
|
||||
$ROTR="rotr";
|
||||
@Sigma0=( 2,13,22);
|
||||
@Sigma1=( 6,11,25);
|
||||
@sigma0=( 3, 7,18); # right shift first
|
||||
|
|
@ -124,6 +130,10 @@ $code.=<<___ if ($i<15);
|
|||
${LD}r @X[1],`($i+1)*$SZ+$LSB`($inp)
|
||||
___
|
||||
$code.=<<___ if (!$big_endian && $i<16 && $SZ==4);
|
||||
#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
|
||||
wsbh @X[0],@X[0] # byte swap($i)
|
||||
rotr @X[0],@X[0],16
|
||||
#else
|
||||
srl $tmp0,@X[0],24 # byte swap($i)
|
||||
srl $tmp1,@X[0],8
|
||||
andi $tmp2,@X[0],0xFF00
|
||||
|
|
@ -133,8 +143,13 @@ $code.=<<___ if (!$big_endian && $i<16 && $SZ==4);
|
|||
or @X[0],$tmp0
|
||||
or $tmp1,$tmp2
|
||||
or @X[0],$tmp1
|
||||
#endif
|
||||
___
|
||||
$code.=<<___ if (!$big_endian && $i<16 && $SZ==8);
|
||||
#if defined(_MIPS_ARCH_MIPS64R2)
|
||||
dsbh @X[0],@X[0] # byte swap($i)
|
||||
dshd @X[0],@X[0]
|
||||
#else
|
||||
ori $tmp0,$zero,0xFF
|
||||
dsll $tmp2,$tmp0,32
|
||||
or $tmp0,$tmp2 # 0x000000FF000000FF
|
||||
|
|
@ -153,8 +168,31 @@ $code.=<<___ if (!$big_endian && $i<16 && $SZ==8);
|
|||
dsrl $tmp1,@X[0],32
|
||||
dsll @X[0],32
|
||||
or @X[0],$tmp1
|
||||
#endif
|
||||
___
|
||||
$code.=<<___;
|
||||
#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
|
||||
xor $tmp2,$f,$g # $i
|
||||
$ROTR $tmp0,$e,@Sigma1[0]
|
||||
$ADDU $T1,$X[0],$h
|
||||
$ROTR $tmp1,$e,@Sigma1[1]
|
||||
and $tmp2,$e
|
||||
$ROTR $h,$e,@Sigma1[2]
|
||||
xor $tmp0,$tmp1
|
||||
$ROTR $tmp1,$a,@Sigma0[0]
|
||||
xor $tmp2,$g # Ch(e,f,g)
|
||||
xor $tmp0,$h # Sigma1(e)
|
||||
|
||||
$ROTR $h,$a,@Sigma0[1]
|
||||
$ADDU $T1,$tmp2
|
||||
$LD $tmp2,`$i*$SZ`($Ktbl) # K[$i]
|
||||
xor $h,$tmp1
|
||||
$ROTR $tmp1,$a,@Sigma0[2]
|
||||
$ADDU $T1,$tmp0
|
||||
and $tmp0,$b,$c
|
||||
xor $h,$tmp1 # Sigma0(a)
|
||||
xor $tmp1,$b,$c
|
||||
#else
|
||||
$ADDU $T1,$X[0],$h # $i
|
||||
$SRL $h,$e,@Sigma1[0]
|
||||
xor $tmp2,$f,$g
|
||||
|
|
@ -184,16 +222,15 @@ $code.=<<___;
|
|||
xor $h,$tmp1
|
||||
$SLL $tmp1,$a,`$SZ*8-@Sigma0[0]`
|
||||
xor $h,$tmp0
|
||||
$ST @X[0],`($i%16)*$SZ`($sp) # offload to ring buffer
|
||||
and $tmp0,$b,$c
|
||||
xor $h,$tmp1 # Sigma0(a)
|
||||
|
||||
or $tmp0,$a,$b
|
||||
and $tmp1,$a,$b
|
||||
and $tmp0,$c
|
||||
or $tmp1,$tmp0 # Maj(a,b,c)
|
||||
xor $tmp1,$b,$c
|
||||
#endif
|
||||
$ST @X[0],`($i%16)*$SZ`($sp) # offload to ring buffer
|
||||
$ADDU $h,$tmp0
|
||||
and $tmp1,$a
|
||||
$ADDU $T1,$tmp2 # +=K[$i]
|
||||
$ADDU $h,$tmp1
|
||||
|
||||
$ADDU $h,$tmp1 # +=Maj(a,b,c)
|
||||
$ADDU $d,$T1
|
||||
$ADDU $h,$T1
|
||||
___
|
||||
|
|
@ -207,6 +244,20 @@ my $i=@_[0];
|
|||
my ($tmp0,$tmp1,$tmp2,$tmp3)=(@X[4],@X[5],@X[6],@X[7]);
|
||||
|
||||
$code.=<<___;
|
||||
#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
|
||||
$SRL $tmp2,@X[1],@sigma0[0] # Xupdate($i)
|
||||
$ROTR $tmp0,@X[1],@sigma0[1]
|
||||
$ADDU @X[0],@X[9] # +=X[i+9]
|
||||
xor $tmp2,$tmp0
|
||||
$ROTR $tmp0,@X[1],@sigma0[2]
|
||||
|
||||
$SRL $tmp3,@X[14],@sigma1[0]
|
||||
$ROTR $tmp1,@X[14],@sigma1[1]
|
||||
xor $tmp2,$tmp0 # sigma0(X[i+1])
|
||||
$ROTR $tmp0,@X[14],@sigma1[2]
|
||||
xor $tmp3,$tmp1
|
||||
$ADDU @X[0],$tmp2
|
||||
#else
|
||||
$SRL $tmp2,@X[1],@sigma0[0] # Xupdate($i)
|
||||
$ADDU @X[0],@X[9] # +=X[i+9]
|
||||
$SLL $tmp1,@X[1],`$SZ*8-@sigma0[2]`
|
||||
|
|
@ -227,7 +278,7 @@ $code.=<<___;
|
|||
xor $tmp3,$tmp0
|
||||
$SRL $tmp0,@X[14],@sigma1[2]
|
||||
xor $tmp3,$tmp1
|
||||
|
||||
#endif
|
||||
xor $tmp3,$tmp0 # sigma1(X[i+14])
|
||||
$ADDU @X[0],$tmp3
|
||||
___
|
||||
|
|
@ -242,9 +293,13 @@ $code.=<<___;
|
|||
# include <openssl/fipssyms.h>
|
||||
#endif
|
||||
|
||||
#if defined(__mips_smartmips) && !defined(_MIPS_ARCH_MIPS32R2)
|
||||
#define _MIPS_ARCH_MIPS32R2
|
||||
#endif
|
||||
|
||||
.text
|
||||
.set noat
|
||||
#if !defined(__vxworks) || defined(__pic__)
|
||||
#if !defined(__mips_eabi) && (!defined(__vxworks) || defined(__pic__))
|
||||
.option pic2
|
||||
#endif
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue