Extend OPENSSL_ia32cap_P (backport from HEAD).
This commit is contained in:
Andy Polyakov
parent
c340c7a88c
commit
d75e384ff8
3 changed files with 47 additions and 7 deletions
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@ -665,7 +665,7 @@ const char *CRYPTO_get_lock_name(int type)
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defined(__INTEL__) || \
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defined(__x86_64) || defined(__x86_64__) || defined(_M_AMD64) || defined(_M_X64)
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unsigned int OPENSSL_ia32cap_P[2];
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extern unsigned int OPENSSL_ia32cap_P[4];
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unsigned long *OPENSSL_ia32cap_loc(void)
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{ if (sizeof(long)==4)
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/*
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@ -674,6 +674,9 @@ unsigned long *OPENSSL_ia32cap_loc(void)
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* is 32-bit.
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*/
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OPENSSL_ia32cap_P[1]=0;
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OPENSSL_ia32cap_P[2]=0;
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return (unsigned long *)OPENSSL_ia32cap_P;
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}
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@ -686,7 +689,7 @@ typedef unsigned long long IA32CAP;
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#endif
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void OPENSSL_cpuid_setup(void)
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{ static int trigger=0;
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IA32CAP OPENSSL_ia32_cpuid(void);
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IA32CAP OPENSSL_ia32_cpuid(unsigned int *);
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IA32CAP vec;
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char *env;
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@ -700,10 +703,21 @@ void OPENSSL_cpuid_setup(void)
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#else
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if (!sscanf(env+off,"%lli",(long long *)&vec)) vec = strtoul(env+off,NULL,0);
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#endif
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if (off) vec = OPENSSL_ia32_cpuid()&~vec;
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if (off) vec = OPENSSL_ia32_cpuid(OPENSSL_ia32cap_P)&~vec;
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else if (env[0]==':') vec = OPENSSL_ia32_cpuid(OPENSSL_ia32cap_P);
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OPENSSL_ia32cap_P[2] = 0;
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if ((env=strchr(env,':'))) {
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unsigned int vecx;
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env++;
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off = (env[0]=='~')?1:0;
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vecx = strtoul(env+off,NULL,0);
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if (off) OPENSSL_ia32cap_P[2] &= ~vecx;
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else OPENSSL_ia32cap_P[2] = vecx;
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}
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}
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else
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vec = OPENSSL_ia32_cpuid();
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vec = OPENSSL_ia32_cpuid(OPENSSL_ia32cap_P);
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/*
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* |(1<<10) sets a reserved bit to signal that variable
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@ -713,6 +727,8 @@ void OPENSSL_cpuid_setup(void)
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OPENSSL_ia32cap_P[0] = (unsigned int)vec|(1<<10);
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OPENSSL_ia32cap_P[1] = (unsigned int)(vec>>32);
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}
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#else
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unsigned int OPENSSL_ia32cap_P[4];
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#endif
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#else
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@ -24,7 +24,7 @@ print<<___;
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call OPENSSL_cpuid_setup
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.hidden OPENSSL_ia32cap_P
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.comm OPENSSL_ia32cap_P,8,4
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.comm OPENSSL_ia32cap_P,16,4
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.text
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@ -53,12 +53,13 @@ OPENSSL_rdtsc:
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.size OPENSSL_rdtsc,.-OPENSSL_rdtsc
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.globl OPENSSL_ia32_cpuid
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.type OPENSSL_ia32_cpuid,\@abi-omnipotent
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.type OPENSSL_ia32_cpuid,\@function,1
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.align 16
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OPENSSL_ia32_cpuid:
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mov %rbx,%r8 # save %rbx
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xor %eax,%eax
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mov %eax,8(%rdi) # clear 3rd word
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cpuid
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mov %eax,%r11d # max value for standard query level
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@ -126,6 +127,14 @@ OPENSSL_ia32_cpuid:
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shr \$14,%r10d
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and \$0xfff,%r10d # number of cores -1 per L1D
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cmp \$7,%r11d
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jb .Lnocacheinfo
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mov \$7,%eax
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xor %ecx,%ecx
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cpuid
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mov %ebx,8(%rdi)
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.Lnocacheinfo:
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mov \$1,%eax
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cpuid
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@ -165,6 +174,7 @@ OPENSSL_ia32_cpuid:
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.Lclear_avx:
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mov \$0xefffe7ff,%eax # ~(1<<28|1<<12|1<<11)
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and %eax,%r9d # clear AVX, FMA and AMD XOP bits
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andl \$0xffffffdf,8(%rdi) # cleax AVX2, ~(1<<5)
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.Ldone:
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shl \$32,%r9
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mov %r10d,%eax
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@ -22,6 +22,8 @@ for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }
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&xor ("eax","eax");
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&bt ("ecx",21);
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&jnc (&label("nocpuid"));
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&mov ("esi",&wparam(0));
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&mov (&DWP(8,"esi"),"eax"); # clear 3rd word
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&cpuid ();
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&mov ("edi","eax"); # max value for standard query level
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@ -79,6 +81,16 @@ for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }
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&jmp (&label("generic"));
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&set_label("intel");
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&cmp ("edi",7);
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&jb (&label("cacheinfo"));
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&mov ("esi",&wparam(0));
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&mov ("eax",7);
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&xor ("ecx","ecx");
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&cpuid ();
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&mov (&DWP(8,"esi"),"ebx");
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&set_label("cacheinfo");
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&cmp ("edi",4);
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&mov ("edi",-1);
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&jb (&label("nocacheinfo"));
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@ -135,6 +147,8 @@ for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }
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&and ("esi",0xfeffffff); # clear FXSR
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&set_label("clear_avx");
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&and ("ebp",0xefffe7ff); # clear AVX, FMA and AMD XOP bits
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&mov ("edi",&wparam(0));
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&and (&DWP(8,"edi"),0xffffffdf); # clear AVX2
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&set_label("done");
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&mov ("eax","esi");
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&mov ("edx","ebp");
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@ -198,7 +212,7 @@ for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }
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&function_begin_B("OPENSSL_far_spin");
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&pushf ();
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&pop ("eax")
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&pop ("eax");
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&bt ("eax",9);
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&jnc (&label("nospin")); # interrupts are disabled
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