Add AES assembly module for Fujitsu SPARC64 X/X+.
Reviewed-by: Richard Levitte <levitte@openssl.org>
This commit is contained in:
Andy Polyakov
parent
38c5674dda
commit
fb65020b37
3 changed files with 439 additions and 0 deletions
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@ -70,6 +70,8 @@ aes-sparcv9.S: asm/aes-sparcv9.pl
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$(PERL) asm/aes-sparcv9.pl $(PERLASM_SCHEME) $@
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aest4-sparcv9.S: asm/aest4-sparcv9.pl ../perlasm/sparcv9_modes.pl
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$(PERL) asm/aest4-sparcv9.pl $(PERLASM_SCHEME) $@
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aesfx-sparcv9.S: asm/aesfx-sparcv9.pl
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$(PERL) asm/aesfx-sparcv9.pl $(PERLASM_SCHEME) $@
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aes-ppc.s: asm/aes-ppc.pl
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$(PERL) asm/aes-ppc.pl $(PERLASM_SCHEME) $@
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435
crypto/aes/asm/aesfx-sparcv9.pl
Executable file
435
crypto/aes/asm/aesfx-sparcv9.pl
Executable file
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@ -0,0 +1,435 @@
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#!/usr/bin/env perl
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#
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# ====================================================================
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# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
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# project. The module is, however, dual licensed under OpenSSL and
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# CRYPTOGAMS licenses depending on where you obtain it. For further
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# details see http://www.openssl.org/~appro/cryptogams/.
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# ====================================================================
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# March 2016
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#
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# Initial support for Fujitsu SPARC64 X/X+ comprises minimally
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# required key setup and single-block procedures.
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$output = pop;
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open STDOUT,">$output";
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{
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my ($inp,$out,$key,$rounds,$tmp,$mask) = map("%o$_",(0..5));
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$code.=<<___;
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.text
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.globl aes_fx_encrypt
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.align 32
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aes_fx_encrypt:
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and $inp, 7, $tmp ! is input aligned?
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alignaddr $inp, %g0, $inp
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ld [$key + 240], $rounds
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ldd [$key + 0], %f6
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ldd [$key + 8], %f8
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ldd [$inp + 0], %f0 ! load input
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brz,pt $tmp, .Lenc_inp_aligned
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ldd [$inp + 8], %f2
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ldd [$inp + 16], %f4
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faligndata %f0, %f2, %f0
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faligndata %f2, %f4, %f2
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.Lenc_inp_aligned:
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ldd [$key + 16], %f10
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ldd [$key + 24], %f12
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add $key, 32, $key
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fxor %f0, %f6, %f0 ! ^=round[0]
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fxor %f2, %f8, %f2
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ldd [$key + 0], %f6
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ldd [$key + 8], %f8
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sub $rounds, 4, $rounds
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.Loop_enc:
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fmovd %f0, %f4
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faesencx %f2, %f10, %f0
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faesencx %f4, %f12, %f2
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ldd [$key + 16], %f10
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ldd [$key + 24], %f12
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add $key, 32, $key
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fmovd %f0, %f4
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faesencx %f2, %f6, %f0
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faesencx %f4, %f8, %f2
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ldd [$key + 0], %f6
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ldd [$key + 8], %f8
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brnz,a $rounds, .Loop_enc
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sub $rounds, 2, $rounds
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andcc $out, 7, $tmp ! is output aligned?
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mov 0xff, $mask
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alignaddrl $out, %g0, $out
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srl $mask, $tmp, $mask
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fmovd %f0, %f4
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faesencx %f2, %f10, %f0
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faesencx %f4, %f12, %f2
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fmovd %f0, %f4
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faesenclx %f2, %f6, %f0
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faesenclx %f4, %f8, %f2
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bnz,pn %icc, .Lenc_out_unaligned
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nop
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std %f0, [$out + 0]
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retl
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std %f2, [$out + 8]
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.Lenc_out_unaligned:
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faligndata %f0, %f0, %f4
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faligndata %f0, %f2, %f6
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faligndata %f2, %f2, %f8
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stda %f4, [$out + $mask]0xc0 ! partial store
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std %f6, [$out + 8]
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add $out, 16, $out
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orn %g0, $mask, $mask
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retl
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stda %f8, [$out + $mask]0xc0 ! partial store
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.size aes_fx_encrypt,.-aes_fx_encrypt
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.globl aes_fx_decrypt
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.align 32
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aes_fx_decrypt:
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and $inp, 7, $tmp ! is input aligned?
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alignaddr $inp, %g0, $inp
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ld [$key + 240], $rounds
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ldd [$key + 0], %f6
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ldd [$key + 8], %f8
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ldd [$inp + 0], %f0 ! load input
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brz,pt $tmp, .Ldec_inp_aligned
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ldd [$inp + 8], %f2
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ldd [$inp + 16], %f4
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faligndata %f0, %f2, %f0
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faligndata %f2, %f4, %f2
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.Ldec_inp_aligned:
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ldd [$key + 16], %f10
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ldd [$key + 24], %f12
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add $key, 32, $key
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fxor %f0, %f6, %f0 ! ^=round[0]
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fxor %f2, %f8, %f2
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ldd [$key + 0], %f6
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ldd [$key + 8], %f8
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sub $rounds, 4, $rounds
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.Loop_dec:
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fmovd %f0, %f4
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faesdecx %f2, %f10, %f0
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faesdecx %f4, %f12, %f2
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ldd [$key + 16], %f10
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ldd [$key + 24], %f12
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add $key, 32, $key
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fmovd %f0, %f4
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faesdecx %f2, %f6, %f0
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faesdecx %f4, %f8, %f2
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ldd [$key + 0], %f6
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ldd [$key + 8], %f8
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brnz,a $rounds, .Loop_dec
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sub $rounds, 2, $rounds
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andcc $out, 7, $tmp ! is output aligned?
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mov 0xff, $mask
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alignaddrl $out, %g0, $out
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srl $mask, $tmp, $mask
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fmovd %f0, %f4
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faesdecx %f2, %f10, %f0
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faesdecx %f4, %f12, %f2
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fmovd %f0, %f4
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faesdeclx %f2, %f6, %f0
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faesdeclx %f4, %f8, %f2
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bnz,pn %icc, .Ldec_out_unaligned
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nop
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std %f0, [$out + 0]
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retl
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std %f2, [$out + 8]
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.Ldec_out_unaligned:
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faligndata %f0, %f0, %f4
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faligndata %f0, %f2, %f6
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faligndata %f2, %f2, %f8
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stda %f4, [$out + $mask]0xc0 ! partial store
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std %f6, [$out + 8]
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add $out, 16, $out
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orn %g0, $mask, $mask
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retl
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stda %f8, [$out + $mask]0xc0 ! partial store
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.size aes_fx_decrypt,.-aes_fx_decrypt
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___
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}
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{
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my ($inp,$bits,$out,$tmp,$inc) = map("%o$_",(0..5));
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$code.=<<___;
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.globl aes_fx_set_decrypt_key
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.align 32
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aes_fx_set_decrypt_key:
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b .Lset_encrypt_key
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mov -1, $inc
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retl
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nop
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.size aes_fx_set_decrypt_key,.-aes_fx_set_decrypt_key
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.globl aes_fx_set_encrypt_key
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.align 32
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aes_fx_set_encrypt_key:
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mov 1, $inc
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.Lset_encrypt_key:
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and $inp, 7, $tmp
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alignaddr $inp, %g0, $inp
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nop
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cmp $bits, 192
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ldd [$inp + 0], %f0
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bl,pt %icc, .L128
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ldd [$inp + 8], %f2
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be,pt %icc, .L192
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ldd [$inp + 16], %f4
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brz,pt $tmp, .L256aligned
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ldd [$inp + 24], %f6
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ldd [$inp + 32], %f8
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faligndata %f0, %f2, %f0
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faligndata %f2, %f4, %f2
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faligndata %f4, %f6, %f4
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faligndata %f6, %f8, %f6
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.L256aligned:
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mov 14, $bits
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and $inc, `14*16`, $tmp
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st $bits, [$out + 240] ! store rounds
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add $out, $tmp, $out ! start or end of key schedule
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sllx $inc, 4, $inc ! 16 or -16
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___
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for ($i=0; $i<6; $i++) {
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$code.=<<___;
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std %f0, [$out + 0]
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faeskeyx %f6, `0x10+$i`, %f0
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std %f2, [$out + 8]
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add $out, $inc, $out
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faeskeyx %f0, 0x00, %f2
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std %f4, [$out + 0]
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faeskeyx %f2, 0x01, %f4
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std %f6, [$out + 8]
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add $out, $inc, $out
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faeskeyx %f4, 0x00, %f6
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___
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}
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$code.=<<___;
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std %f0, [$out + 0]
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faeskeyx %f6, `0x10+$i`, %f0
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std %f2, [$out + 8]
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add $out, $inc, $out
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faeskeyx %f0, 0x00, %f2
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std %f4,[$out+0]
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std %f6,[$out+8]
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add $out, $inc, $out
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std %f0,[$out+0]
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std %f2,[$out+8]
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retl
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xor %o0, %o0, %o0 ! return 0
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.align 16
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.L192:
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brz,pt $tmp, .L192aligned
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nop
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ldd [$inp + 24], %f6
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faligndata %f0, %f2, %f0
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faligndata %f2, %f4, %f2
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faligndata %f4, %f6, %f4
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.L192aligned:
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mov 12, $bits
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and $inc, `12*16`, $tmp
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st $bits, [$out + 240] ! store rounds
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add $out, $tmp, $out ! start or end of key schedule
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sllx $inc, 4, $inc ! 16 or -16
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___
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for ($i=0; $i<8; $i+=2) {
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$code.=<<___;
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std %f0, [$out + 0]
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faeskeyx %f4, `0x10+$i`, %f0
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std %f2, [$out + 8]
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add $out, $inc, $out
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faeskeyx %f0, 0x00, %f2
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std %f4, [$out + 0]
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faeskeyx %f2, 0x00, %f4
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std %f0, [$out + 8]
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add $out, $inc, $out
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faeskeyx %f4, `0x10+$i+1`, %f0
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std %f2, [$out + 0]
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faeskeyx %f0, 0x00, %f2
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std %f4, [$out + 8]
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add $out, $inc, $out
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___
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$code.=<<___ if ($i<6);
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faeskeyx %f2, 0x00, %f4
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___
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}
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$code.=<<___;
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std %f0, [$out + 0]
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std %f2, [$out + 8]
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retl
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xor %o0, %o0, %o0 ! return 0
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.align 16
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.L128:
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brz,pt $tmp, .L128aligned
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nop
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ldd [$inp + 16], %f4
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faligndata %f0, %f2, %f0
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faligndata %f2, %f4, %f2
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.L128aligned:
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mov 10, $bits
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and $inc, `10*16`, $tmp
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st $bits, [$out + 240] ! store rounds
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add $out, $tmp, $out ! start or end of key schedule
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sllx $inc, 4, $inc ! 16 or -16
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___
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for ($i=0; $i<10; $i++) {
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$code.=<<___;
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std %f0, [$out + 0]
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faeskeyx %f2, `0x10+$i`, %f0
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std %f2, [$out + 8]
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add $out, $inc, $out
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faeskeyx %f0, 0x00, %f2
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___
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}
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$code.=<<___;
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std %f0, [$out + 0]
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std %f2, [$out + 8]
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retl
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xor %o0, %o0, %o0 ! return 0
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.size aes_fx_set_encrypt_key,.-aes_fx_set_encrypt_key
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___
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}
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# Purpose of these subroutines is to explicitly encode VIS instructions,
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# so that one can compile the module without having to specify VIS
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# extensions on compiler command line, e.g. -xarch=v9 vs. -xarch=v9a.
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# Idea is to reserve for option to produce "universal" binary and let
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# programmer detect if current CPU is VIS capable at run-time.
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sub unvis {
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my ($mnemonic,$rs1,$rs2,$rd)=@_;
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my ($ref,$opf);
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my %visopf = ( "faligndata" => 0x048,
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"bshuffle" => 0x04c,
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"fxor" => 0x06c,
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"fsrc2" => 0x078 );
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$ref = "$mnemonic\t$rs1,$rs2,$rd";
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if ($opf=$visopf{$mnemonic}) {
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foreach ($rs1,$rs2,$rd) {
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return $ref if (!/%f([0-9]{1,2})/);
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$_=$1;
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if ($1>=32) {
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return $ref if ($1&1);
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# re-encode for upper double register addressing
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$_=($1|$1>>5)&31;
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}
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}
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return sprintf ".word\t0x%08x !%s",
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0x81b00000|$rd<<25|$rs1<<14|$opf<<5|$rs2,
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$ref;
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} else {
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return $ref;
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}
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}
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sub unvis3 {
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my ($mnemonic,$rs1,$rs2,$rd)=@_;
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my %bias = ( "g" => 0, "o" => 8, "l" => 16, "i" => 24 );
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my ($ref,$opf);
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my %visopf = ( "alignaddr" => 0x018,
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"bmask" => 0x019,
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"alignaddrl" => 0x01a );
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$ref = "$mnemonic\t$rs1,$rs2,$rd";
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if ($opf=$visopf{$mnemonic}) {
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foreach ($rs1,$rs2,$rd) {
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return $ref if (!/%([goli])([0-9])/);
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$_=$bias{$1}+$2;
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}
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return sprintf ".word\t0x%08x !%s",
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0x81b00000|$rd<<25|$rs1<<14|$opf<<5|$rs2,
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$ref;
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} else {
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return $ref;
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}
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}
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sub unfx {
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my ($mnemonic,$rs1,$rs2,$rd)=@_;
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my ($ref,$opf);
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my %aesopf = ( "faesencx" => 0x90,
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"faesdecx" => 0x91,
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"faesenclx" => 0x92,
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"faesdeclx" => 0x93,
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"faeskeyx" => 0x94 );
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$ref = "$mnemonic\t$rs1,$rs2,$rd";
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if (defined($opf=$aesopf{$mnemonic})) {
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$rs2 = ($rs2 =~ /%f([0-6]*[02468])/) ? (($1|$1>>5)&31) : $rs2;
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$rs2 = oct($rs2) if ($rs2 =~ /^0/);
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foreach ($rs1,$rd) {
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return $ref if (!/%f([0-9]{1,2})/);
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$_=$1;
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if ($1>=32) {
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return $ref if ($1&1);
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# re-encode for upper double register addressing
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$_=($1|$1>>5)&31;
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}
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}
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return sprintf ".word\t0x%08x !%s",
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2<<30|$rd<<25|0x36<<19|$rs1<<14|$opf<<5|$rs2,
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$ref;
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} else {
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return $ref;
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}
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}
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foreach (split("\n",$code)) {
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s/\`([^\`]*)\`/eval $1/ge;
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s/\b(faes[^x]{3,4}x)\s+(%f[0-9]{1,2}),\s*([%fx0-9]+),\s*(%f[0-9]{1,2})/
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&unfx($1,$2,$3,$4,$5)
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/ge or
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s/\b([fb][^\s]*)\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2}),\s*(%f[0-9]{1,2})/
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&unvis($1,$2,$3,$4)
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/ge or
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s/\b(alignaddr[l]*)\s+(%[goli][0-7]),\s*(%[goli][0-7]),\s*(%[goli][0-7])/
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&unvis3($1,$2,$3,$4)
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/ge;
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print $_,"\n";
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}
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||||
close STDOUT;
|
||||
|
|
@ -25,6 +25,8 @@ INCLUDE[aes-sparcv9.o]=..
|
|||
GENERATE[aest4-sparcv9.S]=asm/aest4-sparcv9.pl $(PERLASM_SCHEME)
|
||||
INCLUDE[aest4-sparcv9.o]=..
|
||||
DEPEND[aest4-sparcv9.S]=../perlasm/sparcv9_modes.pl
|
||||
GENERATE[aesfx-sparcv9.S]=asm/aesfx-sparcv9.pl $(PERLASM_SCHEME)
|
||||
INCLUDE[aesfx-sparcv9.o]=..
|
||||
|
||||
GENERATE[aes-ppc.s]=asm/aes-ppc.pl $(PERLASM_SCHEME)
|
||||
GENERATE[vpaes-ppc.s]=asm/vpaes-ppc.pl $(PERLASM_SCHEME)
|
||||
|
|
|
|||
Loading…
Reference in a new issue