1031 lines
17 KiB
ArmAsm
1031 lines
17 KiB
ArmAsm
.ident "md5-sparcv9.S, Version 1.0"
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.ident "SPARC V9 ISA artwork by Andy Polyakov <appro@fy.chalmers.se>"
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.file "md5-sparcv9.S"
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/*
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* ====================================================================
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* Copyright (c) 1999 Andy Polyakov <appro@fy.chalmers.se>.
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*
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* Rights for redistribution and usage in source and binary forms are
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* granted as long as above copyright notices are retained. Warranty
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* of any kind is (of course:-) disclaimed.
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* ====================================================================
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*/
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/*
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* This is my modest contribution to OpenSSL project (see
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* http://www.openssl.org/ for more information about it) and is an
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* assembler implementation of MD5 block hash function. I've hand-coded
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* this for the sole reason to reach UltraSPARC-specific "load in
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* little-endian byte order" instruction. This gives up to 15%
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* performance improvement for cases when input message is aligned at
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* 32 bits boundary. The module was tested under both 32 *and* 64 bit
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* kernels. For updates see http://fy.chalmers.se/~appro/hpe/.
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*
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* To compile with SC4.x/SC5.x:
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*
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* cc -xarch=v[9|8plus] -DOPENSSL_SYSNAME_ULTRASPARC -DMD5_BLOCK_DATA_ORDER \
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* -c md5-sparcv9.S
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*
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* and with gcc:
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*
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* gcc -mcpu=ultrasparc -DOPENSSL_SYSNAME_ULTRASPARC -DMD5_BLOCK_DATA_ORDER \
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* -c md5-sparcv9.S
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*
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* or if above fails (it does if you have gas):
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*
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* gcc -E -DOPENSSL_SYSNAMEULTRASPARC -DMD5_BLOCK_DATA_ORDER md5_block.sparc.S | \
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* as -xarch=v8plus /dev/fd/0 -o md5-sparcv9.o
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*/
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#include <openssl/e_os2.h>
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#define A %o0
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#define B %o1
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#define C %o2
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#define D %o3
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#define T1 %o4
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#define T2 %o5
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#define R0 %l0
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#define R1 %l1
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#define R2 %l2
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#define R3 %l3
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#define R4 %l4
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#define R5 %l5
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#define R6 %l6
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#define R7 %l7
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#define R8 %i3
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#define R9 %i4
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#define R10 %i5
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#define R11 %g1
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#define R12 %g2
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#define R13 %g3
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#define RX %g4
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#define Aptr %i0+0
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#define Bptr %i0+4
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#define Cptr %i0+8
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#define Dptr %i0+12
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#define Aval R5 /* those not used at the end of the last round */
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#define Bval R6
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#define Cval R7
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#define Dval R8
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#if defined(MD5_BLOCK_DATA_ORDER)
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# if defined(OPENSSL_SYSNAME_ULTRASPARC)
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# define LOAD lda
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# define X(i) [%i1+i*4]%asi
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# define md5_block md5_block_asm_data_order_aligned
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# define ASI_PRIMARY_LITTLE 0x88
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# else
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# error "MD5_BLOCK_DATA_ORDER is supported only on UltraSPARC!"
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# endif
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#else
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# define LOAD ld
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# define X(i) [%i1+i*4]
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# define md5_block md5_block_asm_host_order
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#endif
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.section ".text",#alloc,#execinstr
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#if defined(__SUNPRO_C) && defined(__sparcv9)
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/* They've said -xarch=v9 at command line */
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.register %g2,#scratch
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.register %g3,#scratch
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# define FRAME -192
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#elif defined(__GNUC__) && defined(__arch64__)
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/* They've said -m64 at command line */
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.register %g2,#scratch
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.register %g3,#scratch
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# define FRAME -192
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#else
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# define FRAME -96
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#endif
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.align 32
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.global md5_block
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md5_block:
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save %sp,FRAME,%sp
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ld [Dptr],D
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ld [Cptr],C
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ld [Bptr],B
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ld [Aptr],A
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#ifdef ASI_PRIMARY_LITTLE
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rd %asi,%o7 ! How dare I? Well, I just do:-)
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wr %g0,ASI_PRIMARY_LITTLE,%asi
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#endif
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LOAD X(0),R0
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.Lmd5_block_loop:
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!!!!!!!!Round 0
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xor C,D,T1
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sethi %hi(0xd76aa478),T2
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and T1,B,T1
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or T2,%lo(0xd76aa478),T2 !=
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xor T1,D,T1
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add T1,R0,T1
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LOAD X(1),R1
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add T1,T2,T1 !=
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add A,T1,A
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sll A,7,T2
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srl A,32-7,A
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or A,T2,A !=
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xor B,C,T1
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add A,B,A
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sethi %hi(0xe8c7b756),T2
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and T1,A,T1 !=
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or T2,%lo(0xe8c7b756),T2
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xor T1,C,T1
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LOAD X(2),R2
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add T1,R1,T1 !=
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add T1,T2,T1
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add D,T1,D
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sll D,12,T2
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srl D,32-12,D !=
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or D,T2,D
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xor A,B,T1
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add D,A,D
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sethi %hi(0x242070db),T2 !=
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and T1,D,T1
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or T2,%lo(0x242070db),T2
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xor T1,B,T1
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add T1,R2,T1 !=
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LOAD X(3),R3
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add T1,T2,T1
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add C,T1,C
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sll C,17,T2 !=
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srl C,32-17,C
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or C,T2,C
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xor D,A,T1
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add C,D,C !=
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sethi %hi(0xc1bdceee),T2
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and T1,C,T1
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or T2,%lo(0xc1bdceee),T2
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xor T1,A,T1 !=
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add T1,R3,T1
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LOAD X(4),R4
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add T1,T2,T1
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add B,T1,B !=
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sll B,22,T2
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srl B,32-22,B
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or B,T2,B
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xor C,D,T1 !=
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add B,C,B
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sethi %hi(0xf57c0faf),T2
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and T1,B,T1
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or T2,%lo(0xf57c0faf),T2 !=
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xor T1,D,T1
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add T1,R4,T1
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LOAD X(5),R5
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add T1,T2,T1 !=
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add A,T1,A
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sll A,7,T2
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srl A,32-7,A
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or A,T2,A !=
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xor B,C,T1
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add A,B,A
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sethi %hi(0x4787c62a),T2
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and T1,A,T1 !=
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or T2,%lo(0x4787c62a),T2
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xor T1,C,T1
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LOAD X(6),R6
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add T1,R5,T1 !=
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add T1,T2,T1
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add D,T1,D
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sll D,12,T2
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srl D,32-12,D !=
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or D,T2,D
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xor A,B,T1
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add D,A,D
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sethi %hi(0xa8304613),T2 !=
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and T1,D,T1
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or T2,%lo(0xa8304613),T2
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xor T1,B,T1
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add T1,R6,T1 !=
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LOAD X(7),R7
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add T1,T2,T1
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add C,T1,C
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sll C,17,T2 !=
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srl C,32-17,C
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or C,T2,C
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xor D,A,T1
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add C,D,C !=
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sethi %hi(0xfd469501),T2
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and T1,C,T1
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or T2,%lo(0xfd469501),T2
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xor T1,A,T1 !=
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add T1,R7,T1
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LOAD X(8),R8
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add T1,T2,T1
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add B,T1,B !=
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sll B,22,T2
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srl B,32-22,B
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or B,T2,B
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xor C,D,T1 !=
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add B,C,B
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sethi %hi(0x698098d8),T2
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and T1,B,T1
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or T2,%lo(0x698098d8),T2 !=
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xor T1,D,T1
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add T1,R8,T1
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LOAD X(9),R9
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add T1,T2,T1 !=
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add A,T1,A
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sll A,7,T2
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srl A,32-7,A
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or A,T2,A !=
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xor B,C,T1
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add A,B,A
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sethi %hi(0x8b44f7af),T2
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and T1,A,T1 !=
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or T2,%lo(0x8b44f7af),T2
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xor T1,C,T1
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LOAD X(10),R10
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add T1,R9,T1 !=
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add T1,T2,T1
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add D,T1,D
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sll D,12,T2
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srl D,32-12,D !=
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or D,T2,D
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xor A,B,T1
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add D,A,D
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sethi %hi(0xffff5bb1),T2 !=
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and T1,D,T1
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or T2,%lo(0xffff5bb1),T2
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xor T1,B,T1
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add T1,R10,T1 !=
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LOAD X(11),R11
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add T1,T2,T1
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add C,T1,C
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sll C,17,T2 !=
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srl C,32-17,C
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or C,T2,C
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xor D,A,T1
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add C,D,C !=
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sethi %hi(0x895cd7be),T2
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and T1,C,T1
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or T2,%lo(0x895cd7be),T2
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xor T1,A,T1 !=
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add T1,R11,T1
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LOAD X(12),R12
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add T1,T2,T1
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add B,T1,B !=
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sll B,22,T2
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srl B,32-22,B
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or B,T2,B
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xor C,D,T1 !=
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add B,C,B
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sethi %hi(0x6b901122),T2
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and T1,B,T1
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or T2,%lo(0x6b901122),T2 !=
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xor T1,D,T1
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add T1,R12,T1
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LOAD X(13),R13
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add T1,T2,T1 !=
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add A,T1,A
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sll A,7,T2
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srl A,32-7,A
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or A,T2,A !=
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xor B,C,T1
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add A,B,A
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sethi %hi(0xfd987193),T2
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and T1,A,T1 !=
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or T2,%lo(0xfd987193),T2
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xor T1,C,T1
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LOAD X(14),RX
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add T1,R13,T1 !=
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add T1,T2,T1
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add D,T1,D
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sll D,12,T2
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srl D,32-12,D !=
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or D,T2,D
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xor A,B,T1
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add D,A,D
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sethi %hi(0xa679438e),T2 !=
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and T1,D,T1
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or T2,%lo(0xa679438e),T2
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xor T1,B,T1
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add T1,RX,T1 !=
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LOAD X(15),RX
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add T1,T2,T1
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add C,T1,C
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sll C,17,T2 !=
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srl C,32-17,C
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or C,T2,C
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xor D,A,T1
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add C,D,C !=
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sethi %hi(0x49b40821),T2
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and T1,C,T1
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or T2,%lo(0x49b40821),T2
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xor T1,A,T1 !=
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add T1,RX,T1
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!pre-LOADed X(1),R1
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add T1,T2,T1
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add B,T1,B
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sll B,22,T2 !=
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srl B,32-22,B
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or B,T2,B
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add B,C,B
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!!!!!!!!Round 1
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xor B,C,T1 !=
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sethi %hi(0xf61e2562),T2
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and T1,D,T1
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or T2,%lo(0xf61e2562),T2
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xor T1,C,T1 !=
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add T1,R1,T1
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!pre-LOADed X(6),R6
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add T1,T2,T1
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add A,T1,A
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sll A,5,T2 !=
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srl A,32-5,A
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or A,T2,A
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add A,B,A
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xor A,B,T1 !=
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sethi %hi(0xc040b340),T2
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and T1,C,T1
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or T2,%lo(0xc040b340),T2
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xor T1,B,T1 !=
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add T1,R6,T1
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!pre-LOADed X(11),R11
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add T1,T2,T1
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add D,T1,D
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sll D,9,T2 !=
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srl D,32-9,D
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or D,T2,D
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add D,A,D
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xor D,A,T1 !=
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sethi %hi(0x265e5a51),T2
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and T1,B,T1
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or T2,%lo(0x265e5a51),T2
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xor T1,A,T1 !=
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add T1,R11,T1
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!pre-LOADed X(0),R0
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add T1,T2,T1
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add C,T1,C
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sll C,14,T2 !=
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srl C,32-14,C
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or C,T2,C
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add C,D,C
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|
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xor C,D,T1 !=
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sethi %hi(0xe9b6c7aa),T2
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and T1,A,T1
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or T2,%lo(0xe9b6c7aa),T2
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|
xor T1,D,T1 !=
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|
add T1,R0,T1
|
|
!pre-LOADed X(5),R5
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|
add T1,T2,T1
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|
add B,T1,B
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|
sll B,20,T2 !=
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|
srl B,32-20,B
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|
or B,T2,B
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|
add B,C,B
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|
|
|
xor B,C,T1 !=
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|
sethi %hi(0xd62f105d),T2
|
|
and T1,D,T1
|
|
or T2,%lo(0xd62f105d),T2
|
|
xor T1,C,T1 !=
|
|
add T1,R5,T1
|
|
!pre-LOADed X(10),R10
|
|
add T1,T2,T1
|
|
add A,T1,A
|
|
sll A,5,T2 !=
|
|
srl A,32-5,A
|
|
or A,T2,A
|
|
add A,B,A
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|
|
|
xor A,B,T1 !=
|
|
sethi %hi(0x02441453),T2
|
|
and T1,C,T1
|
|
or T2,%lo(0x02441453),T2
|
|
xor T1,B,T1 !=
|
|
add T1,R10,T1
|
|
LOAD X(15),RX
|
|
add T1,T2,T1
|
|
add D,T1,D !=
|
|
sll D,9,T2
|
|
srl D,32-9,D
|
|
or D,T2,D
|
|
add D,A,D !=
|
|
|
|
xor D,A,T1
|
|
sethi %hi(0xd8a1e681),T2
|
|
and T1,B,T1
|
|
or T2,%lo(0xd8a1e681),T2 !=
|
|
xor T1,A,T1
|
|
add T1,RX,T1
|
|
!pre-LOADed X(4),R4
|
|
add T1,T2,T1
|
|
add C,T1,C !=
|
|
sll C,14,T2
|
|
srl C,32-14,C
|
|
or C,T2,C
|
|
add C,D,C !=
|
|
|
|
xor C,D,T1
|
|
sethi %hi(0xe7d3fbc8),T2
|
|
and T1,A,T1
|
|
or T2,%lo(0xe7d3fbc8),T2 !=
|
|
xor T1,D,T1
|
|
add T1,R4,T1
|
|
!pre-LOADed X(9),R9
|
|
add T1,T2,T1
|
|
add B,T1,B !=
|
|
sll B,20,T2
|
|
srl B,32-20,B
|
|
or B,T2,B
|
|
add B,C,B !=
|
|
|
|
xor B,C,T1
|
|
sethi %hi(0x21e1cde6),T2
|
|
and T1,D,T1
|
|
or T2,%lo(0x21e1cde6),T2 !=
|
|
xor T1,C,T1
|
|
add T1,R9,T1
|
|
LOAD X(14),RX
|
|
add T1,T2,T1 !=
|
|
add A,T1,A
|
|
sll A,5,T2
|
|
srl A,32-5,A
|
|
or A,T2,A !=
|
|
add A,B,A
|
|
|
|
xor A,B,T1
|
|
sethi %hi(0xc33707d6),T2
|
|
and T1,C,T1 !=
|
|
or T2,%lo(0xc33707d6),T2
|
|
xor T1,B,T1
|
|
add T1,RX,T1
|
|
!pre-LOADed X(3),R3
|
|
add T1,T2,T1 !=
|
|
add D,T1,D
|
|
sll D,9,T2
|
|
srl D,32-9,D
|
|
or D,T2,D !=
|
|
add D,A,D
|
|
|
|
xor D,A,T1
|
|
sethi %hi(0xf4d50d87),T2
|
|
and T1,B,T1 !=
|
|
or T2,%lo(0xf4d50d87),T2
|
|
xor T1,A,T1
|
|
add T1,R3,T1
|
|
!pre-LOADed X(8),R8
|
|
add T1,T2,T1 !=
|
|
add C,T1,C
|
|
sll C,14,T2
|
|
srl C,32-14,C
|
|
or C,T2,C !=
|
|
add C,D,C
|
|
|
|
xor C,D,T1
|
|
sethi %hi(0x455a14ed),T2
|
|
and T1,A,T1 !=
|
|
or T2,%lo(0x455a14ed),T2
|
|
xor T1,D,T1
|
|
add T1,R8,T1
|
|
!pre-LOADed X(13),R13
|
|
add T1,T2,T1 !=
|
|
add B,T1,B
|
|
sll B,20,T2
|
|
srl B,32-20,B
|
|
or B,T2,B !=
|
|
add B,C,B
|
|
|
|
xor B,C,T1
|
|
sethi %hi(0xa9e3e905),T2
|
|
and T1,D,T1 !=
|
|
or T2,%lo(0xa9e3e905),T2
|
|
xor T1,C,T1
|
|
add T1,R13,T1
|
|
!pre-LOADed X(2),R2
|
|
add T1,T2,T1 !=
|
|
add A,T1,A
|
|
sll A,5,T2
|
|
srl A,32-5,A
|
|
or A,T2,A !=
|
|
add A,B,A
|
|
|
|
xor A,B,T1
|
|
sethi %hi(0xfcefa3f8),T2
|
|
and T1,C,T1 !=
|
|
or T2,%lo(0xfcefa3f8),T2
|
|
xor T1,B,T1
|
|
add T1,R2,T1
|
|
!pre-LOADed X(7),R7
|
|
add T1,T2,T1 !=
|
|
add D,T1,D
|
|
sll D,9,T2
|
|
srl D,32-9,D
|
|
or D,T2,D !=
|
|
add D,A,D
|
|
|
|
xor D,A,T1
|
|
sethi %hi(0x676f02d9),T2
|
|
and T1,B,T1 !=
|
|
or T2,%lo(0x676f02d9),T2
|
|
xor T1,A,T1
|
|
add T1,R7,T1
|
|
!pre-LOADed X(12),R12
|
|
add T1,T2,T1 !=
|
|
add C,T1,C
|
|
sll C,14,T2
|
|
srl C,32-14,C
|
|
or C,T2,C !=
|
|
add C,D,C
|
|
|
|
xor C,D,T1
|
|
sethi %hi(0x8d2a4c8a),T2
|
|
and T1,A,T1 !=
|
|
or T2,%lo(0x8d2a4c8a),T2
|
|
xor T1,D,T1
|
|
add T1,R12,T1
|
|
!pre-LOADed X(5),R5
|
|
add T1,T2,T1 !=
|
|
add B,T1,B
|
|
sll B,20,T2
|
|
srl B,32-20,B
|
|
or B,T2,B !=
|
|
add B,C,B
|
|
|
|
!!!!!!!!Round 2
|
|
|
|
xor B,C,T1
|
|
sethi %hi(0xfffa3942),T2
|
|
xor T1,D,T1 !=
|
|
or T2,%lo(0xfffa3942),T2
|
|
add T1,R5,T1
|
|
!pre-LOADed X(8),R8
|
|
add T1,T2,T1
|
|
add A,T1,A !=
|
|
sll A,4,T2
|
|
srl A,32-4,A
|
|
or A,T2,A
|
|
add A,B,A !=
|
|
|
|
xor A,B,T1
|
|
sethi %hi(0x8771f681),T2
|
|
xor T1,C,T1
|
|
or T2,%lo(0x8771f681),T2 !=
|
|
add T1,R8,T1
|
|
!pre-LOADed X(11),R11
|
|
add T1,T2,T1
|
|
add D,T1,D
|
|
sll D,11,T2 !=
|
|
srl D,32-11,D
|
|
or D,T2,D
|
|
add D,A,D
|
|
|
|
xor D,A,T1 !=
|
|
sethi %hi(0x6d9d6122),T2
|
|
xor T1,B,T1
|
|
or T2,%lo(0x6d9d6122),T2
|
|
add T1,R11,T1 !=
|
|
LOAD X(14),RX
|
|
add T1,T2,T1
|
|
add C,T1,C
|
|
sll C,16,T2 !=
|
|
srl C,32-16,C
|
|
or C,T2,C
|
|
add C,D,C
|
|
|
|
xor C,D,T1 !=
|
|
sethi %hi(0xfde5380c),T2
|
|
xor T1,A,T1
|
|
or T2,%lo(0xfde5380c),T2
|
|
add T1,RX,T1 !=
|
|
!pre-LOADed X(1),R1
|
|
add T1,T2,T1
|
|
add B,T1,B
|
|
sll B,23,T2
|
|
srl B,32-23,B !=
|
|
or B,T2,B
|
|
add B,C,B
|
|
|
|
xor B,C,T1
|
|
sethi %hi(0xa4beea44),T2 !=
|
|
xor T1,D,T1
|
|
or T2,%lo(0xa4beea44),T2
|
|
add T1,R1,T1
|
|
!pre-LOADed X(4),R4
|
|
add T1,T2,T1 !=
|
|
add A,T1,A
|
|
sll A,4,T2
|
|
srl A,32-4,A
|
|
or A,T2,A !=
|
|
add A,B,A
|
|
|
|
xor A,B,T1
|
|
sethi %hi(0x4bdecfa9),T2
|
|
xor T1,C,T1 !=
|
|
or T2,%lo(0x4bdecfa9),T2
|
|
add T1,R4,T1
|
|
!pre-LOADed X(7),R7
|
|
add T1,T2,T1
|
|
add D,T1,D !=
|
|
sll D,11,T2
|
|
srl D,32-11,D
|
|
or D,T2,D
|
|
add D,A,D !=
|
|
|
|
xor D,A,T1
|
|
sethi %hi(0xf6bb4b60),T2
|
|
xor T1,B,T1
|
|
or T2,%lo(0xf6bb4b60),T2 !=
|
|
add T1,R7,T1
|
|
!pre-LOADed X(10),R10
|
|
add T1,T2,T1
|
|
add C,T1,C
|
|
sll C,16,T2 !=
|
|
srl C,32-16,C
|
|
or C,T2,C
|
|
add C,D,C
|
|
|
|
xor C,D,T1 !=
|
|
sethi %hi(0xbebfbc70),T2
|
|
xor T1,A,T1
|
|
or T2,%lo(0xbebfbc70),T2
|
|
add T1,R10,T1 !=
|
|
!pre-LOADed X(13),R13
|
|
add T1,T2,T1
|
|
add B,T1,B
|
|
sll B,23,T2
|
|
srl B,32-23,B !=
|
|
or B,T2,B
|
|
add B,C,B
|
|
|
|
xor B,C,T1
|
|
sethi %hi(0x289b7ec6),T2 !=
|
|
xor T1,D,T1
|
|
or T2,%lo(0x289b7ec6),T2
|
|
add T1,R13,T1
|
|
!pre-LOADed X(0),R0
|
|
add T1,T2,T1 !=
|
|
add A,T1,A
|
|
sll A,4,T2
|
|
srl A,32-4,A
|
|
or A,T2,A !=
|
|
add A,B,A
|
|
|
|
xor A,B,T1
|
|
sethi %hi(0xeaa127fa),T2
|
|
xor T1,C,T1 !=
|
|
or T2,%lo(0xeaa127fa),T2
|
|
add T1,R0,T1
|
|
!pre-LOADed X(3),R3
|
|
add T1,T2,T1
|
|
add D,T1,D !=
|
|
sll D,11,T2
|
|
srl D,32-11,D
|
|
or D,T2,D
|
|
add D,A,D !=
|
|
|
|
xor D,A,T1
|
|
sethi %hi(0xd4ef3085),T2
|
|
xor T1,B,T1
|
|
or T2,%lo(0xd4ef3085),T2 !=
|
|
add T1,R3,T1
|
|
!pre-LOADed X(6),R6
|
|
add T1,T2,T1
|
|
add C,T1,C
|
|
sll C,16,T2 !=
|
|
srl C,32-16,C
|
|
or C,T2,C
|
|
add C,D,C
|
|
|
|
xor C,D,T1 !=
|
|
sethi %hi(0x04881d05),T2
|
|
xor T1,A,T1
|
|
or T2,%lo(0x04881d05),T2
|
|
add T1,R6,T1 !=
|
|
!pre-LOADed X(9),R9
|
|
add T1,T2,T1
|
|
add B,T1,B
|
|
sll B,23,T2
|
|
srl B,32-23,B !=
|
|
or B,T2,B
|
|
add B,C,B
|
|
|
|
xor B,C,T1
|
|
sethi %hi(0xd9d4d039),T2 !=
|
|
xor T1,D,T1
|
|
or T2,%lo(0xd9d4d039),T2
|
|
add T1,R9,T1
|
|
!pre-LOADed X(12),R12
|
|
add T1,T2,T1 !=
|
|
add A,T1,A
|
|
sll A,4,T2
|
|
srl A,32-4,A
|
|
or A,T2,A !=
|
|
add A,B,A
|
|
|
|
xor A,B,T1
|
|
sethi %hi(0xe6db99e5),T2
|
|
xor T1,C,T1 !=
|
|
or T2,%lo(0xe6db99e5),T2
|
|
add T1,R12,T1
|
|
LOAD X(15),RX
|
|
add T1,T2,T1 !=
|
|
add D,T1,D
|
|
sll D,11,T2
|
|
srl D,32-11,D
|
|
or D,T2,D !=
|
|
add D,A,D
|
|
|
|
xor D,A,T1
|
|
sethi %hi(0x1fa27cf8),T2
|
|
xor T1,B,T1 !=
|
|
or T2,%lo(0x1fa27cf8),T2
|
|
add T1,RX,T1
|
|
!pre-LOADed X(2),R2
|
|
add T1,T2,T1
|
|
add C,T1,C !=
|
|
sll C,16,T2
|
|
srl C,32-16,C
|
|
or C,T2,C
|
|
add C,D,C !=
|
|
|
|
xor C,D,T1
|
|
sethi %hi(0xc4ac5665),T2
|
|
xor T1,A,T1
|
|
or T2,%lo(0xc4ac5665),T2 !=
|
|
add T1,R2,T1
|
|
!pre-LOADed X(0),R0
|
|
add T1,T2,T1
|
|
add B,T1,B
|
|
sll B,23,T2 !=
|
|
srl B,32-23,B
|
|
or B,T2,B
|
|
add B,C,B
|
|
|
|
!!!!!!!!Round 3
|
|
|
|
orn B,D,T1 !=
|
|
sethi %hi(0xf4292244),T2
|
|
xor T1,C,T1
|
|
or T2,%lo(0xf4292244),T2
|
|
add T1,R0,T1 !=
|
|
!pre-LOADed X(7),R7
|
|
add T1,T2,T1
|
|
add A,T1,A
|
|
sll A,6,T2
|
|
srl A,32-6,A !=
|
|
or A,T2,A
|
|
add A,B,A
|
|
|
|
orn A,C,T1
|
|
sethi %hi(0x432aff97),T2 !=
|
|
xor T1,B,T1
|
|
or T2,%lo(0x432aff97),T2
|
|
LOAD X(14),RX
|
|
add T1,R7,T1 !=
|
|
add T1,T2,T1
|
|
add D,T1,D
|
|
sll D,10,T2
|
|
srl D,32-10,D !=
|
|
or D,T2,D
|
|
add D,A,D
|
|
|
|
orn D,B,T1
|
|
sethi %hi(0xab9423a7),T2 !=
|
|
xor T1,A,T1
|
|
or T2,%lo(0xab9423a7),T2
|
|
add T1,RX,T1
|
|
!pre-LOADed X(5),R5
|
|
add T1,T2,T1 !=
|
|
add C,T1,C
|
|
sll C,15,T2
|
|
srl C,32-15,C
|
|
or C,T2,C !=
|
|
add C,D,C
|
|
|
|
orn C,A,T1
|
|
sethi %hi(0xfc93a039),T2
|
|
xor T1,D,T1 !=
|
|
or T2,%lo(0xfc93a039),T2
|
|
add T1,R5,T1
|
|
!pre-LOADed X(12),R12
|
|
add T1,T2,T1
|
|
add B,T1,B !=
|
|
sll B,21,T2
|
|
srl B,32-21,B
|
|
or B,T2,B
|
|
add B,C,B !=
|
|
|
|
orn B,D,T1
|
|
sethi %hi(0x655b59c3),T2
|
|
xor T1,C,T1
|
|
or T2,%lo(0x655b59c3),T2 !=
|
|
add T1,R12,T1
|
|
!pre-LOADed X(3),R3
|
|
add T1,T2,T1
|
|
add A,T1,A
|
|
sll A,6,T2 !=
|
|
srl A,32-6,A
|
|
or A,T2,A
|
|
add A,B,A
|
|
|
|
orn A,C,T1 !=
|
|
sethi %hi(0x8f0ccc92),T2
|
|
xor T1,B,T1
|
|
or T2,%lo(0x8f0ccc92),T2
|
|
add T1,R3,T1 !=
|
|
!pre-LOADed X(10),R10
|
|
add T1,T2,T1
|
|
add D,T1,D
|
|
sll D,10,T2
|
|
srl D,32-10,D !=
|
|
or D,T2,D
|
|
add D,A,D
|
|
|
|
orn D,B,T1
|
|
sethi %hi(0xffeff47d),T2 !=
|
|
xor T1,A,T1
|
|
or T2,%lo(0xffeff47d),T2
|
|
add T1,R10,T1
|
|
!pre-LOADed X(1),R1
|
|
add T1,T2,T1 !=
|
|
add C,T1,C
|
|
sll C,15,T2
|
|
srl C,32-15,C
|
|
or C,T2,C !=
|
|
add C,D,C
|
|
|
|
orn C,A,T1
|
|
sethi %hi(0x85845dd1),T2
|
|
xor T1,D,T1 !=
|
|
or T2,%lo(0x85845dd1),T2
|
|
add T1,R1,T1
|
|
!pre-LOADed X(8),R8
|
|
add T1,T2,T1
|
|
add B,T1,B !=
|
|
sll B,21,T2
|
|
srl B,32-21,B
|
|
or B,T2,B
|
|
add B,C,B !=
|
|
|
|
orn B,D,T1
|
|
sethi %hi(0x6fa87e4f),T2
|
|
xor T1,C,T1
|
|
or T2,%lo(0x6fa87e4f),T2 !=
|
|
add T1,R8,T1
|
|
LOAD X(15),RX
|
|
add T1,T2,T1
|
|
add A,T1,A !=
|
|
sll A,6,T2
|
|
srl A,32-6,A
|
|
or A,T2,A
|
|
add A,B,A !=
|
|
|
|
orn A,C,T1
|
|
sethi %hi(0xfe2ce6e0),T2
|
|
xor T1,B,T1
|
|
or T2,%lo(0xfe2ce6e0),T2 !=
|
|
add T1,RX,T1
|
|
!pre-LOADed X(6),R6
|
|
add T1,T2,T1
|
|
add D,T1,D
|
|
sll D,10,T2 !=
|
|
srl D,32-10,D
|
|
or D,T2,D
|
|
add D,A,D
|
|
|
|
orn D,B,T1 !=
|
|
sethi %hi(0xa3014314),T2
|
|
xor T1,A,T1
|
|
or T2,%lo(0xa3014314),T2
|
|
add T1,R6,T1 !=
|
|
!pre-LOADed X(13),R13
|
|
add T1,T2,T1
|
|
add C,T1,C
|
|
sll C,15,T2
|
|
srl C,32-15,C !=
|
|
or C,T2,C
|
|
add C,D,C
|
|
|
|
orn C,A,T1
|
|
sethi %hi(0x4e0811a1),T2 !=
|
|
xor T1,D,T1
|
|
or T2,%lo(0x4e0811a1),T2
|
|
!pre-LOADed X(4),R4
|
|
ld [Aptr],Aval
|
|
add T1,R13,T1 !=
|
|
add T1,T2,T1
|
|
add B,T1,B
|
|
sll B,21,T2
|
|
srl B,32-21,B !=
|
|
or B,T2,B
|
|
add B,C,B
|
|
|
|
orn B,D,T1
|
|
sethi %hi(0xf7537e82),T2 !=
|
|
xor T1,C,T1
|
|
or T2,%lo(0xf7537e82),T2
|
|
!pre-LOADed X(11),R11
|
|
ld [Dptr],Dval
|
|
add T1,R4,T1 !=
|
|
add T1,T2,T1
|
|
add A,T1,A
|
|
sll A,6,T2
|
|
srl A,32-6,A !=
|
|
or A,T2,A
|
|
add A,B,A
|
|
|
|
orn A,C,T1
|
|
sethi %hi(0xbd3af235),T2 !=
|
|
xor T1,B,T1
|
|
or T2,%lo(0xbd3af235),T2
|
|
!pre-LOADed X(2),R2
|
|
ld [Cptr],Cval
|
|
add T1,R11,T1 !=
|
|
add T1,T2,T1
|
|
add D,T1,D
|
|
sll D,10,T2
|
|
srl D,32-10,D !=
|
|
or D,T2,D
|
|
add D,A,D
|
|
|
|
orn D,B,T1
|
|
sethi %hi(0x2ad7d2bb),T2 !=
|
|
xor T1,A,T1
|
|
or T2,%lo(0x2ad7d2bb),T2
|
|
!pre-LOADed X(9),R9
|
|
ld [Bptr],Bval
|
|
add T1,R2,T1 !=
|
|
add Aval,A,Aval
|
|
add T1,T2,T1
|
|
st Aval,[Aptr]
|
|
add C,T1,C !=
|
|
sll C,15,T2
|
|
add Dval,D,Dval
|
|
srl C,32-15,C
|
|
or C,T2,C !=
|
|
st Dval,[Dptr]
|
|
add C,D,C
|
|
|
|
orn C,A,T1
|
|
sethi %hi(0xeb86d391),T2 !=
|
|
xor T1,D,T1
|
|
or T2,%lo(0xeb86d391),T2
|
|
add T1,R9,T1
|
|
!pre-LOADed X(0),R0
|
|
mov Aval,A !=
|
|
add T1,T2,T1
|
|
mov Dval,D
|
|
add B,T1,B
|
|
sll B,21,T2 !=
|
|
add Cval,C,Cval
|
|
srl B,32-21,B
|
|
st Cval,[Cptr]
|
|
or B,T2,B !=
|
|
add B,C,B
|
|
|
|
deccc %i2
|
|
mov Cval,C
|
|
add B,Bval,B !=
|
|
inc 64,%i1
|
|
nop
|
|
st B,[Bptr]
|
|
nop !=
|
|
|
|
#ifdef OPENSSL_SYSNAME_ULTRASPARC
|
|
bg,a,pt %icc,.Lmd5_block_loop
|
|
#else
|
|
bg,a .Lmd5_block_loop
|
|
#endif
|
|
LOAD X(0),R0
|
|
|
|
#ifdef ASI_PRIMARY_LITTLE
|
|
wr %g0,%o7,%asi
|
|
#endif
|
|
ret
|
|
restore %g0,0,%o0
|
|
|
|
.type md5_block,#function
|
|
.size md5_block,(.-md5_block)
|