ecb044db58
[Note that in master declaration is different.] RT#4568 Reviewed-by: Rich Salz <rsalz@openssl.org>
96 lines
3.3 KiB
Text
96 lines
3.3 KiB
Text
=pod
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=head1 NAME
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OPENSSL_ia32cap, OPENSSL_ia32cap_loc - the IA-32 processor capabilities vector
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=head1 SYNOPSIS
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unsigned long *OPENSSL_ia32cap_loc(void);
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#define OPENSSL_ia32cap ((OPENSSL_ia32cap_loc())[0])
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=head1 DESCRIPTION
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Value returned by OPENSSL_ia32cap_loc() is address of a variable
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containing IA-32 processor capabilities bit vector as it appears in
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EDX:ECX register pair after executing CPUID instruction with EAX=1
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input value (see Intel Application Note #241618). Naturally it's
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meaningful on x86 and x86_64 platforms only. The variable is normally
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set up automatically upon toolkit initialization, but can be
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manipulated afterwards to modify crypto library behaviour. For the
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moment of this writing following bits are significant:
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=over
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=item bit #4 denoting presence of Time-Stamp Counter.
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=item bit #19 denoting availability of CLFLUSH instruction;
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=item bit #20, reserved by Intel, is used to choose among RC4 code paths;
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=item bit #23 denoting MMX support;
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=item bit #24, FXSR bit, denoting availability of XMM registers;
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=item bit #25 denoting SSE support;
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=item bit #26 denoting SSE2 support;
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=item bit #28 denoting Hyperthreading, which is used to distinguish
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cores with shared cache;
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=item bit #30, reserved by Intel, denotes specifically Intel CPUs;
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=item bit #33 denoting availability of PCLMULQDQ instruction;
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=item bit #41 denoting SSSE3, Supplemental SSE3, support;
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=item bit #43 denoting AMD XOP support (forced to zero on non-AMD CPUs);
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=item bit #57 denoting AES-NI instruction set extension;
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=item bit #59, OSXSAVE bit, denoting availability of YMM registers;
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=item bit #60 denoting AVX extension;
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=item bit #62 denoting availability of RDRAND instruction;
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=back
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For example, clearing bit #26 at run-time disables high-performance
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SSE2 code present in the crypto library, while clearing bit #24
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disables SSE2 code operating on 128-bit XMM register bank. You might
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have to do the latter if target OpenSSL application is executed on SSE2
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capable CPU, but under control of OS that does not enable XMM
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registers. Even though you can manipulate the value programmatically,
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you most likely will find it more appropriate to set up an environment
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variable with the same name prior starting target application, e.g. on
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Intel P4 processor 'env OPENSSL_ia32cap=0x16980010 apps/openssl', or
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better yet 'env OPENSSL_ia32cap=~0x1000000 apps/openssl' to achieve same
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effect without modifying the application source code. Alternatively you
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can reconfigure the toolkit with no-sse2 option and recompile.
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Less intuitive is clearing bit #28. The truth is that it's not copied
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from CPUID output verbatim, but is adjusted to reflect whether or not
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the data cache is actually shared between logical cores. This in turn
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affects the decision on whether or not expensive countermeasures
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against cache-timing attacks are applied, most notably in AES assembler
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module.
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The vector is further extended with EBX value returned by CPUID with
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EAX=7 and ECX=0 as input. Following bits are significant:
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=over
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=item bit #64+3 denoting availability of BMI1 instructions, e.g. ANDN;
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=item bit #64+5 denoting availability of AVX2 instructions;
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=item bit #64+8 denoting availability of BMI2 instructions, e.g. MUXL
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and RORX;
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=item bit #64+18 denoting availability of RDSEED instruction;
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=item bit #64+19 denoting availability of ADCX and ADOX instructions;
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=back
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