1e10aee2a7
PR: 3474
Reviewed-by: Kurt Roeckx <kurt@openssl.org>
(cherry picked from commit 6696203963)
219 lines
5.2 KiB
ArmAsm
219 lines
5.2 KiB
ArmAsm
#include "arm_arch.h"
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.text
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.code 32
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@ Special note about using .byte directives to encode instructions.
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@ Initial reason for hand-coding instructions was to allow module to
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@ be compilable by legacy tool-chains. At later point it was pointed
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@ out that since ARMv7, instructions are always encoded in little-endian
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@ order, therefore one has to opt for endian-neutral presentation.
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@ Contemporary tool-chains offer .inst directive for this purpose,
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@ but not legacy ones. Therefore .byte. But there is an exception,
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@ namely ARMv7-R profile still allows for big-endian encoding even for
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@ instructions. This raises the question what if probe instructions
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@ appear executable to such processor operating in big-endian order?
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@ They have to be chosen in a way that avoids this problem. As failed
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@ NEON probe disables a number of other probes we have to ensure that
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@ only NEON probe instruction doesn't appear executable in big-endian
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@ order, therefore 'vorr q8,q8,q8', and not some other register. The
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@ only probe that is not bypassed on failed NEON probe is _armv7_tick,
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@ where you'll spot 'mov r0,r6' that serves this purpose. Basic idea is
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@ that if fetched in alternative byte oder instruction should crash to
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@ denote lack of probed capability...
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.align 5
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.global _armv7_neon_probe
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.type _armv7_neon_probe,%function
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_armv7_neon_probe:
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.byte 0xf0,0x01,0x60,0xf2 @ vorr q8,q8,q8
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.byte 0x1e,0xff,0x2f,0xe1 @ bx lr
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.size _armv7_neon_probe,.-_armv7_neon_probe
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.global _armv7_tick
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.type _armv7_tick,%function
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_armv7_tick:
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.byte 0x06,0x00,0xa0,0xe1 @ mov r0,r6
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.byte 0x1e,0x0f,0x51,0xec @ mrrc p15,1,r0,r1,c14 @ CNTVCT
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.byte 0x1e,0xff,0x2f,0xe1 @ bx lr
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nop
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.size _armv7_tick,.-_armv7_tick
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.global _armv8_aes_probe
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.type _armv8_aes_probe,%function
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_armv8_aes_probe:
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.byte 0x00,0x03,0xb0,0xf3 @ aese.8 q0,q0
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.byte 0x1e,0xff,0x2f,0xe1 @ bx lr
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.size _armv8_aes_probe,.-_armv8_aes_probe
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.global _armv8_sha1_probe
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.type _armv8_sha1_probe,%function
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_armv8_sha1_probe:
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.byte 0x40,0x0c,0x00,0xf2 @ sha1c.32 q0,q0,q0
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.byte 0x1e,0xff,0x2f,0xe1 @ bx lr
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.size _armv8_sha1_probe,.-_armv8_sha1_probe
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.global _armv8_sha256_probe
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.type _armv8_sha256_probe,%function
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_armv8_sha256_probe:
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.byte 0x40,0x0c,0x00,0xf3 @ sha256h.32 q0,q0,q0
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.byte 0x1e,0xff,0x2f,0xe1 @ bx lr
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.size _armv8_sha256_probe,.-_armv8_sha256_probe
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.global _armv8_pmull_probe
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.type _armv8_pmull_probe,%function
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_armv8_pmull_probe:
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.byte 0x00,0x0e,0xa0,0xf2 @ vmull.p64 q0,d0,d0
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.byte 0x1e,0xff,0x2f,0xe1 @ bx lr
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.size _armv8_pmull_probe,.-_armv8_pmull_probe
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.align 5
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.global OPENSSL_atomic_add
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.type OPENSSL_atomic_add,%function
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OPENSSL_atomic_add:
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#if __ARM_ARCH__>=6
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.Ladd: ldrex r2,[r0]
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add r3,r2,r1
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strex r2,r3,[r0]
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cmp r2,#0
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bne .Ladd
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mov r0,r3
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bx lr
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#else
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stmdb sp!,{r4-r6,lr}
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ldr r2,.Lspinlock
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adr r3,.Lspinlock
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mov r4,r0
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mov r5,r1
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add r6,r3,r2 @ &spinlock
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b .+8
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.Lspin: bl sched_yield
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mov r0,#-1
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swp r0,r0,[r6]
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cmp r0,#0
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bne .Lspin
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ldr r2,[r4]
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add r2,r2,r5
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str r2,[r4]
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str r0,[r6] @ release spinlock
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ldmia sp!,{r4-r6,lr}
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tst lr,#1
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moveq pc,lr
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.word 0xe12fff1e @ bx lr
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#endif
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.size OPENSSL_atomic_add,.-OPENSSL_atomic_add
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.global OPENSSL_cleanse
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.type OPENSSL_cleanse,%function
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OPENSSL_cleanse:
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eor ip,ip,ip
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cmp r1,#7
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subhs r1,r1,#4
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bhs .Lot
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cmp r1,#0
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beq .Lcleanse_done
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.Little:
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strb ip,[r0],#1
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subs r1,r1,#1
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bhi .Little
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b .Lcleanse_done
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.Lot: tst r0,#3
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beq .Laligned
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strb ip,[r0],#1
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sub r1,r1,#1
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b .Lot
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.Laligned:
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str ip,[r0],#4
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subs r1,r1,#4
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bhs .Laligned
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adds r1,r1,#4
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bne .Little
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.Lcleanse_done:
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#if __ARM_ARCH__>=5
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bx lr
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#else
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tst lr,#1
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moveq pc,lr
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.word 0xe12fff1e @ bx lr
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#endif
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.size OPENSSL_cleanse,.-OPENSSL_cleanse
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.global OPENSSL_wipe_cpu
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.type OPENSSL_wipe_cpu,%function
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OPENSSL_wipe_cpu:
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ldr r0,.LOPENSSL_armcap
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adr r1,.LOPENSSL_armcap
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ldr r0,[r1,r0]
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eor r2,r2,r2
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eor r3,r3,r3
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eor ip,ip,ip
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tst r0,#1
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beq .Lwipe_done
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.byte 0x50,0x01,0x00,0xf3 @ veor q0, q0, q0
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.byte 0x52,0x21,0x02,0xf3 @ veor q1, q1, q1
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.byte 0x54,0x41,0x04,0xf3 @ veor q2, q2, q2
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.byte 0x56,0x61,0x06,0xf3 @ veor q3, q3, q3
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.byte 0xf0,0x01,0x40,0xf3 @ veor q8, q8, q8
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.byte 0xf2,0x21,0x42,0xf3 @ veor q9, q9, q9
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.byte 0xf4,0x41,0x44,0xf3 @ veor q10, q10, q10
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.byte 0xf6,0x61,0x46,0xf3 @ veor q11, q11, q11
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.byte 0xf8,0x81,0x48,0xf3 @ veor q12, q12, q12
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.byte 0xfa,0xa1,0x4a,0xf3 @ veor q13, q13, q13
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.byte 0xfc,0xc1,0x4c,0xf3 @ veor q14, q14, q14
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.byte 0xfe,0xe1,0x4e,0xf3 @ veor q14, q14, q14
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.Lwipe_done:
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mov r0,sp
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#if __ARM_ARCH__>=5
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bx lr
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#else
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tst lr,#1
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moveq pc,lr
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.word 0xe12fff1e @ bx lr
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#endif
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.size OPENSSL_wipe_cpu,.-OPENSSL_wipe_cpu
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.global OPENSSL_instrument_bus
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.type OPENSSL_instrument_bus,%function
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OPENSSL_instrument_bus:
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eor r0,r0,r0
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#if __ARM_ARCH__>=5
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bx lr
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#else
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tst lr,#1
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moveq pc,lr
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.word 0xe12fff1e @ bx lr
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#endif
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.size OPENSSL_instrument_bus,.-OPENSSL_instrument_bus
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.global OPENSSL_instrument_bus2
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.type OPENSSL_instrument_bus2,%function
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OPENSSL_instrument_bus2:
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eor r0,r0,r0
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#if __ARM_ARCH__>=5
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bx lr
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#else
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tst lr,#1
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moveq pc,lr
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.word 0xe12fff1e @ bx lr
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#endif
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.size OPENSSL_instrument_bus2,.-OPENSSL_instrument_bus2
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.align 5
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.LOPENSSL_armcap:
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.word OPENSSL_armcap_P-.LOPENSSL_armcap
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#if __ARM_ARCH__>=6
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.align 5
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#else
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.Lspinlock:
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.word atomic_add_spinlock-.Lspinlock
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.align 5
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.data
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.align 2
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atomic_add_spinlock:
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.word 0
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#endif
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.comm OPENSSL_armcap_P,4,4
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.hidden OPENSSL_armcap_P
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