366 lines
8.4 KiB
Raku
Executable file
366 lines
8.4 KiB
Raku
Executable file
#!/usr/bin/env perl
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#
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# ====================================================================
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# Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
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# project. The module is, however, dual licensed under OpenSSL and
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# CRYPTOGAMS licenses depending on where you obtain it. For further
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# details see http://www.openssl.org/~appro/cryptogams/.
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# ====================================================================
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#
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# 2.22x RC4 tune-up:-) It should be noted though that my hand [as in
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# "hand-coded assembler"] doesn't stand for the whole improvement
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# coefficient. It turned out that eliminating RC4_CHAR from config
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# line results in ~40% improvement (yes, even for C implementation).
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# Presumably it has everything to do with AMD cache architecture and
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# RAW or whatever penalties. Once again! The module *requires* config
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# line *without* RC4_CHAR! As for coding "secret," I bet on partial
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# register arithmetics. For example instead of 'inc %r8; and $255,%r8'
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# I simply 'inc %r8b'. Even though optimization manual discourages
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# to operate on partial registers, it turned out to be the best bet.
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# At least for AMD... How IA32E would perform remains to be seen...
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# As was shown by Marc Bevand reordering of couple of load operations
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# results in even higher performance gain of 3.3x:-) At least on
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# Opteron... For reference, 1x in this case is RC4_CHAR C-code
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# compiled with gcc 3.3.2, which performs at ~54MBps per 1GHz clock.
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# Latter means that if you want to *estimate* what to expect from
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# *your* Opteron, then multiply 54 by 3.3 and clock frequency in GHz.
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# Intel P4 EM64T core was found to run the AMD64 code really slow...
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# The only way to achieve comparable performance on P4 was to keep
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# RC4_CHAR. Kind of ironic, huh? As it's apparently impossible to
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# compose blended code, which would perform even within 30% marginal
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# on either AMD and Intel platforms, I implement both cases. See
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# rc4_skey.c for further details...
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# P4 EM64T core appears to be "allergic" to 64-bit inc/dec. Replacing
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# those with add/sub results in 50% performance improvement of folded
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# loop...
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# As was shown by Zou Nanhai loop unrolling can improve Intel EM64T
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# performance by >30% [unlike P4 32-bit case that is]. But this is
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# provided that loads are reordered even more aggressively! Both code
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# pathes, AMD64 and EM64T, reorder loads in essentially same manner
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# as my IA-64 implementation. On Opteron this resulted in modest 5%
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# improvement [I had to test it], while final Intel P4 performance
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# achieves respectful 432MBps on 2.8GHz processor now. For reference.
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# If executed on Xeon, current RC4_CHAR code-path is 2.7x faster than
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# RC4_INT code-path. While if executed on Opteron, it's only 25%
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# slower than the RC4_INT one [meaning that if CPU <20>-arch detection
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# is not implemented, then this final RC4_CHAR code-path should be
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# preferred, as it provides better *all-round* performance].
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# Intel Core2 was observed to perform poorly on both code paths:-( It
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# apparently suffers from some kind of partial register stall, which
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# occurs in 64-bit mode only [as virtually identical 32-bit loop was
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# observed to outperform 64-bit one by almost 50%]. Adding two movzb to
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# cloop1 boosts its performance by 80%! This loop appears to be optimal
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# fit for Core2 and therefore the code was modified to skip cloop8 on
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# this CPU.
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$output=shift;
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$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
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( $xlate="${dir}x86_64-xlate.pl" and -f $xlate ) or
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( $xlate="${dir}../../perlasm/x86_64-xlate.pl" and -f $xlate) or
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die "can't locate x86_64-xlate.pl";
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open STDOUT,"| $^X $xlate $output";
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$dat="%rdi"; # arg1
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$len="%rsi"; # arg2
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$inp="%rdx"; # arg3
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$out="%rcx"; # arg4
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@XX=("%r8","%r10");
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@TX=("%r9","%r11");
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$YY="%r12";
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$TY="%r13";
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$code=<<___;
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.text
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.globl RC4
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.type RC4,\@function,4
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.align 16
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RC4: or $len,$len
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jne .Lentry
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ret
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.Lentry:
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push %r12
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push %r13
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add \$8,$dat
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movl -8($dat),$XX[0]#d
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movl -4($dat),$YY#d
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cmpl \$-1,256($dat)
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je .LRC4_CHAR
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inc $XX[0]#b
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movl ($dat,$XX[0],4),$TX[0]#d
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test \$-8,$len
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jz .Lloop1
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jmp .Lloop8
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.align 16
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.Lloop8:
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___
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for ($i=0;$i<8;$i++) {
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$code.=<<___;
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add $TX[0]#b,$YY#b
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mov $XX[0],$XX[1]
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movl ($dat,$YY,4),$TY#d
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ror \$8,%rax # ror is redundant when $i=0
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inc $XX[1]#b
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movl ($dat,$XX[1],4),$TX[1]#d
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cmp $XX[1],$YY
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movl $TX[0]#d,($dat,$YY,4)
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cmove $TX[0],$TX[1]
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movl $TY#d,($dat,$XX[0],4)
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add $TX[0]#b,$TY#b
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movb ($dat,$TY,4),%al
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___
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push(@TX,shift(@TX)); push(@XX,shift(@XX)); # "rotate" registers
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}
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$code.=<<___;
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ror \$8,%rax
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sub \$8,$len
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xor ($inp),%rax
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add \$8,$inp
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mov %rax,($out)
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add \$8,$out
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test \$-8,$len
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jnz .Lloop8
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cmp \$0,$len
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jne .Lloop1
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___
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$code.=<<___;
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.Lexit:
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sub \$1,$XX[0]#b
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movl $XX[0]#d,-8($dat)
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movl $YY#d,-4($dat)
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pop %r13
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pop %r12
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ret
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.align 16
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.Lloop1:
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add $TX[0]#b,$YY#b
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movl ($dat,$YY,4),$TY#d
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movl $TX[0]#d,($dat,$YY,4)
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movl $TY#d,($dat,$XX[0],4)
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add $TY#b,$TX[0]#b
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inc $XX[0]#b
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movl ($dat,$TX[0],4),$TY#d
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movl ($dat,$XX[0],4),$TX[0]#d
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xorb ($inp),$TY#b
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inc $inp
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movb $TY#b,($out)
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inc $out
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dec $len
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jnz .Lloop1
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jmp .Lexit
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.align 16
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.LRC4_CHAR:
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add \$1,$XX[0]#b
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movzb ($dat,$XX[0]),$TX[0]#d
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test \$-8,$len
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jz .Lcloop1
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cmp \$0,260($dat)
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jnz .Lcloop1
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push %rbx
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jmp .Lcloop8
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.align 16
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.Lcloop8:
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mov ($inp),%eax
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mov 4($inp),%ebx
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___
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# unroll 2x4-wise, because 64-bit rotates kill Intel P4...
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for ($i=0;$i<4;$i++) {
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$code.=<<___;
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add $TX[0]#b,$YY#b
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lea 1($XX[0]),$XX[1]
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movzb ($dat,$YY),$TY#d
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movzb $XX[1]#b,$XX[1]#d
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movzb ($dat,$XX[1]),$TX[1]#d
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movb $TX[0]#b,($dat,$YY)
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cmp $XX[1],$YY
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movb $TY#b,($dat,$XX[0])
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jne .Lcmov$i # Intel cmov is sloooow...
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mov $TX[0],$TX[1]
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.Lcmov$i:
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add $TX[0]#b,$TY#b
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xor ($dat,$TY),%al
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ror \$8,%eax
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___
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push(@TX,shift(@TX)); push(@XX,shift(@XX)); # "rotate" registers
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}
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for ($i=4;$i<8;$i++) {
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$code.=<<___;
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add $TX[0]#b,$YY#b
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lea 1($XX[0]),$XX[1]
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movzb ($dat,$YY),$TY#d
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movzb $XX[1]#b,$XX[1]#d
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movzb ($dat,$XX[1]),$TX[1]#d
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movb $TX[0]#b,($dat,$YY)
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cmp $XX[1],$YY
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movb $TY#b,($dat,$XX[0])
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jne .Lcmov$i # Intel cmov is sloooow...
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mov $TX[0],$TX[1]
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.Lcmov$i:
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add $TX[0]#b,$TY#b
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xor ($dat,$TY),%bl
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ror \$8,%ebx
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___
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push(@TX,shift(@TX)); push(@XX,shift(@XX)); # "rotate" registers
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}
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$code.=<<___;
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lea -8($len),$len
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mov %eax,($out)
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lea 8($inp),$inp
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mov %ebx,4($out)
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lea 8($out),$out
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test \$-8,$len
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jnz .Lcloop8
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pop %rbx
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cmp \$0,$len
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jne .Lcloop1
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jmp .Lexit
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___
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$code.=<<___;
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.align 16
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.Lcloop1:
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add $TX[0]#b,$YY#b
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movzb ($dat,$YY),$TY#d
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movb $TX[0]#b,($dat,$YY)
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movb $TY#b,($dat,$XX[0])
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add $TX[0]#b,$TY#b
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add \$1,$XX[0]#b
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movzb $TY#b,$TY#d
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movzb $XX[0]#b,$XX[0]#d
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movzb ($dat,$TY),$TY#d
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movzb ($dat,$XX[0]),$TX[0]#d
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xorb ($inp),$TY#b
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lea 1($inp),$inp
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movb $TY#b,($out)
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lea 1($out),$out
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sub \$1,$len
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jnz .Lcloop1
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jmp .Lexit
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.size RC4,.-RC4
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___
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$idx="%r8";
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$ido="%r9";
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$code.=<<___;
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.extern OPENSSL_ia32cap_P
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.globl RC4_set_key
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.type RC4_set_key,\@function,3
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.align 16
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RC4_set_key:
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lea 8($dat),$dat
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lea ($inp,$len),$inp
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neg $len
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mov $len,%rcx
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xor %eax,%eax
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xor $ido,$ido
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xor %r10,%r10
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xor %r11,%r11
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mov OPENSSL_ia32cap_P(%rip),$idx#d
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bt \$20,$idx#d
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jnc .Lw1stloop
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bt \$30,$idx#d
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setc $ido#b
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mov $ido#d,260($dat)
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jmp .Lc1stloop
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.align 16
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.Lw1stloop:
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mov %eax,($dat,%rax,4)
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add \$1,%al
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jnc .Lw1stloop
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xor $ido,$ido
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xor $idx,$idx
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.align 16
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.Lw2ndloop:
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mov ($dat,$ido,4),%r10d
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add ($inp,$len,1),$idx#b
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add %r10b,$idx#b
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add \$1,$len
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mov ($dat,$idx,4),%r11d
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cmovz %rcx,$len
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mov %r10d,($dat,$idx,4)
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mov %r11d,($dat,$ido,4)
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add \$1,$ido#b
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jnc .Lw2ndloop
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jmp .Lexit_key
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.align 16
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.Lc1stloop:
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mov %al,($dat,%rax)
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add \$1,%al
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jnc .Lc1stloop
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xor $ido,$ido
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xor $idx,$idx
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.align 16
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.Lc2ndloop:
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mov ($dat,$ido),%r10b
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add ($inp,$len),$idx#b
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add %r10b,$idx#b
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add \$1,$len
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mov ($dat,$idx),%r11b
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jnz .Lcnowrap
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mov %rcx,$len
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.Lcnowrap:
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mov %r10b,($dat,$idx)
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mov %r11b,($dat,$ido)
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add \$1,$ido#b
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jnc .Lc2ndloop
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movl \$-1,256($dat)
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.align 16
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.Lexit_key:
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xor %eax,%eax
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mov %eax,-8($dat)
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mov %eax,-4($dat)
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ret
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.size RC4_set_key,.-RC4_set_key
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.globl RC4_options
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.type RC4_options,\@function,0
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.align 16
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RC4_options:
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.picmeup %rax
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lea .Lopts-.(%rax),%rax
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mov OPENSSL_ia32cap_P(%rip),%edx
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bt \$20,%edx
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jnc .Ldone
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add \$12,%rax
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bt \$30,%edx
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jnc .Ldone
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add \$13,%rax
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.Ldone:
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ret
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.align 64
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.Lopts:
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.asciz "rc4(8x,int)"
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.asciz "rc4(8x,char)"
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.asciz "rc4(1x,char)"
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.asciz "RC4 for x86_64, CRYPTOGAMS by <appro\@openssl.org>"
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.align 64
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.size RC4_options,.-RC4_options
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___
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$code =~ s/#([bwd])/$1/gm;
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$code =~ s/RC4_set_key/private_RC4_set_key/g if ($ENV{FIPSCANLIB} ne "");
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print $code;
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close STDOUT;
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