604 lines
13 KiB
Perl
Executable file
604 lines
13 KiB
Perl
Executable file
#!/usr/bin/env perl
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#
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# ====================================================================
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# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
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# project. The module is, however, dual licensed under OpenSSL and
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# CRYPTOGAMS licenses depending on where you obtain it. For further
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# details see http://www.openssl.org/~appro/cryptogams/.
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# ====================================================================
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#
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# This module implements support for ARMv8 AES instructions. The
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# module is endian-agnostic in sense that it supports both big- and
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# little-endian cases. As does it support both 32- and 64-bit modes
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# of operation. Latter is achieved by limiting amount of utilized
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# registers to 16, which implies additional instructions. This has
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# no effect on mighty Apple A7, as results are literally equal to
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# the theoretical estimates. It remains to be seen how does it
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# affect other platforms...
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#
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# Performance in cycles per byte processed with 128-bit key:
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#
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# CBC enc CBC dec
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# Apple A7 2.39 1.20
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$flavour = shift;
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$prefix="AES";
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$code=".text\n";
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$code.=".arch armv8-a+crypto\n" if ($flavour =~ /64/);
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$code.=".fpu neon\n.code 32\n" if ($flavour !~ /64/);
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# Assembler mnemonics are an eclectic mix of 32- and 64-bit syntax,
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# NEON is mostly 32-bit mnemonics, integer - mostly 64. Goal is to
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# maintain both 32- and 64-bit codes within single module and
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# transliterate common code to either flavour with regex vodoo.
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#
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{{{
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my ($inp,$bits,$out,$ptr,$rounds)=("x0","w1","x2","x3","w12");
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my ($zero,$rcon,$mask,$in0,$in1,$tmp,$key)=
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$flavour=~/64/? map("q$_",(0..6)) : map("q$_",(0..3,8..10));
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$code.=<<___;
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.align 5
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rcon:
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.long 0x01,0x01,0x01,0x01
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.long 0x0c0f0e0d,0x0c0f0e0d,0x0c0f0e0d,0x0c0f0e0d // rotate-n-splat
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.long 0x1b,0x1b,0x1b,0x1b
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.globl ${prefix}_set_encrypt_key
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.type ${prefix}_set_encrypt_key,%function
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.align 5
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${prefix}_set_encrypt_key:
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.Lenc_key:
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___
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$code.=<<___ if ($flavour =~ /64/);
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stp x29,x30,[sp,#-16]!
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add x29,sp,#0
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___
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$code.=<<___;
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adr $ptr,rcon
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cmp $bits,#192
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veor $zero,$zero,$zero
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vld1.8 {$in0},[$inp],#16
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mov $bits,#8 // reuse $bits
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vld1.32 {$rcon,$mask},[$ptr],#32
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b.lt .Loop128
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b.eq .L192
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b .L256
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.align 4
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.Loop128:
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vtbl.8 $key,{$in0},$mask
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vext.8 $tmp,$zero,$in0,#12
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vst1.32 {$in0},[$out],#16
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aese $key,$zero
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subs $bits,$bits,#1
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veor $in0,$in0,$tmp
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vext.8 $tmp,$zero,$tmp,#12
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veor $in0,$in0,$tmp
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vext.8 $tmp,$zero,$tmp,#12
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veor $key,$key,$rcon
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veor $in0,$in0,$tmp
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vshl.u8 $rcon,$rcon,#1
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veor $in0,$in0,$key
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b.ne .Loop128
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vld1.32 {$rcon},[$ptr]
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vtbl.8 $key,{$in0},$mask
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vext.8 $tmp,$zero,$in0,#12
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vst1.32 {$in0},[$out],#16
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aese $key,$zero
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veor $in0,$in0,$tmp
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vext.8 $tmp,$zero,$tmp,#12
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veor $in0,$in0,$tmp
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vext.8 $tmp,$zero,$tmp,#12
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veor $key,$key,$rcon
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veor $in0,$in0,$tmp
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vshl.u8 $rcon,$rcon,#1
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veor $in0,$in0,$key
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vtbl.8 $key,{$in0},$mask
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vext.8 $tmp,$zero,$in0,#12
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vst1.32 {$in0},[$out],#16
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aese $key,$zero
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veor $in0,$in0,$tmp
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vext.8 $tmp,$zero,$tmp,#12
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veor $in0,$in0,$tmp
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vext.8 $tmp,$zero,$tmp,#12
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veor $key,$key,$rcon
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veor $in0,$in0,$tmp
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veor $in0,$in0,$key
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vst1.32 {$in0},[$out]
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add $out,$out,#0x50
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mov $rounds,#10
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b .Ldone
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.align 4
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.L192:
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vld1.8 {$in1},[$inp],#8
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vmov.i8 $key,#8 // borrow $key
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vst1.32 {$in0},[$out],#16
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vsub.i8 $mask,$mask,$key // adjust the mask
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.Loop192:
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vtbl.8 $key,{$in1},$mask
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vext.8 $tmp,$zero,$in0,#12
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vst1.32 {$in1},[$out],#8
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aese $key,$zero
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subs $bits,$bits,#1
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veor $in0,$in0,$tmp
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vext.8 $tmp,$zero,$tmp,#12
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veor $in0,$in0,$tmp
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vext.8 $tmp,$zero,$tmp,#12
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veor $in0,$in0,$tmp
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vdup.32 $tmp,${in0}[3]
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veor $tmp,$tmp,$in1
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veor $key,$key,$rcon
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vext.8 $in1,$zero,$in1,#12
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vshl.u8 $rcon,$rcon,#1
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veor $in1,$in1,$tmp
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veor $in0,$in0,$key
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veor $in1,$in1,$key
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vst1.32 {$in0},[$out],#16
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b.ne .Loop192
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mov $rounds,#12
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add $out,$out,#0x20
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b .Ldone
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.align 4
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.L256:
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vld1.8 {$in1},[$inp]
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mov $bits,#7
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mov $rounds,#14
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vst1.32 {$in0},[$out],#16
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.Loop256:
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vtbl.8 $key,{$in1},$mask
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vext.8 $tmp,$zero,$in0,#12
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vst1.32 {$in1},[$out],#16
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aese $key,$zero
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subs $bits,$bits,#1
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veor $in0,$in0,$tmp
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vext.8 $tmp,$zero,$tmp,#12
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veor $in0,$in0,$tmp
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vext.8 $tmp,$zero,$tmp,#12
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veor $key,$key,$rcon
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veor $in0,$in0,$tmp
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vshl.u8 $rcon,$rcon,#1
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veor $in0,$in0,$key
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vst1.32 {$in0},[$out],#16
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b.eq .Ldone
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vdup.32 $key,${in0}[3] // just splat
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vext.8 $tmp,$zero,$in1,#12
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aese $key,$zero
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veor $in1,$in1,$tmp
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vext.8 $tmp,$zero,$tmp,#12
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veor $in1,$in1,$tmp
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vext.8 $tmp,$zero,$tmp,#12
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veor $in1,$in1,$tmp
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veor $in1,$in1,$key
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b .Loop256
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.Ldone:
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str $rounds,[$out]
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eor x0,x0,x0 // return value
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`"ldr x29,[sp],#16" if ($flavour =~ /64/)`
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ret
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.size ${prefix}_set_encrypt_key,.-${prefix}_set_encrypt_key
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.globl ${prefix}_set_decrypt_key
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.type ${prefix}_set_decrypt_key,%function
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.align 5
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${prefix}_set_decrypt_key:
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___
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$code.=<<___ if ($flavour =~ /64/);
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stp x29,x30,[sp,#-16]!
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add x29,sp,#0
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___
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$code.=<<___ if ($flavour !~ /64/);
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stmdb sp!,{r4,lr}
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___
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$code.=<<___;
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bl .Lenc_key
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sub $out,$out,#240 // restore original $out
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mov x4,#-16
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add $inp,$out,x12,lsl#4 // end of key schedule
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vld1.32 {v0.16b},[$out]
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vld1.32 {v1.16b},[$inp]
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vst1.32 {v0.16b},[$inp],x4
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vst1.32 {v1.16b},[$out],#16
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.Loop_imc:
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vld1.32 {v0.16b},[$out]
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vld1.32 {v1.16b},[$inp]
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aesimc v0.16b,v0.16b
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aesimc v1.16b,v1.16b
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vst1.32 {v0.16b},[$inp],x4
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vst1.32 {v1.16b},[$out],#16
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cmp $inp,$out
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b.hi .Loop_imc
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vld1.32 {v0.16b},[$out]
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aesimc v0.16b,v0.16b
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vst1.32 {v0.16b},[$inp]
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eor x0,x0,x0 // return value
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___
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$code.=<<___ if ($flavour !~ /64/);
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ldmia sp!,{r4,pc}
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___
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$code.=<<___ if ($flavour =~ /64/);
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ldp x29,x30,[sp],#16
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ret
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___
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$code.=<<___;
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.size ${prefix}_set_decrypt_key,.-${prefix}_set_decrypt_key
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___
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}}}
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{{{
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sub gen_block () {
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my $dir = shift;
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my ($e,$mc) = $dir eq "en" ? ("e","mc") : ("d","imc");
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my ($inp,$out,$key)=map("x$_",(0..2));
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my $rounds="w3";
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my ($rndkey0,$rndkey1,$inout)=map("q$_",(0..3));
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$code.=<<___;
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.globl ${prefix}_${dir}crypt
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.type ${prefix}_${dir}crypt,%function
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.align 5
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${prefix}_${dir}crypt:
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ldr $rounds,[$key,#240]
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vld1.32 {$rndkey0},[$key],#16
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vld1.8 {$inout},[$inp]
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sub $rounds,$rounds,#2
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vld1.32 {$rndkey1},[$key],#16
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.Loop_${dir}c:
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aes$e $inout,$rndkey0
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aes$mc $inout,$inout
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vld1.32 {$rndkey0},[$key],#16
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subs $rounds,$rounds,#2
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aes$e $inout,$rndkey1
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aes$mc $inout,$inout
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vld1.32 {$rndkey1},[$key],#16
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b.gt .Loop_${dir}c
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aes$e $inout,$rndkey0
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aes$mc $inout,$inout
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vld1.32 {$rndkey0},[$key]
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aes$e $inout,$rndkey1
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veor $inout,$inout,$rndkey0
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vst1.8 {$inout},[$out]
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ret
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.size ${prefix}_${dir}crypt,.-${prefix}_${dir}crypt
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___
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}
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&gen_block("en");
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&gen_block("de");
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}}}
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{{{
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my ($inp,$out,$len,$key,$ivp)=map("x$_",(0..4)); my $enc="w5";
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my ($rounds,$cnt,$key_,$step)=($enc,"w6","x7","x8");
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my ($dat0,$dat1,$in0,$in1,$tmp0,$tmp1,$ivec,$rndlast)=map("q$_",(0..7));
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my ($dat,$tmp,$rndzero_n_last)=($dat0,$tmp0,$tmp1);
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### q8-q15 preloaded key schedule
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$code.=<<___;
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.globl ${prefix}_cbc_encrypt
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.type ${prefix}_cbc_encrypt,%function
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.align 5
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${prefix}_cbc_encrypt:
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___
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$code.=<<___ if ($flavour =~ /64/);
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stp x29,x30,[sp,#-16]!
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add x29,sp,#0
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___
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$code.=<<___ if ($flavour !~ /64/);
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mov ip,sp
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stmdb sp!,{r4-r8,lr}
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vstmdb sp!,{d8-d15} @ ABI specification says so
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ldmia ip,{r4-r5} @ load remaining args
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___
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$code.=<<___;
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subs $len,$len,#16
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mov $step,#16
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b.lo .Lcbc_abort
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cclr $step,eq
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cmp $enc,#0 // en- or decrypting?
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ldr $rounds,[$key,#240]
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and $len,$len,#-16
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vld1.8 {$ivec},[$ivp]
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vld1.8 {$dat},[$inp],$step
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vld1.32 {q8-q9},[$key] // load key schedule...
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sub $rounds,$rounds,#6
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add $key_,$key,x5,lsl#4 // pointer to last 7 round keys
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sub $rounds,$rounds,#2
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vld1.32 {q10-q11},[$key_],#32
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vld1.32 {q12-q13},[$key_],#32
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vld1.32 {q14-q15},[$key_],#32
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vld1.32 {$rndlast},[$key_]
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add $key_,$key,#32
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mov $cnt,$rounds
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b.eq .Lcbc_dec
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veor $dat,$dat,$ivec
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veor $rndzero_n_last,q8,$rndlast
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.Loop_cbc_enc:
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aese $dat,q8
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aesmc $dat,$dat
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vld1.32 {q8},[$key_],#16
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subs $cnt,$cnt,#2
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aese $dat,q9
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aesmc $dat,$dat
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vld1.32 {q9},[$key_],#16
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b.gt .Loop_cbc_enc
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aese $dat,q8
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aesmc $dat,$dat
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subs $len,$len,#16
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aese $dat,q9
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aesmc $dat,$dat
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cclr $step,eq
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aese $dat,q10
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aesmc $dat,$dat
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add $key_,$key,#16
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aese $dat,q11
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aesmc $dat,$dat
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vld1.8 {q8},[$inp],$step
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aese $dat,q12
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aesmc $dat,$dat
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veor q8,q8,$rndzero_n_last
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aese $dat,q13
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aesmc $dat,$dat
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vld1.32 {q9},[$key_],#16 // re-pre-load rndkey[1]
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aese $dat,q14
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aesmc $dat,$dat
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aese $dat,q15
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mov $cnt,$rounds
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veor $ivec,$dat,$rndlast
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vst1.8 {$ivec},[$out],#16
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b.hs .Loop_cbc_enc
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b .Lcbc_done
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.align 5
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.Lcbc_dec:
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subs $len,$len,#16
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vorr $in0,$dat,$dat
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b.lo .Lcbc_dec_tail
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cclr $step,eq
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vld1.8 {$dat1},[$inp],$step
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vorr $in1,$dat1,$dat1
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.Loop2x_cbc_dec:
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aesd $dat0,q8
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aesd $dat1,q8
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aesimc $dat0,$dat0
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aesimc $dat1,$dat1
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vld1.64 {q8},[$key_],#16
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subs $cnt,$cnt,#2
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aesd $dat0,q9
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aesd $dat1,q9
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aesimc $dat0,$dat0
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aesimc $dat1,$dat1
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vld1.64 {q9},[$key_],#16
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b.gt .Loop2x_cbc_dec
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aesd $dat0,q8
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aesd $dat1,q8
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aesimc $dat0,$dat0
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veor $tmp0,$ivec,$rndlast
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aesimc $dat1,$dat1
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veor $tmp1,$in0,$rndlast
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aesd $dat0,q9
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aesd $dat1,q9
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aesimc $dat0,$dat0
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vorr $ivec,$in1,$in1
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aesimc $dat1,$dat1
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subs $len,$len,#32
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aesd $dat0,q10
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aesd $dat1,q10
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aesimc $dat0,$dat0
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cclr $step,lo
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aesimc $dat1,$dat1
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mov $key_,$key
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aesd $dat0,q11
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aesd $dat1,q11
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aesimc $dat0,$dat0
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vld1.8 {$in0},[$inp],$step
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aesimc $dat1,$dat1
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cclr $step,ls
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aesd $dat0,q12
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aesd $dat1,q12
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aesimc $dat0,$dat0
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aesimc $dat1,$dat1
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vld1.8 {$in1},[$inp],$step
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aesd $dat0,q13
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aesd $dat1,q13
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aesimc $dat0,$dat0
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aesimc $dat1,$dat1
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vld1.32 {q8},[$key_],#16 // re-pre-load rndkey[0]
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aesd $dat0,q14
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aesd $dat1,q14
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aesimc $dat0,$dat0
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aesimc $dat1,$dat1
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vld1.32 {q9},[$key_],#16 // re-pre-load rndkey[1]
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aesd $dat0,q15
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aesd $dat1,q15
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mov $cnt,$rounds
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veor $tmp0,$tmp0,$dat0
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vorr $dat0,$in0,$in0
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veor $tmp1,$tmp1,$dat1
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vorr $dat1,$in1,$in1
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vst1.8 {$tmp0-$tmp1},[$out],#32
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b.hs .Loop2x_cbc_dec
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adds $len,$len,#32
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b.eq .Lcbc_done
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.Lcbc_dec_tail:
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aesd $dat,q8
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aesimc $dat,$dat
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vld1.64 {q8},[$key_],#16
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subs $cnt,$cnt,#2
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aesd $dat,q9
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aesimc $dat,$dat
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vld1.64 {q9},[$key_],#16
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b.gt .Lcbc_dec_tail
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aesd $dat,q8
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aesimc $dat,$dat
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aesd $dat,q9
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aesimc $dat,$dat
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veor $tmp,$ivec,$rndlast
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aesd $dat,q10
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aesimc $dat,$dat
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vorr $ivec,$in0,$in0
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aesd $dat,q11
|
|
aesimc $dat,$dat
|
|
aesd $dat,q12
|
|
aesimc $dat,$dat
|
|
aesd $dat,q13
|
|
aesimc $dat,$dat
|
|
aesd $dat,q14
|
|
aesimc $dat,$dat
|
|
aesd $dat,q15
|
|
|
|
veor $tmp,$tmp,$dat
|
|
vst1.8 {$tmp},[$out],#16
|
|
|
|
.Lcbc_done:
|
|
vst1.8 {$ivec},[$ivp]
|
|
.Lcbc_abort:
|
|
___
|
|
$code.=<<___ if ($flavour !~ /64/);
|
|
vldmia sp!,{d8-d15}
|
|
ldmia sp!,{r4-r8,pc}
|
|
___
|
|
$code.=<<___ if ($flavour =~ /64/);
|
|
ldr x29,[sp],#16
|
|
ret
|
|
___
|
|
$code.=<<___;
|
|
.size ${prefix}_cbc_encrypt,.-${prefix}_cbc_encrypt
|
|
___
|
|
}}}
|
|
########################################
|
|
if ($flavour =~ /64/) { ######## 64-bit code
|
|
my %opcode = (
|
|
"aesd" => 0x4e285800, "aese" => 0x4e284800,
|
|
"aesimc"=> 0x4e287800, "aesmc" => 0x4e286800 );
|
|
|
|
sub unaes {
|
|
my ($mnemonic,$arg)=@_;
|
|
|
|
$arg =~ m/[qv]([0-9]+)[^,]*,\s*[qv]([0-9]+)/o &&
|
|
sprintf ".long\t0x%08x\t//%s %s",
|
|
$opcode{$mnemonic}|$1|($2<<5),
|
|
$mnemonic,$arg;
|
|
}
|
|
|
|
foreach(split("\n",$code)) {
|
|
s/\`([^\`]*)\`/eval($1)/geo;
|
|
|
|
s/\bq([0-9]+)\b/"v".($1<8?$1:$1+8).".16b"/geo; # old->new registers
|
|
s/@\s/\/\//o; # old->new style commentary
|
|
|
|
#s/[v]?(aes\w+)\s+([qv].*)/unaes($1,$2)/geo or
|
|
s/cclr\s+([wx])([^,]+),\s*([a-z]+)/csel $1$2,$1zr,$1$2,$3/o or
|
|
s/vmov\.i8/movi/o or # fix up legacy mnemonics
|
|
s/vext\.8/ext/o or
|
|
s/vrev32\.8/rev32/o or
|
|
s/vtst\.8/cmtst/o or
|
|
s/vshr/ushr/o or
|
|
s/^(\s+)v/$1/o or # strip off v prefix
|
|
s/\bbx\s+lr\b/ret/o;
|
|
|
|
# fix up remainig legacy suffixes
|
|
s/\.[ui]?8//o;
|
|
m/\],#8/o and s/\.16b/\.8b/go;
|
|
s/\.[ui]?32//o and s/\.16b/\.4s/go;
|
|
s/\.[ui]?64//o and s/\.16b/\.2d/go;
|
|
s/\.[42]([sd])\[([0-3])\]/\.$1\[$2\]/o;
|
|
|
|
print $_,"\n";
|
|
}
|
|
} else { ######## 32-bit code
|
|
my %opcode = (
|
|
"aesd" => 0xf3b00340, "aese" => 0xf3b00300,
|
|
"aesimc"=> 0xf3b003c0, "aesmc" => 0xf3b00380 );
|
|
|
|
sub unaes {
|
|
my ($mnemonic,$arg)=@_;
|
|
|
|
$arg =~ m/[qv]([0-9]+)[^,]*,\s*[qv]([0-9]+)/o &&
|
|
sprintf ".long\t0x%08x\t@ %s %s",
|
|
$opcode{$mnemonic}|(($1&7)<<13)|(($1&8)<<19)
|
|
|(($2&7)<<1) |(($2&8)<<2),
|
|
$mnemonic,$arg;
|
|
}
|
|
|
|
sub unvtbl {
|
|
my $arg=shift;
|
|
|
|
$arg =~ m/q([0-9]+),\s*\{q([0-9]+)\},\s*q([0-9]+)/o &&
|
|
sprintf "vtbl.8 d%d,{q%d},d%d\n\tvtbl.8 d%d,{q%d},d%d",2*$1,$2,2*$3,2*$1+1,$2,2*$3+1;
|
|
}
|
|
|
|
sub unvdup32 {
|
|
my $arg=shift;
|
|
|
|
$arg =~ m/q([0-9]+),\s*q([0-9]+)\[([0-3])\]/o &&
|
|
sprintf "vdup.32 q%d,d%d[%d]",$1,2*$2+$3>>1,$3&1;
|
|
}
|
|
|
|
foreach(split("\n",$code)) {
|
|
s/\`([^\`]*)\`/eval($1)/geo;
|
|
|
|
s/\b[wx]([0-9]+)\b/r$1/go; # new->old registers
|
|
s/\bv([0-9])\.[12468]+[bsd]\b/q$1/go; # new->old registers
|
|
s/\/\/\s?/@ /o; # new->old style commentary
|
|
|
|
# fix up remainig new-style suffixes
|
|
s/\],#[0-9]+/]!/o;
|
|
|
|
s/[v]?(aes\w+)\s+([qv].*)/unaes($1,$2)/geo or
|
|
s/cclr\s+([^,]+),\s*([a-z]+)/mov$2 $1,#0/o or
|
|
s/vtbl\.8\s+(.*)/unvtbl($1)/geo or
|
|
s/vdup\.32\s+(.*)/unvdup32($1)/geo or
|
|
s/^(\s+)b\./$1b/o or
|
|
s/^(\s+)ret/$1bx\tlr/o;
|
|
|
|
print $_,"\n";
|
|
}
|
|
}
|
|
|
|
close STDOUT;
|