685 lines
17 KiB
Prolog
685 lines
17 KiB
Prolog
#!/usr/bin/env perl
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# ====================================================================
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# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
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# project. The module is, however, dual licensed under OpenSSL and
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# CRYPTOGAMS licenses depending on where you obtain it. For further
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# details see http://www.openssl.org/~appro/cryptogams/.
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# ====================================================================
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# sha1_block procedure for ARMv4.
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#
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# January 2007.
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# Size/performance trade-off
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# ====================================================================
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# impl size in bytes comp cycles[*] measured performance
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# ====================================================================
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# thumb 304 3212 4420
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# armv4-small 392/+29% 1958/+64% 2250/+96%
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# armv4-compact 740/+89% 1552/+26% 1840/+22%
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# armv4-large 1420/+92% 1307/+19% 1370/+34%[***]
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# full unroll ~5100/+260% ~1260/+4% ~1300/+5%
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# ====================================================================
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# thumb = same as 'small' but in Thumb instructions[**] and
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# with recurring code in two private functions;
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# small = detached Xload/update, loops are folded;
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# compact = detached Xload/update, 5x unroll;
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# large = interleaved Xload/update, 5x unroll;
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# full unroll = interleaved Xload/update, full unroll, estimated[!];
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#
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# [*] Manually counted instructions in "grand" loop body. Measured
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# performance is affected by prologue and epilogue overhead,
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# i-cache availability, branch penalties, etc.
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# [**] While each Thumb instruction is twice smaller, they are not as
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# diverse as ARM ones: e.g., there are only two arithmetic
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# instructions with 3 arguments, no [fixed] rotate, addressing
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# modes are limited. As result it takes more instructions to do
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# the same job in Thumb, therefore the code is never twice as
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# small and always slower.
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# [***] which is also ~35% better than compiler generated code. Dual-
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# issue Cortex A8 core was measured to process input block in
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# ~990 cycles.
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# August 2010.
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#
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# Rescheduling for dual-issue pipeline resulted in 13% improvement on
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# Cortex A8 core and in absolute terms ~870 cycles per input block
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# [or 13.6 cycles per byte].
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# February 2011.
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#
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# Profiler-assisted and platform-specific optimization resulted in 10%
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# improvement on Cortex A8 core and 12.2 cycles per byte.
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# September 2013.
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#
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# Add NEON implementation (see sha1-586.pl for background info). On
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# Cortex A8 it was measured to process one byte in 6.7 cycles or >80%
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# faster than integer-only code. Because [fully unrolled] NEON code
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# is ~2.5x larger and there are some redundant instructions executed
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# when processing last block, improvement is not as big for smallest
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# blocks, only ~30%. Snapdragon S4 is a tad faster, 6.4 cycles per
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# byte, which is also >80% faster than integer-only code. Cortex-A15
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# is even faster spending 5.6 cycles per byte outperforming integer-
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# only code by factor of 2.
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# May 2014.
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#
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# Add ARMv8 code path performing at 2.35 cpb on Apple A7.
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while (($output=shift) && ($output!~/^\w[\w\-]*\.\w+$/)) {}
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open STDOUT,">$output";
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$ctx="r0";
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$inp="r1";
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$len="r2";
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$a="r3";
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$b="r4";
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$c="r5";
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$d="r6";
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$e="r7";
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$K="r8";
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$t0="r9";
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$t1="r10";
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$t2="r11";
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$t3="r12";
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$Xi="r14";
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@V=($a,$b,$c,$d,$e);
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sub Xupdate {
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my ($a,$b,$c,$d,$e,$opt1,$opt2)=@_;
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$code.=<<___;
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ldr $t0,[$Xi,#15*4]
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ldr $t1,[$Xi,#13*4]
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ldr $t2,[$Xi,#7*4]
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add $e,$K,$e,ror#2 @ E+=K_xx_xx
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ldr $t3,[$Xi,#2*4]
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eor $t0,$t0,$t1
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eor $t2,$t2,$t3 @ 1 cycle stall
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eor $t1,$c,$d @ F_xx_xx
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mov $t0,$t0,ror#31
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add $e,$e,$a,ror#27 @ E+=ROR(A,27)
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eor $t0,$t0,$t2,ror#31
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str $t0,[$Xi,#-4]!
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$opt1 @ F_xx_xx
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$opt2 @ F_xx_xx
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add $e,$e,$t0 @ E+=X[i]
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___
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}
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sub BODY_00_15 {
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my ($a,$b,$c,$d,$e)=@_;
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$code.=<<___;
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#if __ARM_ARCH__<7
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ldrb $t1,[$inp,#2]
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ldrb $t0,[$inp,#3]
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ldrb $t2,[$inp,#1]
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add $e,$K,$e,ror#2 @ E+=K_00_19
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ldrb $t3,[$inp],#4
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orr $t0,$t0,$t1,lsl#8
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eor $t1,$c,$d @ F_xx_xx
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orr $t0,$t0,$t2,lsl#16
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add $e,$e,$a,ror#27 @ E+=ROR(A,27)
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orr $t0,$t0,$t3,lsl#24
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#else
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ldr $t0,[$inp],#4 @ handles unaligned
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add $e,$K,$e,ror#2 @ E+=K_00_19
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eor $t1,$c,$d @ F_xx_xx
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add $e,$e,$a,ror#27 @ E+=ROR(A,27)
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#ifdef __ARMEL__
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rev $t0,$t0 @ byte swap
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#endif
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#endif
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and $t1,$b,$t1,ror#2
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add $e,$e,$t0 @ E+=X[i]
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eor $t1,$t1,$d,ror#2 @ F_00_19(B,C,D)
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str $t0,[$Xi,#-4]!
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add $e,$e,$t1 @ E+=F_00_19(B,C,D)
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___
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}
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sub BODY_16_19 {
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my ($a,$b,$c,$d,$e)=@_;
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&Xupdate(@_,"and $t1,$b,$t1,ror#2");
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$code.=<<___;
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eor $t1,$t1,$d,ror#2 @ F_00_19(B,C,D)
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add $e,$e,$t1 @ E+=F_00_19(B,C,D)
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___
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}
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sub BODY_20_39 {
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my ($a,$b,$c,$d,$e)=@_;
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&Xupdate(@_,"eor $t1,$b,$t1,ror#2");
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$code.=<<___;
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add $e,$e,$t1 @ E+=F_20_39(B,C,D)
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___
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}
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sub BODY_40_59 {
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my ($a,$b,$c,$d,$e)=@_;
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&Xupdate(@_,"and $t1,$b,$t1,ror#2","and $t2,$c,$d");
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$code.=<<___;
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add $e,$e,$t1 @ E+=F_40_59(B,C,D)
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add $e,$e,$t2,ror#2
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___
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}
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$code=<<___;
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#include "arm_arch.h"
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.text
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.code 32
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.global sha1_block_data_order
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.type sha1_block_data_order,%function
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.align 5
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sha1_block_data_order:
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#if __ARM_MAX_ARCH__>=7
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sub r3,pc,#8 @ sha1_block_data_order
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ldr r12,.LOPENSSL_armcap
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ldr r12,[r3,r12] @ OPENSSL_armcap_P
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tst r12,#ARMV8_SHA1
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bne .LARMv8
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tst r12,#ARMV7_NEON
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bne .LNEON
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#endif
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stmdb sp!,{r4-r12,lr}
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add $len,$inp,$len,lsl#6 @ $len to point at the end of $inp
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ldmia $ctx,{$a,$b,$c,$d,$e}
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.Lloop:
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ldr $K,.LK_00_19
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mov $Xi,sp
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sub sp,sp,#15*4
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mov $c,$c,ror#30
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mov $d,$d,ror#30
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mov $e,$e,ror#30 @ [6]
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.L_00_15:
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___
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for($i=0;$i<5;$i++) {
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&BODY_00_15(@V); unshift(@V,pop(@V));
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}
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$code.=<<___;
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teq $Xi,sp
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bne .L_00_15 @ [((11+4)*5+2)*3]
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sub sp,sp,#25*4
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___
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&BODY_00_15(@V); unshift(@V,pop(@V));
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&BODY_16_19(@V); unshift(@V,pop(@V));
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&BODY_16_19(@V); unshift(@V,pop(@V));
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&BODY_16_19(@V); unshift(@V,pop(@V));
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&BODY_16_19(@V); unshift(@V,pop(@V));
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$code.=<<___;
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ldr $K,.LK_20_39 @ [+15+16*4]
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cmn sp,#0 @ [+3], clear carry to denote 20_39
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.L_20_39_or_60_79:
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___
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for($i=0;$i<5;$i++) {
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&BODY_20_39(@V); unshift(@V,pop(@V));
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}
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$code.=<<___;
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teq $Xi,sp @ preserve carry
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bne .L_20_39_or_60_79 @ [+((12+3)*5+2)*4]
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bcs .L_done @ [+((12+3)*5+2)*4], spare 300 bytes
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ldr $K,.LK_40_59
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sub sp,sp,#20*4 @ [+2]
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.L_40_59:
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___
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for($i=0;$i<5;$i++) {
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&BODY_40_59(@V); unshift(@V,pop(@V));
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}
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$code.=<<___;
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teq $Xi,sp
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bne .L_40_59 @ [+((12+5)*5+2)*4]
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ldr $K,.LK_60_79
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sub sp,sp,#20*4
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cmp sp,#0 @ set carry to denote 60_79
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b .L_20_39_or_60_79 @ [+4], spare 300 bytes
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.L_done:
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add sp,sp,#80*4 @ "deallocate" stack frame
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ldmia $ctx,{$K,$t0,$t1,$t2,$t3}
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add $a,$K,$a
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add $b,$t0,$b
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add $c,$t1,$c,ror#2
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add $d,$t2,$d,ror#2
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add $e,$t3,$e,ror#2
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stmia $ctx,{$a,$b,$c,$d,$e}
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teq $inp,$len
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bne .Lloop @ [+18], total 1307
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#if __ARM_ARCH__>=5
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ldmia sp!,{r4-r12,pc}
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#else
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ldmia sp!,{r4-r12,lr}
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tst lr,#1
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moveq pc,lr @ be binary compatible with V4, yet
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bx lr @ interoperable with Thumb ISA:-)
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#endif
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.size sha1_block_data_order,.-sha1_block_data_order
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.align 5
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.LK_00_19: .word 0x5a827999
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.LK_20_39: .word 0x6ed9eba1
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.LK_40_59: .word 0x8f1bbcdc
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.LK_60_79: .word 0xca62c1d6
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#if __ARM_MAX_ARCH__>=7
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.LOPENSSL_armcap:
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.word OPENSSL_armcap_P-sha1_block_data_order
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#endif
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.asciz "SHA1 block transform for ARMv4/NEON/ARMv8, CRYPTOGAMS by <appro\@openssl.org>"
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.align 5
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___
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#####################################################################
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# NEON stuff
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#
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{{{
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my @V=($a,$b,$c,$d,$e);
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my ($K_XX_XX,$Ki,$t0,$t1,$Xfer,$saved_sp)=map("r$_",(8..12,14));
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my $Xi=4;
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my @X=map("q$_",(8..11,0..3));
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my @Tx=("q12","q13");
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my ($K,$zero)=("q14","q15");
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my $j=0;
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sub AUTOLOAD() # thunk [simplified] x86-style perlasm
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{ my $opcode = $AUTOLOAD; $opcode =~ s/.*:://; $opcode =~ s/_/\./;
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my $arg = pop;
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$arg = "#$arg" if ($arg*1 eq $arg);
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$code .= "\t$opcode\t".join(',',@_,$arg)."\n";
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}
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sub body_00_19 () {
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(
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'($a,$b,$c,$d,$e)=@V;'. # '$code.="@ $j\n";'.
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'&bic ($t0,$d,$b)',
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'&add ($e,$e,$Ki)', # e+=X[i]+K
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'&and ($t1,$c,$b)',
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'&ldr ($Ki,sprintf "[sp,#%d]",4*(($j+1)&15))',
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'&add ($e,$e,$a,"ror#27")', # e+=ROR(A,27)
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'&eor ($t1,$t1,$t0)', # F_00_19
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'&mov ($b,$b,"ror#2")', # b=ROR(b,2)
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'&add ($e,$e,$t1);'. # e+=F_00_19
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'$j++; unshift(@V,pop(@V));'
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)
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}
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sub body_20_39 () {
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(
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'($a,$b,$c,$d,$e)=@V;'. # '$code.="@ $j\n";'.
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'&eor ($t0,$b,$d)',
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'&add ($e,$e,$Ki)', # e+=X[i]+K
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'&ldr ($Ki,sprintf "[sp,#%d]",4*(($j+1)&15)) if ($j<79)',
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'&eor ($t1,$t0,$c)', # F_20_39
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'&add ($e,$e,$a,"ror#27")', # e+=ROR(A,27)
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'&mov ($b,$b,"ror#2")', # b=ROR(b,2)
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'&add ($e,$e,$t1);'. # e+=F_20_39
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'$j++; unshift(@V,pop(@V));'
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)
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}
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sub body_40_59 () {
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(
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'($a,$b,$c,$d,$e)=@V;'. # '$code.="@ $j\n";'.
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'&add ($e,$e,$Ki)', # e+=X[i]+K
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'&and ($t0,$c,$d)',
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'&ldr ($Ki,sprintf "[sp,#%d]",4*(($j+1)&15))',
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'&add ($e,$e,$a,"ror#27")', # e+=ROR(A,27)
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'&eor ($t1,$c,$d)',
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'&add ($e,$e,$t0)',
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'&and ($t1,$t1,$b)',
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'&mov ($b,$b,"ror#2")', # b=ROR(b,2)
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'&add ($e,$e,$t1);'. # e+=F_40_59
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'$j++; unshift(@V,pop(@V));'
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)
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}
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sub Xupdate_16_31 ()
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{ use integer;
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my $body = shift;
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my @insns = (&$body,&$body,&$body,&$body);
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my ($a,$b,$c,$d,$e);
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&vext_8 (@X[0],@X[-4&7],@X[-3&7],8); # compose "X[-14]" in "X[0]"
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eval(shift(@insns));
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eval(shift(@insns));
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eval(shift(@insns));
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&vadd_i32 (@Tx[1],@X[-1&7],$K);
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eval(shift(@insns));
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&vld1_32 ("{$K\[]}","[$K_XX_XX,:32]!") if ($Xi%5==0);
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eval(shift(@insns));
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&vext_8 (@Tx[0],@X[-1&7],$zero,4); # "X[-3]", 3 words
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eval(shift(@insns));
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eval(shift(@insns));
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eval(shift(@insns));
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&veor (@X[0],@X[0],@X[-4&7]); # "X[0]"^="X[-16]"
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eval(shift(@insns));
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eval(shift(@insns));
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&veor (@Tx[0],@Tx[0],@X[-2&7]); # "X[-3]"^"X[-8]"
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eval(shift(@insns));
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eval(shift(@insns));
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&veor (@Tx[0],@Tx[0],@X[0]); # "X[0]"^="X[-3]"^"X[-8]
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eval(shift(@insns));
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eval(shift(@insns));
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&vst1_32 ("{@Tx[1]}","[$Xfer,:128]!"); # X[]+K xfer
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&sub ($Xfer,$Xfer,64) if ($Xi%4==0);
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eval(shift(@insns));
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eval(shift(@insns));
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&vext_8 (@Tx[1],$zero,@Tx[0],4); # "X[0]"<<96, extract one dword
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eval(shift(@insns));
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eval(shift(@insns));
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&vadd_i32 (@X[0],@Tx[0],@Tx[0]);
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eval(shift(@insns));
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eval(shift(@insns));
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&vsri_32 (@X[0],@Tx[0],31); # "X[0]"<<<=1
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eval(shift(@insns));
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eval(shift(@insns));
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eval(shift(@insns));
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&vshr_u32 (@Tx[0],@Tx[1],30);
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eval(shift(@insns));
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eval(shift(@insns));
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&vshl_u32 (@Tx[1],@Tx[1],2);
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eval(shift(@insns));
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eval(shift(@insns));
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&veor (@X[0],@X[0],@Tx[0]);
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eval(shift(@insns));
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eval(shift(@insns));
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&veor (@X[0],@X[0],@Tx[1]); # "X[0]"^=("X[0]">>96)<<<2
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foreach (@insns) { eval; } # remaining instructions [if any]
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$Xi++; push(@X,shift(@X)); # "rotate" X[]
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}
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sub Xupdate_32_79 ()
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{ use integer;
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my $body = shift;
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my @insns = (&$body,&$body,&$body,&$body);
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my ($a,$b,$c,$d,$e);
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&vext_8 (@Tx[0],@X[-2&7],@X[-1&7],8); # compose "X[-6]"
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eval(shift(@insns));
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eval(shift(@insns));
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eval(shift(@insns));
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&veor (@X[0],@X[0],@X[-4&7]); # "X[0]"="X[-32]"^"X[-16]"
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eval(shift(@insns));
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eval(shift(@insns));
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&veor (@X[0],@X[0],@X[-7&7]); # "X[0]"^="X[-28]"
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eval(shift(@insns));
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eval(shift(@insns));
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&vadd_i32 (@Tx[1],@X[-1&7],$K);
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eval(shift(@insns));
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&vld1_32 ("{$K\[]}","[$K_XX_XX,:32]!") if ($Xi%5==0);
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eval(shift(@insns));
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&veor (@Tx[0],@Tx[0],@X[0]); # "X[-6]"^="X[0]"
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eval(shift(@insns));
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eval(shift(@insns));
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&vshr_u32 (@X[0],@Tx[0],30);
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eval(shift(@insns));
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eval(shift(@insns));
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&vst1_32 ("{@Tx[1]}","[$Xfer,:128]!"); # X[]+K xfer
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&sub ($Xfer,$Xfer,64) if ($Xi%4==0);
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eval(shift(@insns));
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eval(shift(@insns));
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&vsli_32 (@X[0],@Tx[0],2); # "X[0]"="X[-6]"<<<2
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|
foreach (@insns) { eval; } # remaining instructions [if any]
|
|
|
|
$Xi++; push(@X,shift(@X)); # "rotate" X[]
|
|
}
|
|
|
|
sub Xuplast_80 ()
|
|
{ use integer;
|
|
my $body = shift;
|
|
my @insns = (&$body,&$body,&$body,&$body);
|
|
my ($a,$b,$c,$d,$e);
|
|
|
|
&vadd_i32 (@Tx[1],@X[-1&7],$K);
|
|
eval(shift(@insns));
|
|
eval(shift(@insns));
|
|
&vst1_32 ("{@Tx[1]}","[$Xfer,:128]!");
|
|
&sub ($Xfer,$Xfer,64);
|
|
|
|
&teq ($inp,$len);
|
|
&sub ($K_XX_XX,$K_XX_XX,16); # rewind $K_XX_XX
|
|
&subeq ($inp,$inp,64); # reload last block to avoid SEGV
|
|
&vld1_8 ("{@X[-4&7]-@X[-3&7]}","[$inp]!");
|
|
eval(shift(@insns));
|
|
eval(shift(@insns));
|
|
&vld1_8 ("{@X[-2&7]-@X[-1&7]}","[$inp]!");
|
|
eval(shift(@insns));
|
|
eval(shift(@insns));
|
|
&vld1_32 ("{$K\[]}","[$K_XX_XX,:32]!"); # load K_00_19
|
|
eval(shift(@insns));
|
|
eval(shift(@insns));
|
|
&vrev32_8 (@X[-4&7],@X[-4&7]);
|
|
|
|
foreach (@insns) { eval; } # remaining instructions
|
|
|
|
$Xi=0;
|
|
}
|
|
|
|
sub Xloop()
|
|
{ use integer;
|
|
my $body = shift;
|
|
my @insns = (&$body,&$body,&$body,&$body);
|
|
my ($a,$b,$c,$d,$e);
|
|
|
|
&vrev32_8 (@X[($Xi-3)&7],@X[($Xi-3)&7]);
|
|
eval(shift(@insns));
|
|
eval(shift(@insns));
|
|
&vadd_i32 (@X[$Xi&7],@X[($Xi-4)&7],$K);
|
|
eval(shift(@insns));
|
|
eval(shift(@insns));
|
|
&vst1_32 ("{@X[$Xi&7]}","[$Xfer,:128]!");# X[]+K xfer to IALU
|
|
|
|
foreach (@insns) { eval; }
|
|
|
|
$Xi++;
|
|
}
|
|
|
|
$code.=<<___;
|
|
#if __ARM_MAX_ARCH__>=7
|
|
.arch armv7-a
|
|
.fpu neon
|
|
|
|
.type sha1_block_data_order_neon,%function
|
|
.align 4
|
|
sha1_block_data_order_neon:
|
|
.LNEON:
|
|
stmdb sp!,{r4-r12,lr}
|
|
add $len,$inp,$len,lsl#6 @ $len to point at the end of $inp
|
|
@ dmb @ errata #451034 on early Cortex A8
|
|
@ vstmdb sp!,{d8-d15} @ ABI specification says so
|
|
mov $saved_sp,sp
|
|
sub sp,sp,#64 @ alloca
|
|
adr $K_XX_XX,.LK_00_19
|
|
bic sp,sp,#15 @ align for 128-bit stores
|
|
|
|
ldmia $ctx,{$a,$b,$c,$d,$e} @ load context
|
|
mov $Xfer,sp
|
|
|
|
vld1.8 {@X[-4&7]-@X[-3&7]},[$inp]! @ handles unaligned
|
|
veor $zero,$zero,$zero
|
|
vld1.8 {@X[-2&7]-@X[-1&7]},[$inp]!
|
|
vld1.32 {${K}\[]},[$K_XX_XX,:32]! @ load K_00_19
|
|
vrev32.8 @X[-4&7],@X[-4&7] @ yes, even on
|
|
vrev32.8 @X[-3&7],@X[-3&7] @ big-endian...
|
|
vrev32.8 @X[-2&7],@X[-2&7]
|
|
vadd.i32 @X[0],@X[-4&7],$K
|
|
vrev32.8 @X[-1&7],@X[-1&7]
|
|
vadd.i32 @X[1],@X[-3&7],$K
|
|
vst1.32 {@X[0]},[$Xfer,:128]!
|
|
vadd.i32 @X[2],@X[-2&7],$K
|
|
vst1.32 {@X[1]},[$Xfer,:128]!
|
|
vst1.32 {@X[2]},[$Xfer,:128]!
|
|
ldr $Ki,[sp] @ big RAW stall
|
|
|
|
.Loop_neon:
|
|
___
|
|
&Xupdate_16_31(\&body_00_19);
|
|
&Xupdate_16_31(\&body_00_19);
|
|
&Xupdate_16_31(\&body_00_19);
|
|
&Xupdate_16_31(\&body_00_19);
|
|
&Xupdate_32_79(\&body_00_19);
|
|
&Xupdate_32_79(\&body_20_39);
|
|
&Xupdate_32_79(\&body_20_39);
|
|
&Xupdate_32_79(\&body_20_39);
|
|
&Xupdate_32_79(\&body_20_39);
|
|
&Xupdate_32_79(\&body_20_39);
|
|
&Xupdate_32_79(\&body_40_59);
|
|
&Xupdate_32_79(\&body_40_59);
|
|
&Xupdate_32_79(\&body_40_59);
|
|
&Xupdate_32_79(\&body_40_59);
|
|
&Xupdate_32_79(\&body_40_59);
|
|
&Xupdate_32_79(\&body_20_39);
|
|
&Xuplast_80(\&body_20_39);
|
|
&Xloop(\&body_20_39);
|
|
&Xloop(\&body_20_39);
|
|
&Xloop(\&body_20_39);
|
|
$code.=<<___;
|
|
ldmia $ctx,{$Ki,$t0,$t1,$Xfer} @ accumulate context
|
|
add $a,$a,$Ki
|
|
ldr $Ki,[$ctx,#16]
|
|
add $b,$b,$t0
|
|
add $c,$c,$t1
|
|
add $d,$d,$Xfer
|
|
moveq sp,$saved_sp
|
|
add $e,$e,$Ki
|
|
ldrne $Ki,[sp]
|
|
stmia $ctx,{$a,$b,$c,$d,$e}
|
|
addne $Xfer,sp,#3*16
|
|
bne .Loop_neon
|
|
|
|
@ vldmia sp!,{d8-d15}
|
|
ldmia sp!,{r4-r12,pc}
|
|
.size sha1_block_data_order_neon,.-sha1_block_data_order_neon
|
|
#endif
|
|
___
|
|
}}}
|
|
#####################################################################
|
|
# ARMv8 stuff
|
|
#
|
|
{{{
|
|
my ($ABCD,$E,$E0,$E1)=map("q$_",(0..3));
|
|
my @MSG=map("q$_",(4..7));
|
|
my @Kxx=map("q$_",(8..11));
|
|
my ($W0,$W1,$ABCD_SAVE)=map("q$_",(12..14));
|
|
|
|
$code.=<<___;
|
|
#if __ARM_MAX_ARCH__>=7
|
|
.type sha1_block_data_order_armv8,%function
|
|
.align 5
|
|
sha1_block_data_order_armv8:
|
|
.LARMv8:
|
|
vstmdb sp!,{d8-d15} @ ABI specification says so
|
|
|
|
veor $E,$E,$E
|
|
adr r3,.LK_00_19
|
|
vld1.32 {$ABCD},[$ctx]!
|
|
vld1.32 {$E\[0]},[$ctx]
|
|
sub $ctx,$ctx,#16
|
|
vld1.32 {@Kxx[0]\[]},[r3,:32]!
|
|
vld1.32 {@Kxx[1]\[]},[r3,:32]!
|
|
vld1.32 {@Kxx[2]\[]},[r3,:32]!
|
|
vld1.32 {@Kxx[3]\[]},[r3,:32]
|
|
|
|
.Loop_v8:
|
|
vld1.8 {@MSG[0]-@MSG[1]},[$inp]!
|
|
vld1.8 {@MSG[2]-@MSG[3]},[$inp]!
|
|
vrev32.8 @MSG[0],@MSG[0]
|
|
vrev32.8 @MSG[1],@MSG[1]
|
|
|
|
vadd.i32 $W0,@Kxx[0],@MSG[0]
|
|
vrev32.8 @MSG[2],@MSG[2]
|
|
vmov $ABCD_SAVE,$ABCD @ offload
|
|
subs $len,$len,#1
|
|
|
|
vadd.i32 $W1,@Kxx[0],@MSG[1]
|
|
vrev32.8 @MSG[3],@MSG[3]
|
|
sha1h $E1,$ABCD @ 0
|
|
sha1c $ABCD,$E,$W0
|
|
vadd.i32 $W0,@Kxx[$j],@MSG[2]
|
|
sha1su0 @MSG[0],@MSG[1],@MSG[2]
|
|
___
|
|
for ($j=0,$i=1;$i<20-3;$i++) {
|
|
my $f=("c","p","m","p")[$i/5];
|
|
$code.=<<___;
|
|
sha1h $E0,$ABCD @ $i
|
|
sha1$f $ABCD,$E1,$W1
|
|
vadd.i32 $W1,@Kxx[$j],@MSG[3]
|
|
sha1su1 @MSG[0],@MSG[3]
|
|
___
|
|
$code.=<<___ if ($i<20-4);
|
|
sha1su0 @MSG[1],@MSG[2],@MSG[3]
|
|
___
|
|
($E0,$E1)=($E1,$E0); ($W0,$W1)=($W1,$W0);
|
|
push(@MSG,shift(@MSG)); $j++ if ((($i+3)%5)==0);
|
|
}
|
|
$code.=<<___;
|
|
sha1h $E0,$ABCD @ $i
|
|
sha1p $ABCD,$E1,$W1
|
|
vadd.i32 $W1,@Kxx[$j],@MSG[3]
|
|
|
|
sha1h $E1,$ABCD @ 18
|
|
sha1p $ABCD,$E0,$W0
|
|
|
|
sha1h $E0,$ABCD @ 19
|
|
sha1p $ABCD,$E1,$W1
|
|
|
|
vadd.i32 $E,$E,$E0
|
|
vadd.i32 $ABCD,$ABCD,$ABCD_SAVE
|
|
bne .Loop_v8
|
|
|
|
vst1.32 {$ABCD},[$ctx]!
|
|
vst1.32 {$E\[0]},[$ctx]
|
|
|
|
vldmia sp!,{d8-d15}
|
|
ret @ bx lr
|
|
.size sha1_block_data_order_armv8,.-sha1_block_data_order_armv8
|
|
#endif
|
|
___
|
|
}}}
|
|
$code.=<<___;
|
|
#if __ARM_MAX_ARCH__>=7
|
|
.comm OPENSSL_armcap_P,4,4
|
|
#endif
|
|
___
|
|
|
|
{ my %opcode = (
|
|
"sha1c" => 0xf2000c40, "sha1p" => 0xf2100c40,
|
|
"sha1m" => 0xf2200c40, "sha1su0" => 0xf2300c40,
|
|
"sha1h" => 0xf3b902c0, "sha1su1" => 0xf3ba0380 );
|
|
|
|
sub unsha1 {
|
|
my ($mnemonic,$arg)=@_;
|
|
|
|
if ($arg =~ m/q([0-9]+)(?:,\s*q([0-9]+))?,\s*q([0-9]+)/o) {
|
|
my $word = $opcode{$mnemonic}|(($1&7)<<13)|(($1&8)<<19)
|
|
|(($2&7)<<17)|(($2&8)<<4)
|
|
|(($3&7)<<1) |(($3&8)<<2);
|
|
# since ARMv7 instructions are always encoded little-endian.
|
|
# correct solution is to use .inst directive, but older
|
|
# assemblers don't implement it:-(
|
|
sprintf ".byte\t0x%02x,0x%02x,0x%02x,0x%02x\t@ %s %s",
|
|
$word&0xff,($word>>8)&0xff,
|
|
($word>>16)&0xff,($word>>24)&0xff,
|
|
$mnemonic,$arg;
|
|
}
|
|
}
|
|
}
|
|
|
|
foreach (split($/,$code)) {
|
|
s/{q([0-9]+)\[\]}/sprintf "{d%d[],d%d[]}",2*$1,2*$1+1/eo or
|
|
s/{q([0-9]+)\[0\]}/sprintf "{d%d[0]}",2*$1/eo;
|
|
|
|
s/\b(sha1\w+)\s+(q.*)/unsha1($1,$2)/geo;
|
|
|
|
s/\bret\b/bx lr/o or
|
|
s/\bbx\s+lr\b/.word\t0xe12fff1e/o; # make it possible to compile with -march=armv4
|
|
|
|
print $_,$/;
|
|
}
|
|
|
|
close STDOUT; # enforce flush
|