1266 lines
38 KiB
C
1266 lines
38 KiB
C
/*-
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* Support for VIA PadLock Advanced Cryptography Engine (ACE)
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* Written by Michal Ludvig <michal@logix.cz>
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* http://www.logix.cz/michal
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*
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* Big thanks to Andy Polyakov for a help with optimization,
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* assembler fixes, port to MS Windows and a lot of other
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* valuable work on this engine!
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*/
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/* ====================================================================
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* Copyright (c) 1999-2001 The OpenSSL Project. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* 3. All advertising materials mentioning features or use of this
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* software must display the following acknowledgment:
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* "This product includes software developed by the OpenSSL Project
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* for use in the OpenSSL Toolkit. (http://www.OpenSSL.org/)"
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*
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* 4. The names "OpenSSL Toolkit" and "OpenSSL Project" must not be used to
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* endorse or promote products derived from this software without
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* prior written permission. For written permission, please contact
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* licensing@OpenSSL.org.
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*
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* 5. Products derived from this software may not be called "OpenSSL"
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* nor may "OpenSSL" appear in their names without prior written
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* permission of the OpenSSL Project.
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*
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* 6. Redistributions of any form whatsoever must retain the following
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* acknowledgment:
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* "This product includes software developed by the OpenSSL Project
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* for use in the OpenSSL Toolkit (http://www.OpenSSL.org/)"
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*
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* THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY
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* EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE OpenSSL PROJECT OR
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* ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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* ====================================================================
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*
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* This product includes cryptographic software written by Eric Young
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* (eay@cryptsoft.com). This product includes software written by Tim
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* Hudson (tjh@cryptsoft.com).
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*
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*/
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#include <stdio.h>
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#include <string.h>
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#include <openssl/opensslconf.h>
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#include <openssl/crypto.h>
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#include <openssl/dso.h>
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#include <openssl/engine.h>
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#include <openssl/evp.h>
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#ifndef OPENSSL_NO_AES
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# include <openssl/aes.h>
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#endif
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#include <openssl/rand.h>
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#include <openssl/err.h>
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#ifndef OPENSSL_NO_HW
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# ifndef OPENSSL_NO_HW_PADLOCK
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/* Attempt to have a single source for both 0.9.7 and 0.9.8 :-) */
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# if (OPENSSL_VERSION_NUMBER >= 0x00908000L)
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# ifndef OPENSSL_NO_DYNAMIC_ENGINE
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# define DYNAMIC_ENGINE
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# endif
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# elif (OPENSSL_VERSION_NUMBER >= 0x00907000L)
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# ifdef ENGINE_DYNAMIC_SUPPORT
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# define DYNAMIC_ENGINE
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# endif
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# else
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# error "Only OpenSSL >= 0.9.7 is supported"
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# endif
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/*
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* VIA PadLock AES is available *ONLY* on some x86 CPUs. Not only that it
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* doesn't exist elsewhere, but it even can't be compiled on other platforms!
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*
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* In addition, because of the heavy use of inline assembler, compiler choice
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* is limited to GCC and Microsoft C.
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*/
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# undef COMPILE_HW_PADLOCK
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# if !defined(I386_ONLY) && !defined(OPENSSL_NO_INLINE_ASM)
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# if (defined(__GNUC__) && (defined(__i386__) || defined(__i386))) || \
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(defined(_MSC_VER) && defined(_M_IX86))
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# define COMPILE_HW_PADLOCK
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# endif
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# endif
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# ifdef OPENSSL_NO_DYNAMIC_ENGINE
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# ifdef COMPILE_HW_PADLOCK
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static ENGINE *ENGINE_padlock(void);
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# endif
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void ENGINE_load_padlock(void)
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{
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/* On non-x86 CPUs it just returns. */
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# ifdef COMPILE_HW_PADLOCK
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ENGINE *toadd = ENGINE_padlock();
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if (!toadd)
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return;
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ENGINE_add(toadd);
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ENGINE_free(toadd);
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ERR_clear_error();
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# endif
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}
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# endif
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# ifdef COMPILE_HW_PADLOCK
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/*
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* We do these includes here to avoid header problems on platforms that do
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* not have the VIA padlock anyway...
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*/
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# include <stdlib.h>
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# ifdef _WIN32
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# include <malloc.h>
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# ifndef alloca
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# define alloca _alloca
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# endif
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# elif defined(__GNUC__)
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# ifndef alloca
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# define alloca(s) __builtin_alloca(s)
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# endif
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# endif
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/* Function for ENGINE detection and control */
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static int padlock_available(void);
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static int padlock_init(ENGINE *e);
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/* RNG Stuff */
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static RAND_METHOD padlock_rand;
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/* Cipher Stuff */
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# ifndef OPENSSL_NO_AES
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static int padlock_ciphers(ENGINE *e, const EVP_CIPHER **cipher,
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const int **nids, int nid);
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# endif
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/* Engine names */
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static const char *padlock_id = "padlock";
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static char padlock_name[100];
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/* Available features */
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static int padlock_use_ace = 0; /* Advanced Cryptography Engine */
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static int padlock_use_rng = 0; /* Random Number Generator */
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# ifndef OPENSSL_NO_AES
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static int padlock_aes_align_required = 1;
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# endif
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/* ===== Engine "management" functions ===== */
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/* Prepare the ENGINE structure for registration */
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static int padlock_bind_helper(ENGINE *e)
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{
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/* Check available features */
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padlock_available();
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# if 1 /* disable RNG for now, see commentary in
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* vicinity of RNG code */
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padlock_use_rng = 0;
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# endif
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/* Generate a nice engine name with available features */
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BIO_snprintf(padlock_name, sizeof(padlock_name),
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"VIA PadLock (%s, %s)",
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padlock_use_rng ? "RNG" : "no-RNG",
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padlock_use_ace ? "ACE" : "no-ACE");
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/* Register everything or return with an error */
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if (!ENGINE_set_id(e, padlock_id) ||
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!ENGINE_set_name(e, padlock_name) ||
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!ENGINE_set_init_function(e, padlock_init) ||
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# ifndef OPENSSL_NO_AES
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(padlock_use_ace && !ENGINE_set_ciphers(e, padlock_ciphers)) ||
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# endif
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(padlock_use_rng && !ENGINE_set_RAND(e, &padlock_rand))) {
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return 0;
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}
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/* Everything looks good */
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return 1;
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}
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# ifdef OPENSSL_NO_DYNAMIC_ENGINE
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/* Constructor */
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static ENGINE *ENGINE_padlock(void)
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{
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ENGINE *eng = ENGINE_new();
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if (!eng) {
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return NULL;
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}
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if (!padlock_bind_helper(eng)) {
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ENGINE_free(eng);
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return NULL;
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}
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return eng;
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}
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# endif
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/* Check availability of the engine */
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static int padlock_init(ENGINE *e)
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{
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return (padlock_use_rng || padlock_use_ace);
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}
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/*
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* This stuff is needed if this ENGINE is being compiled into a
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* self-contained shared-library.
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*/
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# ifdef DYNAMIC_ENGINE
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static int padlock_bind_fn(ENGINE *e, const char *id)
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{
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if (id && (strcmp(id, padlock_id) != 0)) {
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return 0;
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}
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if (!padlock_bind_helper(e)) {
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return 0;
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}
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return 1;
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}
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IMPLEMENT_DYNAMIC_CHECK_FN()
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IMPLEMENT_DYNAMIC_BIND_FN(padlock_bind_fn)
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# endif /* DYNAMIC_ENGINE */
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/* ===== Here comes the "real" engine ===== */
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# ifndef OPENSSL_NO_AES
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/* Some AES-related constants */
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# define AES_BLOCK_SIZE 16
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# define AES_KEY_SIZE_128 16
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# define AES_KEY_SIZE_192 24
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# define AES_KEY_SIZE_256 32
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/*
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* Here we store the status information relevant to the current context.
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*/
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/*
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* BIG FAT WARNING: Inline assembler in PADLOCK_XCRYPT_ASM() depends on
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* the order of items in this structure. Don't blindly modify, reorder,
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* etc!
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*/
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struct padlock_cipher_data {
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unsigned char iv[AES_BLOCK_SIZE]; /* Initialization vector */
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union {
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unsigned int pad[4];
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struct {
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int rounds:4;
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int dgst:1; /* n/a in C3 */
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int align:1; /* n/a in C3 */
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int ciphr:1; /* n/a in C3 */
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unsigned int keygen:1;
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int interm:1;
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unsigned int encdec:1;
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int ksize:2;
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} b;
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} cword; /* Control word */
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AES_KEY ks; /* Encryption key */
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};
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/*
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* Essentially this variable belongs in thread local storage.
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* Having this variable global on the other hand can only cause
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* few bogus key reloads [if any at all on single-CPU system],
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* so we accept the penatly...
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*/
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static volatile struct padlock_cipher_data *padlock_saved_context;
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# endif
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/*-
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* =======================================================
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* Inline assembler section(s).
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* =======================================================
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* Order of arguments is chosen to facilitate Windows port
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* using __fastcall calling convention. If you wish to add
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* more routines, keep in mind that first __fastcall
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* argument is passed in %ecx and second - in %edx.
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* =======================================================
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*/
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# if defined(__GNUC__) && __GNUC__>=2
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/*
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* As for excessive "push %ebx"/"pop %ebx" found all over.
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* When generating position-independent code GCC won't let
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* us use "b" in assembler templates nor even respect "ebx"
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* in "clobber description." Therefore the trouble...
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*/
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/*
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* Helper function - check if a CPUID instruction is available on this CPU
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*/
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static int padlock_insn_cpuid_available(void)
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{
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int result = -1;
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/*
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* We're checking if the bit #21 of EFLAGS can be toggled. If yes =
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* CPUID is available.
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*/
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asm volatile ("pushf\n"
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"popl %%eax\n"
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"xorl $0x200000, %%eax\n"
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"movl %%eax, %%ecx\n"
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"andl $0x200000, %%ecx\n"
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"pushl %%eax\n"
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"popf\n"
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"pushf\n"
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"popl %%eax\n"
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"andl $0x200000, %%eax\n"
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"xorl %%eax, %%ecx\n"
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"movl %%ecx, %0\n":"=r" (result)::"eax", "ecx");
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return (result == 0);
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}
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/*
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* Load supported features of the CPU to see if the PadLock is available.
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*/
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static int padlock_available(void)
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{
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char vendor_string[16];
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unsigned int eax, edx;
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/* First check if the CPUID instruction is available at all... */
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if (!padlock_insn_cpuid_available())
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return 0;
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/* Are we running on the Centaur (VIA) CPU? */
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eax = 0x00000000;
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vendor_string[12] = 0;
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asm volatile ("pushl %%ebx\n"
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"cpuid\n"
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"movl %%ebx,(%%edi)\n"
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"movl %%edx,4(%%edi)\n"
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"movl %%ecx,8(%%edi)\n"
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"popl %%ebx":"+a" (eax):"D"(vendor_string):"ecx", "edx");
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if (strcmp(vendor_string, "CentaurHauls") != 0)
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return 0;
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/* Check for Centaur Extended Feature Flags presence */
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eax = 0xC0000000;
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asm volatile ("pushl %%ebx; cpuid; popl %%ebx":"+a" (eax)::"ecx", "edx");
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if (eax < 0xC0000001)
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return 0;
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/* Read the Centaur Extended Feature Flags */
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eax = 0xC0000001;
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asm volatile ("pushl %%ebx; cpuid; popl %%ebx":"+a" (eax),
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"=d"(edx)::"ecx");
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/* Fill up some flags */
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padlock_use_ace = ((edx & (0x3 << 6)) == (0x3 << 6));
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padlock_use_rng = ((edx & (0x3 << 2)) == (0x3 << 2));
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return padlock_use_ace + padlock_use_rng;
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}
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# ifndef OPENSSL_NO_AES
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# ifndef AES_ASM
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/* Our own htonl()/ntohl() */
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static inline void padlock_bswapl(AES_KEY *ks)
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{
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size_t i = sizeof(ks->rd_key) / sizeof(ks->rd_key[0]);
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unsigned int *key = ks->rd_key;
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while (i--) {
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asm volatile ("bswapl %0":"+r" (*key));
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key++;
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}
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}
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# endif
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# endif
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/*
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* Force key reload from memory to the CPU microcode. Loading EFLAGS from the
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* stack clears EFLAGS[30] which does the trick.
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*/
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static inline void padlock_reload_key(void)
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{
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asm volatile ("pushfl; popfl");
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}
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# ifndef OPENSSL_NO_AES
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/*
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* This is heuristic key context tracing. At first one
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* believes that one should use atomic swap instructions,
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* but it's not actually necessary. Point is that if
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* padlock_saved_context was changed by another thread
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* after we've read it and before we compare it with cdata,
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* our key *shall* be reloaded upon thread context switch
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* and we are therefore set in either case...
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*/
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static inline void padlock_verify_context(struct padlock_cipher_data *cdata)
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{
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asm volatile ("pushfl\n"
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" btl $30,(%%esp)\n"
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" jnc 1f\n"
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" cmpl %2,%1\n"
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" je 1f\n"
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" popfl\n"
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" subl $4,%%esp\n"
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"1: addl $4,%%esp\n"
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" movl %2,%0":"+m" (padlock_saved_context)
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:"r"(padlock_saved_context), "r"(cdata):"cc");
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}
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|
|
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/* Template for padlock_xcrypt_* modes */
|
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/*
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* BIG FAT WARNING: The offsets used with 'leal' instructions describe items
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* of the 'padlock_cipher_data' structure.
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*/
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# define PADLOCK_XCRYPT_ASM(name,rep_xcrypt) \
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static inline void *name(size_t cnt, \
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struct padlock_cipher_data *cdata, \
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void *out, const void *inp) \
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{ void *iv; \
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asm volatile ( "pushl %%ebx\n" \
|
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" leal 16(%0),%%edx\n" \
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" leal 32(%0),%%ebx\n" \
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rep_xcrypt "\n" \
|
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" popl %%ebx" \
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: "=a"(iv), "=c"(cnt), "=D"(out), "=S"(inp) \
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: "0"(cdata), "1"(cnt), "2"(out), "3"(inp) \
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: "edx", "cc", "memory"); \
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return iv; \
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}
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|
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/* Generate all functions with appropriate opcodes */
|
|
/* rep xcryptecb */
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PADLOCK_XCRYPT_ASM(padlock_xcrypt_ecb, ".byte 0xf3,0x0f,0xa7,0xc8")
|
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/* rep xcryptcbc */
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PADLOCK_XCRYPT_ASM(padlock_xcrypt_cbc, ".byte 0xf3,0x0f,0xa7,0xd0")
|
|
/* rep xcryptcfb */
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PADLOCK_XCRYPT_ASM(padlock_xcrypt_cfb, ".byte 0xf3,0x0f,0xa7,0xe0")
|
|
/* rep xcryptofb */
|
|
PADLOCK_XCRYPT_ASM(padlock_xcrypt_ofb, ".byte 0xf3,0x0f,0xa7,0xe8")
|
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# endif
|
|
/* The RNG call itself */
|
|
static inline unsigned int padlock_xstore(void *addr, unsigned int edx_in)
|
|
{
|
|
unsigned int eax_out;
|
|
|
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asm volatile (".byte 0x0f,0xa7,0xc0" /* xstore */
|
|
:"=a" (eax_out), "=m"(*(unsigned *)addr)
|
|
:"D"(addr), "d"(edx_in)
|
|
);
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|
|
|
return eax_out;
|
|
}
|
|
|
|
/*
|
|
* Why not inline 'rep movsd'? I failed to find information on what value in
|
|
* Direction Flag one can expect and consequently have to apply
|
|
* "better-safe-than-sorry" approach and assume "undefined." I could
|
|
* explicitly clear it and restore the original value upon return from
|
|
* padlock_aes_cipher, but it's presumably too much trouble for too little
|
|
* gain... In case you wonder 'rep xcrypt*' instructions above are *not*
|
|
* affected by the Direction Flag and pointers advance toward larger
|
|
* addresses unconditionally.
|
|
*/
|
|
static inline unsigned char *padlock_memcpy(void *dst, const void *src,
|
|
size_t n)
|
|
{
|
|
long *d = dst;
|
|
const long *s = src;
|
|
|
|
n /= sizeof(*d);
|
|
do {
|
|
*d++ = *s++;
|
|
} while (--n);
|
|
|
|
return dst;
|
|
}
|
|
|
|
# elif defined(_MSC_VER)
|
|
/*
|
|
* Unlike GCC these are real functions. In order to minimize impact
|
|
* on performance we adhere to __fastcall calling convention in
|
|
* order to get two first arguments passed through %ecx and %edx.
|
|
* Which kind of suits very well, as instructions in question use
|
|
* both %ecx and %edx as input:-)
|
|
*/
|
|
# define REP_XCRYPT(code) \
|
|
_asm _emit 0xf3 \
|
|
_asm _emit 0x0f _asm _emit 0xa7 \
|
|
_asm _emit code
|
|
|
|
/*
|
|
* BIG FAT WARNING: The offsets used with 'lea' instructions describe items
|
|
* of the 'padlock_cipher_data' structure.
|
|
*/
|
|
# define PADLOCK_XCRYPT_ASM(name,code) \
|
|
static void * __fastcall \
|
|
name (size_t cnt, void *cdata, \
|
|
void *outp, const void *inp) \
|
|
{ _asm mov eax,edx \
|
|
_asm lea edx,[eax+16] \
|
|
_asm lea ebx,[eax+32] \
|
|
_asm mov edi,outp \
|
|
_asm mov esi,inp \
|
|
REP_XCRYPT(code) \
|
|
}
|
|
|
|
PADLOCK_XCRYPT_ASM(padlock_xcrypt_ecb,0xc8)
|
|
PADLOCK_XCRYPT_ASM(padlock_xcrypt_cbc,0xd0)
|
|
PADLOCK_XCRYPT_ASM(padlock_xcrypt_cfb,0xe0)
|
|
PADLOCK_XCRYPT_ASM(padlock_xcrypt_ofb,0xe8)
|
|
|
|
static int __fastcall padlock_xstore(void *outp, unsigned int code)
|
|
{
|
|
_asm mov edi,ecx
|
|
_asm _emit 0x0f _asm _emit 0xa7 _asm _emit 0xc0
|
|
}
|
|
|
|
static void __fastcall padlock_reload_key(void)
|
|
{
|
|
_asm pushfd
|
|
_asm popfd
|
|
}
|
|
|
|
static void __fastcall padlock_verify_context(void *cdata)
|
|
{
|
|
_asm {
|
|
pushfd
|
|
bt DWORD PTR[esp],30
|
|
jnc skip
|
|
cmp ecx,padlock_saved_context
|
|
je skip
|
|
popfd
|
|
sub esp,4
|
|
skip: add esp,4
|
|
mov padlock_saved_context,ecx
|
|
}
|
|
}
|
|
|
|
static int
|
|
padlock_available(void)
|
|
{
|
|
_asm {
|
|
pushfd
|
|
pop eax
|
|
mov ecx,eax
|
|
xor eax,1<<21
|
|
push eax
|
|
popfd
|
|
pushfd
|
|
pop eax
|
|
xor eax,ecx
|
|
bt eax,21
|
|
jnc noluck
|
|
mov eax,0
|
|
cpuid
|
|
xor eax,eax
|
|
cmp ebx,'tneC'
|
|
jne noluck
|
|
cmp edx,'Hrua'
|
|
jne noluck
|
|
cmp ecx,'slua'
|
|
jne noluck
|
|
mov eax,0xC0000000
|
|
cpuid
|
|
mov edx,eax
|
|
xor eax,eax
|
|
cmp edx,0xC0000001
|
|
jb noluck
|
|
mov eax,0xC0000001
|
|
cpuid
|
|
xor eax,eax
|
|
bt edx,6
|
|
jnc skip_a
|
|
bt edx,7
|
|
jnc skip_a
|
|
mov padlock_use_ace,1
|
|
inc eax
|
|
skip_a: bt edx,2
|
|
jnc skip_r
|
|
bt edx,3
|
|
jnc skip_r
|
|
mov padlock_use_rng,1
|
|
inc eax
|
|
skip_r:
|
|
noluck:
|
|
}
|
|
}
|
|
|
|
static void __fastcall padlock_bswapl(void *key)
|
|
{
|
|
_asm {
|
|
pushfd
|
|
cld
|
|
mov esi,ecx
|
|
mov edi,ecx
|
|
mov ecx,60
|
|
up: lodsd
|
|
bswap eax
|
|
stosd
|
|
loop up
|
|
popfd
|
|
}
|
|
}
|
|
|
|
/*
|
|
* MS actually specifies status of Direction Flag and compiler even manages
|
|
* to compile following as 'rep movsd' all by itself...
|
|
*/
|
|
# define padlock_memcpy(o,i,n) ((unsigned char *)memcpy((o),(i),(n)&~3U))
|
|
# endif
|
|
/* ===== AES encryption/decryption ===== */
|
|
# ifndef OPENSSL_NO_AES
|
|
# if defined(NID_aes_128_cfb128) && ! defined (NID_aes_128_cfb)
|
|
# define NID_aes_128_cfb NID_aes_128_cfb128
|
|
# endif
|
|
# if defined(NID_aes_128_ofb128) && ! defined (NID_aes_128_ofb)
|
|
# define NID_aes_128_ofb NID_aes_128_ofb128
|
|
# endif
|
|
# if defined(NID_aes_192_cfb128) && ! defined (NID_aes_192_cfb)
|
|
# define NID_aes_192_cfb NID_aes_192_cfb128
|
|
# endif
|
|
# if defined(NID_aes_192_ofb128) && ! defined (NID_aes_192_ofb)
|
|
# define NID_aes_192_ofb NID_aes_192_ofb128
|
|
# endif
|
|
# if defined(NID_aes_256_cfb128) && ! defined (NID_aes_256_cfb)
|
|
# define NID_aes_256_cfb NID_aes_256_cfb128
|
|
# endif
|
|
# if defined(NID_aes_256_ofb128) && ! defined (NID_aes_256_ofb)
|
|
# define NID_aes_256_ofb NID_aes_256_ofb128
|
|
# endif
|
|
/*
|
|
* List of supported ciphers.
|
|
*/ static int padlock_cipher_nids[] = {
|
|
NID_aes_128_ecb,
|
|
NID_aes_128_cbc,
|
|
NID_aes_128_cfb,
|
|
NID_aes_128_ofb,
|
|
|
|
NID_aes_192_ecb,
|
|
NID_aes_192_cbc,
|
|
NID_aes_192_cfb,
|
|
NID_aes_192_ofb,
|
|
|
|
NID_aes_256_ecb,
|
|
NID_aes_256_cbc,
|
|
NID_aes_256_cfb,
|
|
NID_aes_256_ofb,
|
|
};
|
|
|
|
static int padlock_cipher_nids_num = (sizeof(padlock_cipher_nids) /
|
|
sizeof(padlock_cipher_nids[0]));
|
|
|
|
/* Function prototypes ... */
|
|
static int padlock_aes_init_key(EVP_CIPHER_CTX *ctx, const unsigned char *key,
|
|
const unsigned char *iv, int enc);
|
|
static int padlock_aes_cipher(EVP_CIPHER_CTX *ctx, unsigned char *out,
|
|
const unsigned char *in, size_t nbytes);
|
|
|
|
# define NEAREST_ALIGNED(ptr) ( (unsigned char *)(ptr) + \
|
|
( (0x10 - ((size_t)(ptr) & 0x0F)) & 0x0F ) )
|
|
# define ALIGNED_CIPHER_DATA(ctx) ((struct padlock_cipher_data *)\
|
|
NEAREST_ALIGNED(ctx->cipher_data))
|
|
|
|
# define EVP_CIPHER_block_size_ECB AES_BLOCK_SIZE
|
|
# define EVP_CIPHER_block_size_CBC AES_BLOCK_SIZE
|
|
# define EVP_CIPHER_block_size_OFB 1
|
|
# define EVP_CIPHER_block_size_CFB 1
|
|
|
|
/*
|
|
* Declaring so many ciphers by hand would be a pain. Instead introduce a bit
|
|
* of preprocessor magic :-)
|
|
*/
|
|
# define DECLARE_AES_EVP(ksize,lmode,umode) \
|
|
static const EVP_CIPHER padlock_aes_##ksize##_##lmode = { \
|
|
NID_aes_##ksize##_##lmode, \
|
|
EVP_CIPHER_block_size_##umode, \
|
|
AES_KEY_SIZE_##ksize, \
|
|
AES_BLOCK_SIZE, \
|
|
0 | EVP_CIPH_##umode##_MODE, \
|
|
padlock_aes_init_key, \
|
|
padlock_aes_cipher, \
|
|
NULL, \
|
|
sizeof(struct padlock_cipher_data) + 16, \
|
|
EVP_CIPHER_set_asn1_iv, \
|
|
EVP_CIPHER_get_asn1_iv, \
|
|
NULL, \
|
|
NULL \
|
|
}
|
|
|
|
DECLARE_AES_EVP(128, ecb, ECB);
|
|
DECLARE_AES_EVP(128, cbc, CBC);
|
|
DECLARE_AES_EVP(128, cfb, CFB);
|
|
DECLARE_AES_EVP(128, ofb, OFB);
|
|
|
|
DECLARE_AES_EVP(192, ecb, ECB);
|
|
DECLARE_AES_EVP(192, cbc, CBC);
|
|
DECLARE_AES_EVP(192, cfb, CFB);
|
|
DECLARE_AES_EVP(192, ofb, OFB);
|
|
|
|
DECLARE_AES_EVP(256, ecb, ECB);
|
|
DECLARE_AES_EVP(256, cbc, CBC);
|
|
DECLARE_AES_EVP(256, cfb, CFB);
|
|
DECLARE_AES_EVP(256, ofb, OFB);
|
|
|
|
static int
|
|
padlock_ciphers(ENGINE *e, const EVP_CIPHER **cipher, const int **nids,
|
|
int nid)
|
|
{
|
|
/* No specific cipher => return a list of supported nids ... */
|
|
if (!cipher) {
|
|
*nids = padlock_cipher_nids;
|
|
return padlock_cipher_nids_num;
|
|
}
|
|
|
|
/* ... or the requested "cipher" otherwise */
|
|
switch (nid) {
|
|
case NID_aes_128_ecb:
|
|
*cipher = &padlock_aes_128_ecb;
|
|
break;
|
|
case NID_aes_128_cbc:
|
|
*cipher = &padlock_aes_128_cbc;
|
|
break;
|
|
case NID_aes_128_cfb:
|
|
*cipher = &padlock_aes_128_cfb;
|
|
break;
|
|
case NID_aes_128_ofb:
|
|
*cipher = &padlock_aes_128_ofb;
|
|
break;
|
|
|
|
case NID_aes_192_ecb:
|
|
*cipher = &padlock_aes_192_ecb;
|
|
break;
|
|
case NID_aes_192_cbc:
|
|
*cipher = &padlock_aes_192_cbc;
|
|
break;
|
|
case NID_aes_192_cfb:
|
|
*cipher = &padlock_aes_192_cfb;
|
|
break;
|
|
case NID_aes_192_ofb:
|
|
*cipher = &padlock_aes_192_ofb;
|
|
break;
|
|
|
|
case NID_aes_256_ecb:
|
|
*cipher = &padlock_aes_256_ecb;
|
|
break;
|
|
case NID_aes_256_cbc:
|
|
*cipher = &padlock_aes_256_cbc;
|
|
break;
|
|
case NID_aes_256_cfb:
|
|
*cipher = &padlock_aes_256_cfb;
|
|
break;
|
|
case NID_aes_256_ofb:
|
|
*cipher = &padlock_aes_256_ofb;
|
|
break;
|
|
|
|
default:
|
|
/* Sorry, we don't support this NID */
|
|
*cipher = NULL;
|
|
return 0;
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
|
|
/* Prepare the encryption key for PadLock usage */
|
|
static int
|
|
padlock_aes_init_key(EVP_CIPHER_CTX *ctx, const unsigned char *key,
|
|
const unsigned char *iv, int enc)
|
|
{
|
|
struct padlock_cipher_data *cdata;
|
|
int key_len = EVP_CIPHER_CTX_key_length(ctx) * 8;
|
|
|
|
if (key == NULL)
|
|
return 0; /* ERROR */
|
|
|
|
cdata = ALIGNED_CIPHER_DATA(ctx);
|
|
memset(cdata, 0, sizeof(struct padlock_cipher_data));
|
|
|
|
/* Prepare Control word. */
|
|
if (EVP_CIPHER_CTX_mode(ctx) == EVP_CIPH_OFB_MODE)
|
|
cdata->cword.b.encdec = 0;
|
|
else
|
|
cdata->cword.b.encdec = (ctx->encrypt == 0);
|
|
cdata->cword.b.rounds = 10 + (key_len - 128) / 32;
|
|
cdata->cword.b.ksize = (key_len - 128) / 64;
|
|
|
|
switch (key_len) {
|
|
case 128:
|
|
/*
|
|
* PadLock can generate an extended key for AES128 in hardware
|
|
*/
|
|
memcpy(cdata->ks.rd_key, key, AES_KEY_SIZE_128);
|
|
cdata->cword.b.keygen = 0;
|
|
break;
|
|
|
|
case 192:
|
|
case 256:
|
|
/*
|
|
* Generate an extended AES key in software. Needed for AES192/AES256
|
|
*/
|
|
/*
|
|
* Well, the above applies to Stepping 8 CPUs and is listed as
|
|
* hardware errata. They most likely will fix it at some point and
|
|
* then a check for stepping would be due here.
|
|
*/
|
|
if (EVP_CIPHER_CTX_mode(ctx) == EVP_CIPH_CFB_MODE ||
|
|
EVP_CIPHER_CTX_mode(ctx) == EVP_CIPH_OFB_MODE || enc)
|
|
AES_set_encrypt_key(key, key_len, &cdata->ks);
|
|
else
|
|
AES_set_decrypt_key(key, key_len, &cdata->ks);
|
|
# ifndef AES_ASM
|
|
/*
|
|
* OpenSSL C functions use byte-swapped extended key.
|
|
*/
|
|
padlock_bswapl(&cdata->ks);
|
|
# endif
|
|
cdata->cword.b.keygen = 1;
|
|
break;
|
|
|
|
default:
|
|
/* ERROR */
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* This is done to cover for cases when user reuses the
|
|
* context for new key. The catch is that if we don't do
|
|
* this, padlock_eas_cipher might proceed with old key...
|
|
*/
|
|
padlock_reload_key();
|
|
|
|
return 1;
|
|
}
|
|
|
|
/*-
|
|
* Simplified version of padlock_aes_cipher() used when
|
|
* 1) both input and output buffers are at aligned addresses.
|
|
* or when
|
|
* 2) running on a newer CPU that doesn't require aligned buffers.
|
|
*/
|
|
static int
|
|
padlock_aes_cipher_omnivorous(EVP_CIPHER_CTX *ctx, unsigned char *out_arg,
|
|
const unsigned char *in_arg, size_t nbytes)
|
|
{
|
|
struct padlock_cipher_data *cdata;
|
|
void *iv;
|
|
|
|
cdata = ALIGNED_CIPHER_DATA(ctx);
|
|
padlock_verify_context(cdata);
|
|
|
|
switch (EVP_CIPHER_CTX_mode(ctx)) {
|
|
case EVP_CIPH_ECB_MODE:
|
|
padlock_xcrypt_ecb(nbytes / AES_BLOCK_SIZE, cdata, out_arg, in_arg);
|
|
break;
|
|
|
|
case EVP_CIPH_CBC_MODE:
|
|
memcpy(cdata->iv, ctx->iv, AES_BLOCK_SIZE);
|
|
iv = padlock_xcrypt_cbc(nbytes / AES_BLOCK_SIZE, cdata, out_arg,
|
|
in_arg);
|
|
memcpy(ctx->iv, iv, AES_BLOCK_SIZE);
|
|
break;
|
|
|
|
case EVP_CIPH_CFB_MODE:
|
|
memcpy(cdata->iv, ctx->iv, AES_BLOCK_SIZE);
|
|
iv = padlock_xcrypt_cfb(nbytes / AES_BLOCK_SIZE, cdata, out_arg,
|
|
in_arg);
|
|
memcpy(ctx->iv, iv, AES_BLOCK_SIZE);
|
|
break;
|
|
|
|
case EVP_CIPH_OFB_MODE:
|
|
memcpy(cdata->iv, ctx->iv, AES_BLOCK_SIZE);
|
|
padlock_xcrypt_ofb(nbytes / AES_BLOCK_SIZE, cdata, out_arg, in_arg);
|
|
memcpy(ctx->iv, cdata->iv, AES_BLOCK_SIZE);
|
|
break;
|
|
|
|
default:
|
|
return 0;
|
|
}
|
|
|
|
memset(cdata->iv, 0, AES_BLOCK_SIZE);
|
|
|
|
return 1;
|
|
}
|
|
|
|
# ifndef PADLOCK_CHUNK
|
|
# define PADLOCK_CHUNK 512 /* Must be a power of 2 larger than 16 */
|
|
# endif
|
|
# if PADLOCK_CHUNK<16 || PADLOCK_CHUNK&(PADLOCK_CHUNK-1)
|
|
# error "insane PADLOCK_CHUNK..."
|
|
# endif
|
|
|
|
/*
|
|
* Re-align the arguments to 16-Bytes boundaries and run the encryption
|
|
* function itself. This function is not AES-specific.
|
|
*/
|
|
static int
|
|
padlock_aes_cipher(EVP_CIPHER_CTX *ctx, unsigned char *out_arg,
|
|
const unsigned char *in_arg, size_t nbytes)
|
|
{
|
|
struct padlock_cipher_data *cdata;
|
|
const void *inp;
|
|
unsigned char *out;
|
|
void *iv;
|
|
int inp_misaligned, out_misaligned, realign_in_loop;
|
|
size_t chunk, allocated = 0;
|
|
|
|
/*
|
|
* ctx->num is maintained in byte-oriented modes, such as CFB and OFB...
|
|
*/
|
|
if ((chunk = ctx->num)) { /* borrow chunk variable */
|
|
unsigned char *ivp = ctx->iv;
|
|
|
|
switch (EVP_CIPHER_CTX_mode(ctx)) {
|
|
case EVP_CIPH_CFB_MODE:
|
|
if (chunk >= AES_BLOCK_SIZE)
|
|
return 0; /* bogus value */
|
|
|
|
if (ctx->encrypt)
|
|
while (chunk < AES_BLOCK_SIZE && nbytes != 0) {
|
|
ivp[chunk] = *(out_arg++) = *(in_arg++) ^ ivp[chunk];
|
|
chunk++, nbytes--;
|
|
} else
|
|
while (chunk < AES_BLOCK_SIZE && nbytes != 0) {
|
|
unsigned char c = *(in_arg++);
|
|
*(out_arg++) = c ^ ivp[chunk];
|
|
ivp[chunk++] = c, nbytes--;
|
|
}
|
|
|
|
ctx->num = chunk % AES_BLOCK_SIZE;
|
|
break;
|
|
case EVP_CIPH_OFB_MODE:
|
|
if (chunk >= AES_BLOCK_SIZE)
|
|
return 0; /* bogus value */
|
|
|
|
while (chunk < AES_BLOCK_SIZE && nbytes != 0) {
|
|
*(out_arg++) = *(in_arg++) ^ ivp[chunk];
|
|
chunk++, nbytes--;
|
|
}
|
|
|
|
ctx->num = chunk % AES_BLOCK_SIZE;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (nbytes == 0)
|
|
return 1;
|
|
# if 0
|
|
if (nbytes % AES_BLOCK_SIZE)
|
|
return 0; /* are we expected to do tail processing? */
|
|
# else
|
|
/*
|
|
* nbytes is always multiple of AES_BLOCK_SIZE in ECB and CBC modes and
|
|
* arbitrary value in byte-oriented modes, such as CFB and OFB...
|
|
*/
|
|
# endif
|
|
|
|
/*
|
|
* VIA promises CPUs that won't require alignment in the future. For now
|
|
* padlock_aes_align_required is initialized to 1 and the condition is
|
|
* never met...
|
|
*/
|
|
/*
|
|
* C7 core is capable to manage unaligned input in non-ECB[!] mode, but
|
|
* performance penalties appear to be approximately same as for software
|
|
* alignment below or ~3x. They promise to improve it in the future, but
|
|
* for now we can just as well pretend that it can only handle aligned
|
|
* input...
|
|
*/
|
|
if (!padlock_aes_align_required && (nbytes % AES_BLOCK_SIZE) == 0)
|
|
return padlock_aes_cipher_omnivorous(ctx, out_arg, in_arg, nbytes);
|
|
|
|
inp_misaligned = (((size_t)in_arg) & 0x0F);
|
|
out_misaligned = (((size_t)out_arg) & 0x0F);
|
|
|
|
/*
|
|
* Note that even if output is aligned and input not, I still prefer to
|
|
* loop instead of copy the whole input and then encrypt in one stroke.
|
|
* This is done in order to improve L1 cache utilization...
|
|
*/
|
|
realign_in_loop = out_misaligned | inp_misaligned;
|
|
|
|
if (!realign_in_loop && (nbytes % AES_BLOCK_SIZE) == 0)
|
|
return padlock_aes_cipher_omnivorous(ctx, out_arg, in_arg, nbytes);
|
|
|
|
/* this takes one "if" out of the loops */
|
|
chunk = nbytes;
|
|
chunk %= PADLOCK_CHUNK;
|
|
if (chunk == 0)
|
|
chunk = PADLOCK_CHUNK;
|
|
|
|
if (out_misaligned) {
|
|
/* optmize for small input */
|
|
allocated = (chunk < nbytes ? PADLOCK_CHUNK : nbytes);
|
|
out = alloca(0x10 + allocated);
|
|
out = NEAREST_ALIGNED(out);
|
|
} else
|
|
out = out_arg;
|
|
|
|
cdata = ALIGNED_CIPHER_DATA(ctx);
|
|
padlock_verify_context(cdata);
|
|
|
|
switch (EVP_CIPHER_CTX_mode(ctx)) {
|
|
case EVP_CIPH_ECB_MODE:
|
|
do {
|
|
if (inp_misaligned)
|
|
inp = padlock_memcpy(out, in_arg, chunk);
|
|
else
|
|
inp = in_arg;
|
|
in_arg += chunk;
|
|
|
|
padlock_xcrypt_ecb(chunk / AES_BLOCK_SIZE, cdata, out, inp);
|
|
|
|
if (out_misaligned)
|
|
out_arg = padlock_memcpy(out_arg, out, chunk) + chunk;
|
|
else
|
|
out = out_arg += chunk;
|
|
|
|
nbytes -= chunk;
|
|
chunk = PADLOCK_CHUNK;
|
|
} while (nbytes);
|
|
break;
|
|
|
|
case EVP_CIPH_CBC_MODE:
|
|
memcpy(cdata->iv, ctx->iv, AES_BLOCK_SIZE);
|
|
goto cbc_shortcut;
|
|
do {
|
|
if (iv != cdata->iv)
|
|
memcpy(cdata->iv, iv, AES_BLOCK_SIZE);
|
|
chunk = PADLOCK_CHUNK;
|
|
cbc_shortcut: /* optimize for small input */
|
|
if (inp_misaligned)
|
|
inp = padlock_memcpy(out, in_arg, chunk);
|
|
else
|
|
inp = in_arg;
|
|
in_arg += chunk;
|
|
|
|
iv = padlock_xcrypt_cbc(chunk / AES_BLOCK_SIZE, cdata, out, inp);
|
|
|
|
if (out_misaligned)
|
|
out_arg = padlock_memcpy(out_arg, out, chunk) + chunk;
|
|
else
|
|
out = out_arg += chunk;
|
|
|
|
} while (nbytes -= chunk);
|
|
memcpy(ctx->iv, iv, AES_BLOCK_SIZE);
|
|
break;
|
|
|
|
case EVP_CIPH_CFB_MODE:
|
|
memcpy(iv = cdata->iv, ctx->iv, AES_BLOCK_SIZE);
|
|
chunk &= ~(AES_BLOCK_SIZE - 1);
|
|
if (chunk)
|
|
goto cfb_shortcut;
|
|
else
|
|
goto cfb_skiploop;
|
|
do {
|
|
if (iv != cdata->iv)
|
|
memcpy(cdata->iv, iv, AES_BLOCK_SIZE);
|
|
chunk = PADLOCK_CHUNK;
|
|
cfb_shortcut: /* optimize for small input */
|
|
if (inp_misaligned)
|
|
inp = padlock_memcpy(out, in_arg, chunk);
|
|
else
|
|
inp = in_arg;
|
|
in_arg += chunk;
|
|
|
|
iv = padlock_xcrypt_cfb(chunk / AES_BLOCK_SIZE, cdata, out, inp);
|
|
|
|
if (out_misaligned)
|
|
out_arg = padlock_memcpy(out_arg, out, chunk) + chunk;
|
|
else
|
|
out = out_arg += chunk;
|
|
|
|
nbytes -= chunk;
|
|
} while (nbytes >= AES_BLOCK_SIZE);
|
|
|
|
cfb_skiploop:
|
|
if (nbytes) {
|
|
unsigned char *ivp = cdata->iv;
|
|
|
|
if (iv != ivp) {
|
|
memcpy(ivp, iv, AES_BLOCK_SIZE);
|
|
iv = ivp;
|
|
}
|
|
ctx->num = nbytes;
|
|
if (cdata->cword.b.encdec) {
|
|
cdata->cword.b.encdec = 0;
|
|
padlock_reload_key();
|
|
padlock_xcrypt_ecb(1, cdata, ivp, ivp);
|
|
cdata->cword.b.encdec = 1;
|
|
padlock_reload_key();
|
|
while (nbytes) {
|
|
unsigned char c = *(in_arg++);
|
|
*(out_arg++) = c ^ *ivp;
|
|
*(ivp++) = c, nbytes--;
|
|
}
|
|
} else {
|
|
padlock_reload_key();
|
|
padlock_xcrypt_ecb(1, cdata, ivp, ivp);
|
|
padlock_reload_key();
|
|
while (nbytes) {
|
|
*ivp = *(out_arg++) = *(in_arg++) ^ *ivp;
|
|
ivp++, nbytes--;
|
|
}
|
|
}
|
|
}
|
|
|
|
memcpy(ctx->iv, iv, AES_BLOCK_SIZE);
|
|
break;
|
|
|
|
case EVP_CIPH_OFB_MODE:
|
|
memcpy(cdata->iv, ctx->iv, AES_BLOCK_SIZE);
|
|
chunk &= ~(AES_BLOCK_SIZE - 1);
|
|
if (chunk)
|
|
do {
|
|
if (inp_misaligned)
|
|
inp = padlock_memcpy(out, in_arg, chunk);
|
|
else
|
|
inp = in_arg;
|
|
in_arg += chunk;
|
|
|
|
padlock_xcrypt_ofb(chunk / AES_BLOCK_SIZE, cdata, out, inp);
|
|
|
|
if (out_misaligned)
|
|
out_arg = padlock_memcpy(out_arg, out, chunk) + chunk;
|
|
else
|
|
out = out_arg += chunk;
|
|
|
|
nbytes -= chunk;
|
|
chunk = PADLOCK_CHUNK;
|
|
} while (nbytes >= AES_BLOCK_SIZE);
|
|
|
|
if (nbytes) {
|
|
unsigned char *ivp = cdata->iv;
|
|
|
|
ctx->num = nbytes;
|
|
padlock_reload_key(); /* empirically found */
|
|
padlock_xcrypt_ecb(1, cdata, ivp, ivp);
|
|
padlock_reload_key(); /* empirically found */
|
|
while (nbytes) {
|
|
*(out_arg++) = *(in_arg++) ^ *ivp;
|
|
ivp++, nbytes--;
|
|
}
|
|
}
|
|
|
|
memcpy(ctx->iv, cdata->iv, AES_BLOCK_SIZE);
|
|
break;
|
|
|
|
default:
|
|
return 0;
|
|
}
|
|
|
|
/* Clean the realign buffer if it was used */
|
|
if (out_misaligned) {
|
|
volatile unsigned long *p = (void *)out;
|
|
size_t n = allocated / sizeof(*p);
|
|
while (n--)
|
|
*p++ = 0;
|
|
}
|
|
|
|
memset(cdata->iv, 0, AES_BLOCK_SIZE);
|
|
|
|
return 1;
|
|
}
|
|
|
|
# endif /* OPENSSL_NO_AES */
|
|
|
|
/* ===== Random Number Generator ===== */
|
|
/*
|
|
* This code is not engaged. The reason is that it does not comply
|
|
* with recommendations for VIA RNG usage for secure applications
|
|
* (posted at http://www.via.com.tw/en/viac3/c3.jsp) nor does it
|
|
* provide meaningful error control...
|
|
*/
|
|
/*
|
|
* Wrapper that provides an interface between the API and the raw PadLock
|
|
* RNG
|
|
*/
|
|
static int padlock_rand_bytes(unsigned char *output, int count)
|
|
{
|
|
unsigned int eax, buf;
|
|
|
|
while (count >= 8) {
|
|
eax = padlock_xstore(output, 0);
|
|
if (!(eax & (1 << 6)))
|
|
return 0; /* RNG disabled */
|
|
/* this ---vv--- covers DC bias, Raw Bits and String Filter */
|
|
if (eax & (0x1F << 10))
|
|
return 0;
|
|
if ((eax & 0x1F) == 0)
|
|
continue; /* no data, retry... */
|
|
if ((eax & 0x1F) != 8)
|
|
return 0; /* fatal failure... */
|
|
output += 8;
|
|
count -= 8;
|
|
}
|
|
while (count > 0) {
|
|
eax = padlock_xstore(&buf, 3);
|
|
if (!(eax & (1 << 6)))
|
|
return 0; /* RNG disabled */
|
|
/* this ---vv--- covers DC bias, Raw Bits and String Filter */
|
|
if (eax & (0x1F << 10))
|
|
return 0;
|
|
if ((eax & 0x1F) == 0)
|
|
continue; /* no data, retry... */
|
|
if ((eax & 0x1F) != 1)
|
|
return 0; /* fatal failure... */
|
|
*output++ = (unsigned char)buf;
|
|
count--;
|
|
}
|
|
*(volatile unsigned int *)&buf = 0;
|
|
|
|
return 1;
|
|
}
|
|
|
|
/* Dummy but necessary function */
|
|
static int padlock_rand_status(void)
|
|
{
|
|
return 1;
|
|
}
|
|
|
|
/* Prepare structure for registration */
|
|
static RAND_METHOD padlock_rand = {
|
|
NULL, /* seed */
|
|
padlock_rand_bytes, /* bytes */
|
|
NULL, /* cleanup */
|
|
NULL, /* add */
|
|
padlock_rand_bytes, /* pseudorand */
|
|
padlock_rand_status, /* rand status */
|
|
};
|
|
|
|
# else /* !COMPILE_HW_PADLOCK */
|
|
# ifndef OPENSSL_NO_DYNAMIC_ENGINE
|
|
OPENSSL_EXPORT
|
|
int bind_engine(ENGINE *e, const char *id, const dynamic_fns *fns);
|
|
OPENSSL_EXPORT
|
|
int bind_engine(ENGINE *e, const char *id, const dynamic_fns *fns)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
IMPLEMENT_DYNAMIC_CHECK_FN()
|
|
# endif
|
|
# endif /* COMPILE_HW_PADLOCK */
|
|
# endif /* !OPENSSL_NO_HW_PADLOCK */
|
|
#endif /* !OPENSSL_NO_HW */
|