159 lines
5.8 KiB
ArmAsm
159 lines
5.8 KiB
ArmAsm
// ====================================================================
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// Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
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// project.
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//
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// Rights for redistribution and usage in source and binary forms are
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// granted according to the OpenSSL license. Warranty of any kind is
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// disclaimed.
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// ====================================================================
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.ident "rc4-ia64.S, Version 2.0"
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.ident "IA-64 ISA artwork by Andy Polyakov <appro@fy.chalmers.se>"
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// What's wrong with compiler generated code? Because of the nature of
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// C language, compiler doesn't [dare to] reorder load and stores. But
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// being memory-bound, RC4 should benefit from reorder [on in-order-
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// execution core such as IA-64]. But what can we reorder? At the very
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// least we can safely reorder references to key schedule in respect
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// to input and output streams. Secondly, from the first [close] glance
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// it appeared that it's possible to pull up some references to
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// elements of the key schedule itself. Original rationale ["prior
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// loads are not safe only for "degenerated" key schedule, when some
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// elements equal to the same value"] was kind of sloppy. I should have
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// formulated as it really was: if we assume that pulling up reference
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// to key[x+1] is not safe, then it would mean that key schedule would
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// "degenerate," which is never the case. The problem is that this
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// holds true in respect to references to key[x], but not to key[y].
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// Legitimate "collisions" do occur within every 256^2 bytes window.
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// Fortunately there're enough free instruction slots to keep prior
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// reference to key[x+1], detect "collision" and compensate for it.
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// All this without sacrificing a single clock cycle:-) Throughput is
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// ~210MBps on 900MHz CPU, which is is >3x faster than gcc generated
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// code and +30% - if compared to HP-UX C. Unrolling loop below should
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// give >30% on top of that...
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.text
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.explicit
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#if defined(_HPUX_SOURCE) && !defined(_LP64)
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# define ADDP addp4
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#else
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# define ADDP add
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#endif
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#ifndef SZ
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#define SZ 4 // this is set to sizeof(RC4_INT)
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#endif
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// SZ==4 seems to be optimal. At least SZ==8 is not any faster, not for
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// assembler implementation, while SZ==1 code is ~30% slower.
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#if SZ==1 // RC4_INT is unsigned char
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# define LDKEY ld1
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# define STKEY st1
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# define OFF 0
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#elif SZ==4 // RC4_INT is unsigned int
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# define LDKEY ld4
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# define STKEY st4
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# define OFF 2
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#elif SZ==8 // RC4_INT is unsigned long
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# define LDKEY ld8
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# define STKEY st8
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# define OFF 3
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#endif
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out=r8; // [expanded] output pointer
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inp=r9; // [expanded] output pointer
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prsave=r10;
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key=r28; // [expanded] pointer to RC4_KEY
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ksch=r29; // (key->data+255)[&~(sizeof(key->data)-1)]
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xx=r30;
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yy=r31;
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// void RC4(RC4_KEY *key,size_t len,const void *inp,void *out);
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.global RC4#
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.proc RC4#
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.align 32
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.skip 16
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RC4:
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.prologue
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.save ar.pfs,r2
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{ .mii; alloc r2=ar.pfs,4,12,0,16
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.save pr,prsave
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mov prsave=pr
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ADDP key=0,in0 };;
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{ .mib; cmp.eq p6,p0=0,in1 // len==0?
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.save ar.lc,r3
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mov r3=ar.lc
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(p6) br.ret.spnt.many b0 };; // emergency exit
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.body
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.rotr dat[4],key_x[4],tx[2],rnd[2],key_y[2],ty[1];
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{ .mib; LDKEY xx=[key],SZ // load key->x
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add in1=-1,in1 // adjust len for loop counter
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nop.b 0 }
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{ .mib; ADDP inp=0,in2
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ADDP out=0,in3
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brp.loop.imp .Ltop,.Lexit-16 };;
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{ .mmi; LDKEY yy=[key] // load key->y
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add ksch=SZ,key
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mov ar.lc=in1 }
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{ .mmi; mov key_y[1]=r0 // guarantee inequality
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// in first iteration
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add xx=1,xx
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mov pr.rot=1<<16 };;
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{ .mii; nop.m 0
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dep key_x[1]=xx,r0,OFF,8
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mov ar.ec=3 };; // note that epilogue counter
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// is off by 1. I compensate
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// for this at exit...
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.Ltop:
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// The loop is scheduled for 4*(n+2) spin-rate on Itanium 2, which
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// theoretically gives asymptotic performance of clock frequency
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// divided by 4 bytes per seconds, or 400MBps on 1.6GHz CPU. This is
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// for sizeof(RC4_INT)==4. For smaller RC4_INT STKEY inadvertently
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// splits the last bundle and you end up with 5*n spin-rate:-(
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// Originally the loop was scheduled for 3*n and relied on key
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// schedule to be aligned at 256*sizeof(RC4_INT) boundary. But
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// *(out++)=dat, which maps to st1, had same effect [inadvertent
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// bundle split] and holded the loop back. Rescheduling for 4*n
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// made it possible to eliminate dependence on specific alignment
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// and allow OpenSSH keep "abusing" our API. Reaching for 3*n would
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// require unrolling, sticking to variable shift instruction for
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// collecting output [to avoid starvation for integer shifter] and
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// copying of key schedule to controlled place in stack [so that
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// deposit instruction can serve as substitute for whole
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// key->data+((x&255)<<log2(sizeof(key->data[0])))]...
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{ .mmi; (p19) st1 [out]=dat[3],1 // *(out++)=dat
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(p16) add xx=1,xx // x++
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(p18) dep rnd[1]=rnd[1],r0,OFF,8 } // ((tx+ty)&255)<<OFF
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{ .mmi; (p16) add key_x[1]=ksch,key_x[1] // &key[xx&255]
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(p17) add key_y[1]=ksch,key_y[1] };; // &key[yy&255]
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{ .mmi; (p16) LDKEY tx[0]=[key_x[1]] // tx=key[xx]
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(p17) LDKEY ty[0]=[key_y[1]] // ty=key[yy]
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(p16) dep key_x[0]=xx,r0,OFF,8 } // (xx&255)<<OFF
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{ .mmi; (p18) add rnd[1]=ksch,rnd[1] // &key[(tx+ty)&255]
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(p16) cmp.ne.unc p20,p21=key_x[1],key_y[1] };;
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{ .mmi; (p18) LDKEY rnd[1]=[rnd[1]] // rnd=key[(tx+ty)&255]
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(p16) ld1 dat[0]=[inp],1 } // dat=*(inp++)
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.pred.rel "mutex",p20,p21
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{ .mmi; (p21) add yy=yy,tx[1] // (p16)
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(p20) add yy=yy,tx[0] // (p16) y+=tx
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(p21) mov tx[0]=tx[1] };; // (p16)
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{ .mmi; (p17) STKEY [key_y[1]]=tx[1] // key[yy]=tx
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(p17) STKEY [key_x[2]]=ty[0] // key[xx]=ty
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(p16) dep key_y[0]=yy,r0,OFF,8 } // &key[yy&255]
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{ .mmb; (p17) add rnd[0]=tx[1],ty[0] // tx+=ty
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(p18) xor dat[2]=dat[2],rnd[1] // dat^=rnd
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br.ctop.sptk .Ltop };;
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.Lexit:
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{ .mib; STKEY [key]=yy,-SZ // save key->y
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mov pr=prsave,0x1ffff
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nop.b 0 }
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{ .mib; st1 [out]=dat[3],1 // compensate for truncated
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// epilogue counter
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add xx=-1,xx
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nop.b 0 };;
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{ .mib; STKEY [key]=xx // save key->x
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mov ar.lc=r3
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br.ret.sptk.many b0 };;
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.endp RC4#
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